Digitally adjustable resistors in CMOS for high-performance applications

I I76

Digitally Adjustable IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 21, NO. 8, AUGUST 1992

Resistors in CMOS for High-Performance Applications

Thaddeus J. Gabara, Member, IEEE, and Scott C. Knauer, Member, IEEE

Abstract-This paper describes how CMOS circuits can be adjusted digitally to generate controlled impedances for use in high-performance circuits. Since digital signals are the only in- puts to these circuits, on-chip dc power dissipation can be reduced, the circuit can be made more robust, and the impedance of the circuit can be adjusted by manipulating the input digital information. In particular, a design of a CMOS series terminated line driver is discussed. Also described is the utilization of how this controlled impedance could be used in terminating transmission lines on-chip, constant delay lines, and controlled dildt output buffers.

I. INTRODUCTION HE I /O of CMOS chips has been a bottleneck for T high-performance applications. Although the design

rules of CMOS have been steadily shrinking, on-chip performance has scaled while off-chip performance capabil- ities have generally remained the same. Issues such as slew-rate control, ESD protection, and simultaneously switching buffers act to stagnate off-chip performance. Improvements in performance in this 110 bottleneck have been made [1]-[3], but the penalties are the requirement of external resistors to terminate all transmission lines and/or the increased on-chip dc power dissipation associated with these networks.

CMOS series terminated line drivers can reduce the dc power dissipation of the output buffer to zero. Series terminated drivers have an impedance which matches the transmission line being driven. This impedance is formed from a transistor whose width is adjusted by digital means. Fig. 1 illustrates the desired circuit characteristics for series terminated line drivers. The far end of the transmission line is left unterminated while an impedance equivalent to that of the transmission line is used to pull up or pull down the voltage on the line. The values of the two power supplies are 0 V and VLs, where V,, is less than 0 V. Once IN enables the bottom switch, a forward wave of half the voltage swing propagates down the line. The wave is reflected back when it reaches the end of the line. This backward wave of -1 /2 the voltage swing super- imposes over the forward wave to produce a full voltage swing. The backward wave is fully absorbed in the matching impedance of the driving buffer. This type of network is ideal for a single-receiver single-transmitter system.

Manuscript received July 22, 1991; revised March 12, 1992. The authors are with AT&T Bell Laboratories, Murray Hill, NJ 07974. IEEE Log Number 9200641.

I -2v ( V W

Fig. 1 . Ideal series terminated buffer

A method of utilizing analog techniques to create CMOS terminated line drivers has been mentioned in the literature [3]. However, this analog technique has limi- tations. They include increased dc power dissipation on- chip to generate the analog voltages and the inability to easily adjust the impedance of several on-chip buffers in- dependently.

This paper describes how CMOS circuits can be adjusted digitally to generate controlled impedances for use in high-performance circuits. Because these CMOS circuits only require digital signals to operate, on-chip dc power can be reduced and impedances can be adjusted (by manipulating the digital control information). In particular, a design of a CMOS series terminated line driver will be discussed, although these controlled impedances can be used for a multitude of purposes, such as on-chip transmission-line terminating circuits, constant delay lines, and controlled d i / d t output buffers.

External resistors are used to terminate transmission lines driven by lOOK ECL signals. These resistors can be placed on a Poly-Hic package [4], but the packaging costs can be prohibitive. A simplier package (i.e., PGA, plas- tic) could be used if these resistors can be placed on-chip. Resistors can be formed on silicon by using MOS devices controlled by a digital signal. This design could be used to terminate transmission lines in their characteristic impedance on-chip. Thus, this digital resistance technique offers a interface capability between lOOK ECL logic levels and internal CMOS levels. Although addi- tional power dissipation occurs on-chip due to this newly formed resistor, external resistors would not be neces-

0018-9200/92$03.00 @ 1992 IEEE

GABARA AND KNAUER: DIGITALLY ADJUSTABLE RESISTORS IN CMOS 1 I77

sary , thereby reducing costs, improving performance, and providing a reduced cost alternative.

11. CIRCUIT BACKGROUND A. Transistor Array

The basis of digitally adjustable impedance resides in the binary-weighted transistor array shown in Fig. 2(a). Binary-weighted capacitors and transistors have been used in digital-to-analog converters [5] while binary-weighted transistors controlled by an analog voltage have been used in an adjustable current source [6].

The digitally adjustable impedance is formed by a transistor array consisting of N + 1 transistors connected in parallel between A and B where each transistor is controlled by a digital signal. The digital signal is generated by the circuit equivalent structure of a NAND gate. The common terminal of all the NAND gates is driven by the input signal through the inverter ZNV. The elements of the transistor array are enabled according to the setting of the ( N + 1)-bit control bus which is applied to the NAND gates. The width of each of the N + 1 transistors is 2NWre,. The least significant bit (LSB) of the control bus enables the device with a width of 2’Wref while the most significant bit (MSB) enables the device with width 2NWre,. Thus, the control bits can dynamically adjust the width of the com- bined transistor array between terminals A and B. The total gate width of the array can have a width of 0 pm (all control bits are 0) to a width of [ZNf I - 11 Wref (all control bits are 1 ) in increments of Wref. This allows the effective impedance of this circuit to be adjusted digitally. A block diagram of this circuit is shown in Fig. 2(b) and is called a digital transistor array (DTA).

B. Series Terminated Output Bufer A series terminated line driver can be formed by con-

necting two DTA’s together as illustrated in Fig. 3(a). This CMOS circuit emulates the characteristics of the ideal circuit shown in Fig. 1. For the design shown here, the conventional power supply values were 0 V ( VDD) and - 5 V (Vss). The voltage swing at the output of the I/O was reduced to achieve high-frequency operation ( 2 200 MHz). Another power supply (in this case, VLs = -2 V) needs to be applied to the chip in order to generate the reduced swing at the output. The voltage swing of the I/O buffer, for these conditions, will be between 0 and -2 V, which also includes the range of ECL voltage levels. The absolute magnitude of the VLs power supply could be reduced further for lower power dissipation at the ex- pense of reduced noise margins of the transferred signal.

The need of a third power supply to the chip is not a limiting issue, since the substrate conduction technique [7] can be used for CMOS designs. Substrate conduction uses the substrate of the CMOS chip for the return current flow of either the V D D or the V,, lead depending on the type of starting material used for the substrate. In this case, only two types of pads are required on the surface of the chip, either V D D and VLs or VLs and V,,.

In

2~ 12 Control bus

(a)

Input - I

DTA A I Input I Control

(b) Fig. 2 . (a) Logical representation and (b) block diagram of a digitally con-

trolled CMOS resistor formed from binary-weighted transistor widths.

Input

UN U2 U1 U0

LN U L1 LO

(a)

Input

Input output

(b) Fig. 3 . (a) Logical representation and (b) block diagram of a series ter-

minated transmission line driver.

The buffer in Fig. 3(a) consists of two separate digital transistors arrays, where the resistance of each array is determined by a separate ( N + 1)-bit control bus that is generated on-chip. Since this voltage swing lies very close

1 I78 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27, NO. 8, AUGUST 1992

to the VDD rail, p-channels are used for both transistor arrays. (However, a design could be chosen for the swing to be near the V,, power supply, such as -4 to -5 V. Then the arrays would have used n-channels devices.) The lower transistor array actively pulls the output low to -2 V. It consists of devices MPLO-N, NAND gates NANDLO-N, and control signals LO-N. The upper transistor array actively pulls the output high to 0 V. It consists of devices MPUO-N, NAND gates NANDUO-N, and control signals UO-N. Fig. 3(b) illustrates the block diagram of Fig. 3(a). An inverter is inserted into the input signal path of the upper transistor array to insure that only one transistor array is on at a time. The generation of the control bits LO-N and UO-N is described in the following sections.

C. Lower Transistor Array Reference Circuit

The reference circuit that digitally adjusts the width of the lower transistor array is illustrated in Fig. 4. An external off-chip resistor, RI = 50 Cl, serves as the reference impedance. The top of the transistor array, V/half, is connected to V,, (0 V) through the resistor. The bottom of the array is connected to - 2 V (VLs). In order for the array to achieve a resistance of 50 Cl at worst-case slow (WCS; 4.5 V, 125”C, and long channel length) in the 0.9-pm process [8], the device requires a width of at least 680 pm.

In order to maximize performance (by minimizing drain and input gate capacitance), the total available width of the device should nearly match the above width (of 680 pm). The choice of determining the values of Wref and N was a function of layout design rules and desired ac- curacy of the final resistance. Since these resistors can be formed anywhere on a large die (> 1 cm2), the mismatch- ing characteristics of identical MOS devices were reduced by using the rotational symmetry layout technique [9]. This technique compensates for processing and orienta- tion anomalies of “matched” devices and reduced the variation of the mismatch from 14% to 2.7 % over a 1-cm2 area. However, the two above rules of rotational symmetry and the minimum design rules dictated that W,,, should be 1 1 pm. Knowing W,, and the desire to achieve a total width of 680 pm indicated that N = 5.

The minimum device width of Wref serves as the building block of all larger sized devices. Forming all transistors this way insures that these devices scale (i.e., AW/ W is the same for the transistor array independent of the final width chosen). Only the device controlled by the funny bit, which is discussed later, has a width less than Wref.

The input of the transistor array in Fig. 4 is set to Vss to potentially enable the array. The transistor array and RI form a resistor divider network whose output, V/half, is applied through a low-pass filter to the positive terminal of the differential amplifier. Another resistor divider network, R2 and R3, is formed between the same two power supplies by on-chip resistors formed by silicide. The value of R2 = R3. The voltage of this second divider, Vmid, is

ov L(VDD)

k m VLHALF

-2v

Counter

Fig. 4. Lower transistor array reference circuit

applied through a low-pass filter to the negative terminal of the differential amplifier. The output of the differential amplifier generates a U / D signal which is applied to a 6-b up-down counter through a positive edge-triggered flip-flop. The up-down counter, which uses negative edge-triggered flip-flops, generates the control bits LCO-5 which are used to adjust the width of the reference transistor array. The clock that counts the flip-flops is generated on-chip by a low-frequency ring oscillator. The up-down counter either increments or decrements the control bit pattern by 1 b every period of the ring oscillator, until the impedance of the array matches the value of R I . The positive edge flip-flop prevents glitches from being passed to the 6-b up-down counter.

When the voltage at V/half is lower than the voltage at Vmid, then the differential amplifier generates a ZERO control signal. This signal is applied to the up-down counter, and it will decrement the control signal, LCO-5, by one. The width of the array is reduced by 11 pm and causes the voltage at V/half to increase. This search process will continue until the waveform of I/lhalf alternates about V,, , as illustrated in Fig. 5 .

The voltages at V[half, V,, and the U / D signals are depicted in Fig. 5. Also indicated is a possible hexidecimal control bit pattern of LCO-5. When VIhalf < Y n i d , then the U / o signal is low. This forces the up-down counter to count down, reducing the width of the array. The duration of the step is equal to one period of the ring oscillator. When V/half exceeds Vmld, as shown at time t l , then the U / D signal goes high. This forces the counter to count up 1 b and reduces the value of V,,,,,below Vmid, as shown at time t2. Due to the quantization of the buffer width, V/half alternates about Vmjd. The control bits causing this effect are alternating between two values 1 b apart. For this transistor array, the voltage between V[half and V,, could be as much as 10 mV, providing a +_4% variation in resistance of the array biased at Vmjd.

D . Lower Transistor Array Sequencer Circuit Once the quantization condition occurs, the control bit

pattern LCO-5 is alternating between two values 1 b apart. Attempting to send these alternating bit patterns around the frame of the chip could cause timing problems to de- velop in the output buffers. For instance, the buffer’s

GABARA AND KNAUER: DIGITALLY ADJUSTABLE RESISTORS IN CMOS I I79

-0.93v r vtAIO

I I I I I I I I I I I I I I I 1 I I l l l I 1 I I I I l

Digital 31 I 30 I 2F I 2E I 2 D I 2E I 2D 1 control I I I I I

of LCO - 5 I I I I I I I I I I I I I I

(b)

(C) I I I I I I I

Fig. 5. Waveforms of (a) V,fl,d and V,hrlf. (b) lJ/6 counter signal, and (c) hex value of LCO-5.

impedance could vary significantly from 50 !J during the transitions between the assertion of the two control bit pattern's 010000 and 001 11 1, which are 1 b apart. But, the impedance for a bit pattern varying between 010001 and 010000 may not be noticeable, since only the LSB is changing. Since these final bit patterns are determined by process, voltage, and temperature, the latter bit pattern may not always occur. Therefore, it is necessary to determine when the U / D signal is alternating every clock cycle so that one of the two bit patterns can be held in a register and send around the frame.

The circuit in Fig. 6 is used to pick one of the two control bit patterns. A sequencer is used to detect when the U / D bit alternates between a ONE and a ZERO and generates a recycle signal. A transparent register becomes a hold register once the recyle signal is issued and stores one of the control bit patterns into the register. This final control bit pattern, called LO-5, is sent around the frame of the chip to the lower transistor array of all the output buffers.

A block diagram of the lower transistor reference array and hold register is depicted in Fig. 7. The closed- loop circuit consists of the lower transistor array, low- pass filter, comparator, flip-flop, and the up-down counter, which is always updating the control bit pattern LCO-5. If the power supply voltage and temperature remain constant, then due to the sequencer and hold register, the bit pattern LO-5 is stable. However, if either of these two external conditions varies, then the bit pattern is updated with new information.

To illustrate this effect, the bits 150-5 are applied to a second transistor array which is terminated through 50 !J to ground. Fig. 8 illustrates how the voltage formed between the second array and the resistor behaves after the power supply is varied by 1 V . From t = 0 ns to t = 0.2 ps, the reference circuit searches for one of the two possible LO-5 patterns. From t = 0.2 to t = 0.3 ps, the sequencer circuit is selecting the final control bits. At t = 0.3 ps, the recycle signal selects one of the two control bit patterns. At t = 0.4 ps, the V,, power supply is decreased from -4.5 to -5.5 V. This forces an out-of-se-

Recycle Signal

Clock

LCO

LC1

. . .

Fig. 6 . Sequencer and hold register

1 ov =(VDD)

VLHALF

transistor

-2v

1 - LO-5

Fig. 7. Lower transistor array and hold resister reference

-0.88 -0.90 I -0.92 -0.94

-1.06 -1.08 -1.10 -1.12 -1.14 -1.16 -1.18

0.0 0.2

VSS changed from

(X 1 E-6) I 0.6 0.8 1.0 1.2

Time

Fig. 8. ADVICE results of V,hal, when power supply is varied by 1 V

quence condition, and removes the recycle signal which makes the holding flip-flops transparent. At t = 1.1 ps, the reference circuit again locks onto one of the two final control bit patterns. The second control bit pattern is different from the first one selected at t = 0.3 ps. In this way, even after a 1-V change to the power supply, the circuit in Fig. 7 has the ability to update and lock in the control bits LO-5.

When this buffer is used during normal operation, a variation in temperature could occur by various data pat-

1180 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27, NO. 8, AUGUST 1992

h

terns flowing through the chip. This could cause a change in temperature which would force an update to occur. Al- though our current design can compensate for this case, the potential glitch during the control bit update could still occur. Several alternatives are available to prevent this event. One is to update the pattern during a period of time that the chip has a known “dead space,” where an update would not affect the operation. Another is to first apply the pattern locally to each and every buffer, then update the information during the inactive edge.

*Input

Control B

E. Upper Transistor Array Reference Circuit The circuit used to determine the control bits for the

upper transistor array is shown in Fig. 9. Instead of using an external resistor as the reference, a lower transistor array that is controlled by bits LO-5 is used as the reference 504 impedance. These two transistor arrays form a voltage divider that generates the voltage I/uhalf. A differential amplifier compares this voltage with V,, and generates a U / D signal. Because the upper transistor array is being adjusted, the U / D is inverted before being applied to the up-down counter. Otherwise, this circuit operates similar to the circuit Fig. 7. The bit pattern UO-5 is sent to the upper transistor array of all the output buffers. The series terminated output buffer which is used for all output buffers is illustrated in Fig. 10.

In

F. Metastability Effect A condition of metastability in the differential amplifier

may occur during the operation of both of the above reference circuits. For example, in the process of matching the voltage of v/haIfof the lower transistor array to that of Vmrd, a condition can occur where these two voltages overlap one another, as shown in Fig. 11. Since the differential amplifier cannot detect a small voltage difference (< 1 mV) within the clock period of the ring oscillator (40 ns), the U / D signal remains in the previous state. Metastability forces the U / D signal to have a pattern of 00110011 * * .

To correct this condition, another sequencer is required which searches for this pattern. Once it is detected, the sequencer generates a signal called the funny bit. The funny bit is either in a ONE or ZERO state and is changed from one to the other when the sequencer detects the pattern 110011 - * - .

Both the upper and lower reference transistor arrays require their ownfunny bit to avoid the metastability state; it is only the two reference cells which require thefunny bit. Thebnny bit is applied to a transistor in the reference transistor array that has a width of Wref/2. The addition of thefunny bit circuitry to the lower reference array is depicted in Fig. 12. Once the metastability state has been detected, thefunny bit changes state and causes the waveform of I/rhalfto become offset by half a voltage step. This causes v,half to be centered about Vmjk

The way the funny bit removes the metastable condition is shown in Fig. 13. Once the sequencer detects a 0011

out UO-5

DTA A

c Input

I I I n\r

transistor

LO-5

Fig. 9. Upper transistor array and hold register reference.

t

(c) I 1 I I ; I I l l

Fig. 11. Waveforms of (a) Vmrd and V,halr, (b) U / D counter signal at the metastability state, and (c) hex value of K O - 5 .

Control B 1 N + l

Fig. 12. Location of the funny bir controlled transistor.

in the U / D signal, thefunny bit changes state and shifts the waveform of I/lhalf by half a voltage step.

This causes the U / D signal to have the form 101010 * * which is used to lock in the 6-b pattern of LO-5.

GABARA A N D KNAUER: DIGITALLY ADJUSTABLE RESISTORS IN CMOS 1181

I

-1100 sequence-' detected I

Funnybit - changed state ': g "0" "l" L

(c)

Fig. 13. Waveforms of (a) Vnlld and V,h,,lr, (b) W I D counter signal, and (c) funny bit signal.

G. Power Dissipation

In efforts to obtain high-performance CMOS circuits, the output buffer needs to be viewed as a transmission line driver. Generally, this buffer drives the transmission line which is terminated in its characteristic impedance [I], 121. The current the chip must source would be either 3.4 or 21 mA for the low- and high-logic IOOK ECI voltage levels. The 18-mA difference is approximately due to the voltage swing of the signal divided by the impedance of the transmission line. Since the line is terminated in its characteristic impedance, the line appears infinite and either of these two currents is continually sourced from the chip causing an average on-chip power dissipation of 12 mW per output.

For the buffer described in this paper the transmission line is not terminated. Furthermore, the driving elements have impedances that match the line. The dc currents for a 2-V swing on a 504 line would be 20 mA for both sourcing and sinking currents off and on the chip. How- ever, this current would remain active for a duration of tD = 2 ( l / v ) where 1 is the length of the line and v is the propagation velocity of the wavefront along the line. The factor 2 is due to round-trip propagation of the wavefront along the transmission line. The on-chip dc power dissipation for each output buffer with a 2-V swing would be 20 mW for the round-trip propagation of the pulse or to. Reducing the voltage swing to 1 V would reduce the on- chip dc power dissipation to 5 mW during tD. The trade- off of reducing the voltage swing would be the loss in noise margin while the gain would be the decreased power dissipation. It is important to note that this power dissipation occurs on-chip for only the duration of the round- trip flight time; afterwards the power dissipation will be ZERO. Thus, the power saving would be significant when this buffer is used for driving many data lines where the data transferred on the lines occurs at a fraction of the clock rate.

The ac component of power dissipation for this buffer is 120 pW/MHz; in comparsion, a typical CMOS output buffer generating TTL logic levels into a IO-pF load has

an ac power dissipation of 350 pW/MHz. The two inverters driven by the input in Fig. 3(a) have total gate widths of 36 and 18 pm for the p and n channels, respectively. If n-channel devices were used instead of p-channels to form the DTA, the lower gate capacitance could reduce the ac component of power dissipation by a factor of 2 .

The reference circuits in Figs. 7 and 9 dissipate a total of 75 mW. The largest fraction of this power dissipation is due to the three DTA's forming part of the reference circuit that are on-chip which dissipate dc power contin- uously. This power can be decreased by scaling only these three reference DTA's by a factor of 10 and changing the external resistor to 500 s2. This would reduce the on-chip power dissipation due to these reference circuits to 21 mW.

111. OTHER CIRCUIT CONFIGURATIONS

A. Termination Resistor The lower transistor arrray can also be used as a ter-

minating resistor at the end of transmission line as illustrated in Fig. 14. This would allow IOOK ECL signal levels to be transmitted to the input pad of the chip since the transistor array will act as an on-chip resistor. Having this capability allows the CMOS chip to communicate with OEM parts via ECL levels [ l ] , [2], yet chip-to-chip trans- fer within the system could use the voltage swing of 0 V to V,, ( - 2 V) which the series terminated drivers will generate. This allows a significant power savings for the overall system since the dc power dissipation associated with resistors at the end of transmission lines are elimi- nated for interchip communication within the system.

B. Adjustable Resistors The buffer in Fig. 10 has two separate control buses,

UO-5 and LO-5, determining its pull-up and pull-down impedance. These control buses effectively carry information concerning how much channel width the buffer should have in order to have an impedance matching that of the single external reference resistor. By locally latch- ing the value of these buses at each buffer and using local data manipulation, the buffer's impedance can be varied (i.e., dividing the control bus pattern by 2 will double the impedance of the buffer). Thus, the digital control of the buffer offers a feature that cannot be achieved with analog control. The impedance of these buffers can be varied in- dependently from each other by digital manipulation of the primary control bus signals.

C. di /dt Controlled Output Buffers Ground bounce is a concern when CMOS chips drive

TTL signals. The discharge of the capacitive load through the parasitic inductance of the power leads causes a ring- ing noise to occur on the switching waveform [ IO]. The magnitude of the ground bounce is related to the riselfall time of the output waveform. The impedance of the


-

1 OOK ECL CHIP

-

CMOS CHIP

50n TRANSMISSION LINE P-

I I

Fig. 14. Using the digital resistor array as a transmission line terminating impedance for lOOK ECL signals.

CMOS output buffer varies a factor of 2.5 times over temperature, power supply voltage, and process variations. The digital adjustable resistor technique can be used to control the output impedance. Futhermore, the same technique could be used to regulate the slew rate of the waveform being applied to the gate of the output buffer by digitally manipulating the prestage driver, thereby providing a CMOS buffer that has a well-controlled rise/fall time. Using this technique, the ground bounce can be controlled from chip to chip.

For a TTL buffer, the lower transistor array in Fig. 3(a) needs to be replaced with an array of n-channel transistors to provide a full swing CMOS capability. Also the upper array would be driven by one inverter instead of two. By utilizing the impedance control technique, the ground- bounce generation as well as the delay through the buffer can be maintained at constant levels over temperature, power supply voltage, and process variations.

D. Adjustable Delay Lines Another possible use of these digitally controlled

CMOS circuits is in an adjustable delay line formed from inverters. The delay through each inverter can be adjusted by the control bit pattern being applied to each inverter. As the control bit pattern is varied to increase the effective resistance of the inverter, the delay through the chain of inverters will increase. Similarly, the delay can be decreased allowing the chain of inverters to become an adjustable delay line which could be used for PLL's or other applications.

IV. ADVICE RESULTS A . DC Simulation

DC ADVICE [ 111 simulations were performed on the circuits illustrated in Fig. 15(a) and (b). The conditions of the simulation were performed at 125°C and long- channel process. Several arrays were simulated with different control bus values while the power supply was varied from -5.5 to -4.5 V. The results of the output voltages, (VLXXXXXX) and ( V U X X X X X X ) , in Fig. 15(a) and (b) are illustrated in Fig. 16(a) and (b), respectively. The actual control bit pattern has been substituted in for the X X X X X X pattern. As the control bits of the lower array, VLO-5, are decremented, the effective impedance of the array decreases causing the voltage to shift upwards

vuxxxxxx

(a) (b) Fig. 15. Circuit configuration for the dc simulations: (a) lower transistor

array and (b) upper transistor array.

-0.E

-0.g

P

z 6 -1.0

-1.1

.- I

-1.2 I 1 I I I

V s (VOLTS) -5.6 -5.4 -5.2 -5.0 -4.8 -4.6 -

(a)

--- I -0.9

s

z 2 -1.0

-1.1 . -.

-1.2 I I I I I I

V s (VOLTS) -5.6 -5.4 -5.2 -5.0 -4.8 -4.6 -

(b) Fig. 16. DC results for the (a) lower transistor array and (b) upper tran-

sistor array.

in Fig. 16(a). The control bits of the upper array, VUO-5, shift the voltage downwards as they are decremented.

Since the full transient analyses of the circuit shown in Figs. 7 and 9 are prohibitive due to the required simulation time, the dc analysis method can quickly determine

GABARA A N D KNAUER: DIGITALLY ADJUSTABLE RESISTORS IN CMOS I I83

INPUT -1

;-I; -0.5

z

-1.5

-2.0 1

B

I , ,, uo-5 1 1 sm DTA 5

50n TRANSMISSION LINE ,0U7 a

- - -

Fig.

;II Fig. 18. Waveform at end of open-circuited terminated transmission line;

conditions are nominal channel length, 30"C, and -5 V .

what value the two control buses LO-5 and UO-5 should have when simulating a single buffer under various operating conditions.

B. Transient Analysis Fig. 17 illustrates the circuit that was simulated in AD-

VICE. It consists of a CMOS series terminating buffer driving an open-ended 504 transmission line. The AD- VICE model of the CMOS buffer was extracted from the layout. The waveform at V,,, is depicted in Fig. 18 where the conditions were 30°C, -5.0 V , and nominal channel length. The frequency of operation was 200 MHz.

V. MEASURED RESULTS Fig. 19 is a microphotograph of a digitally controlled

I/O buffer. The DTA illustrated in Fig. 2(a) is the basic building block for the entire 110 buffer. On the input pads, the DTA's are used to terminate a lOOK ECL signal; thus, these resistors are used to terminate the transmission line on-chip. The balanced output pads are the source terminated drivers illustrated in Fig. 3(a). Note the two power supply rails, 0 and -2 (VLs) V , and the two control buses,

Fig. 19. Photomicrograph of a balanced input IOOK ECL buffer with on-chip terminating resistors and a digitally controlled balanced output buffer.

UO-5 and LO-5, that are used to control the input and output impedances. The VLs power rail was adjusted to different voltage levels when the device was tested. The signal on the input buffer is translated by the ECL-to- CMOS level shifter and applied to the CMOS phase split- ter. This output is then applied to the output buffers generating OUT and W T .

Fig. 20(a) and (b) depicts the measured waveform of the output buffer operating at 330 MHz at two different reduced power supply voltages ( VLs). The buffer has N =

5 , Wref = 11 pm, and the UO-5 and LO-5 bit patterns listed in the figure caption. The power supply voltage is 5.0 V, while the reduced power supply voltages (VLs) were 1.8 and 0.8 V, respectively. A Tektronix 11801 with an SD-24 sampling head was used for the measurement. A high-impedance probe Tektronix 6201 with 1101-A power supply was used to measure the waveform at the end of an unterminated 3-ft 5 0 4 transmission line.

For the buffer with VLs = 1.8 V, the on-chip dc power dissipation would be 16.2 mW. Significant power savings occur as VLs is reduced. For the measured waveform with


4”mV

E e e m V 0d 1 U

*

=ir ~.

- 1 . 6 V ’ - - -

’/ “c.T - -

VLs = 0 . 8 V, the on-chip dc power dissipation would be

be 40 mW9 giving a total of

VII. CONCLUSION

justed digitally to generate controlled impedances for use

cuits only require digital signals to operate, on-chip dc power is reduced and impedances can be manipulated by adjusting the digital information. In particular, a design of a CMOS series terminated line driver was discussed.

3.2 mW for the round-trip propagation. In both cases, the

56.2 and 43.2 mW Of total power dissipation at 330 MHz

This paper describes how CMOS circuits can be ad-

in high-performance circuits. Because these CMOS cir- ac

for the two cases, respectively.

VI. FUTURE IMPROVEMENTS

Several areas could be addressed to insure a more robust buffer operation. The period of the ring oscillator could be increased and help improve the circuit operation since the comparator in Fig. 4 will have more time to generate the up-down count during the metastable state. Also several series inverters can be placed at the output of the comparator to prevent the propagation of the metastable state. The sequencer block in Fig. 6 currently takes one clock period to detect the sequence but two clock periods to come out of sequence. This increases the error of the DTA’s resistance by a factor of 2. By using taps on the ring oscillator, the out-of-sequence can be detected in one clock period.

ADVICE results of this buffer driving an open-ended transmission line were given. Also, a microphotograph of the series terminated output buffer and several measured waveforms were given. Finally, an explanation of how the controlled impedance technique could be used in transmission line terminating circuits, constant delay lines, and controlled d i ld t output buffers was given.

ACKNOWLEDGMENT The authors would like to thank J . Condon for identi-

fying the metastability problem and offering several so- lutions, R . Mclellan for helpful discussions, and Y. C. Wu for help in using his automated layout tool, W2.

GABARA AND KNAUER: DIGITALLY ADJUSTABLE RESISTORS IN CMOS 1185

REFERENCES nologies. These include adoptable circuits which ease system interface design yet allow high performance to be achieved. Other topics of interest include ground-bounce reduction techniques, PLL’s, dynamic logic, and laser driverlreceiver systems. He holds five U.S. patents.

M. Pedersen and P. Metz, “A CMOS to lOOK ECL interface circuit,” in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 226-227. T . J . Gabara and D. W. Thompson, “A 200 Mhz lOOK ECL output buffer for CMOS ASIC’s,’’ in Proc. IEEE ASIC Seminar and Exhibit, Sept. 1990, pp. 8-5.1-8-5.4. T. F. Knight and A. Krymm, “A self-terminating low-voltage swing CMOS output driver,” IEEE J . Solid-State Circuits, vol. 23, no. 2, pp. 457-464, Apr. 1988. D. W. Thompson, T . J . Gabara, and C. Stroud, “A 180 MHz ASIC for high-speed backplane interfaces, ” in ISSCC Dig. Tech. Papers, vol. 34, Feb. 1991, pp. 140-141. J . L. McCreary and P. R. Grey, “All-MOS charge redistribution analog-to-digital conversion techniques,’’ IEEE J . Solid-Stare Circuits, vol. SC-10, no. 6 , pp. 371-379, Dec. 1975. M. Banu, “ 100 KHz-GHz NMOS variable-frequency oscillator with analog and digital control,” in ISSCC Dig. Tech. Papers, Feb. 1988,

T . J . Gabara, “Ground bounce control and improved latch-up suppression through substrate conduction, ” IEEE J . Solid-State Cir- cuits, vol. 23, no. 5 , pp. 1224-1232, Oct. 1988. M-L. Chen er a l . , “A high performance submicron CMOS process

pp. 20-21.

with self-aligned chan-stop and punch-through implants (twin-tub V),” in IEDM Tech. Dig. , Dec. 1986, pp. 256-259. T. Gabara and P. Metz, “Improved DC matching of CMOS circuits using rotational symmetry,” in Proc. IEEE ASIC Seminar and Ex- hibit, Sept. 1991, pp. 10.3.1-10.3.3. T. Gabara and D. Thompson, “Ground bounce control in CMOS in- tegrated circuits,” in ISSCC Dig. Tech. Papers, Feb. 1988, pp.

L. W. Nagel, “ADVICE for circuit simulations,” in Proc. Inr. Symp. Circuits Syst. (Houston, TX), Apr. 28, 1980.

88-89.

Thaddeus J. Gabara (S’77-M’85) received the B.S.E.E. and M.S.E.E. degrees from New Jersey Institute of Technology and studied physical elec- tronics at the University of Minnesota.

He is a Member of the Technical Staff at AT&T Bell Laboratories, Murray Hill, NJ, in the Digital Architectures Research Department. His experi- ence has covered VLSI design issues involved with areas of microprocessors and telecommunication CMOS devices. He has been concentrating on developing new circuit techniques for CMOS tech-

Scott C. Knauer (S’68-M’71) received the B.S.E.E. degree from Rutgers University, New Brunswick, NJ, in 1968, and the M.S.E.E. and Ph.D. degrees in electrical engineering from Stan- ford University, Stanford, CA, in 1969 and 1977, respectively.

He worked at NASA’s Ames Research Center from 1972 to 1981 on algorithms and hardware for real-time video compression, which was also his thesis topic. He arrived at AT&T Bell Laborato- ries, Holmdel, NJ, in April 1981. He met A.

Huang (with a background in optical computing), and they decided to jump into high-capacity switch fabrics. They developed the self-routing, non- blocking Batcher-banyan fabric, and several systems based upon variations of this principle. He continued video processing work and developed VLSI architectures for both video and switching. He currently heads the Digital Architectures Research Department in the Computing Systems Research Laboratory at Murray Hill, NJ. The department develops special-purpose computer architectures, creating custom chips and building them into board- level systems. He is part of the AT&T Zenith team developing an HDTV standard (including a hardware prototype transmitter and receiver) for the FCC competition and continues his activities in broad-band (2.4 Gb/line) switching projects.

Digitally adjustable resistors in CMOS for high-performance applications

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