Determination of the channel doping density in MOS devices with high-k devices

DETERMINATION OF THE CHANNEL DOPING DENSITY IN MOS DEVICES WITH HIGH-Κ GATE DIELECTRICS

Dharmendar Reddy and Samares Kar Department of Electrical Engineering, Indian Institute of Technology, Kanpur-

208016, India

ABSTRACT

A new technique is outlined here for the extraction of the channel doping density of MOS nano-transistors with high permittivity ultrathin (equivalent oxide thickness (EOT) = 0.5 to 2.0 nm) gate dielectrics, using either the accumulation or the strong inversion MOS capacitance or both. This technique also obtains the doping density at the edge of the space charge layer at the onset of strong inversion, if the device is a MOSFET. Comparision of results from the new technique is made with the interface doping density and the doping profile obtained from the Ziegler technique.

INTRODUCTION

With increasing miniaturization of the MOSFET, the dopant distribution has become ever more non-uniform in the active part of the device, and, particularly, in the most critical space, which is the channel region. The factors influencing the dopant profile and its complexity include the nature of the implanted profile, diffusion and segregation during subsequent high temperature processing, and diffusion of impurities into the channel region through the ultrathin gate dielectric. The doping profile, particularly, the channel doping, is a very critical device parameter, that needs to be known or determined, in order to assess the important device characteristics, such as the threshold voltage and the drain current.

Current techniques for extracting the doping profile can be classified into two groups: physical and electrical. The physical extraction techniques yield the total doping density, and include secondary ion mass spectroscopy (SIMS) and helium ion (Rutherford) backscattering spectroscopy (RBS). SIMS and RBS are costly, destructive, and time-consuming techniques; further, they require special sample preparation. The electrical extraction techniques yield the density of ionized dopants, are non-destructive and time-wise efficient, and include spreading resistance and capacitance-voltage techniques. A time-wise efficient and very simple electrical characterization technique, based on the depletion approximation, has been in use for long, and employs the following relations:

ECS Transactions, 1 (5) 553-563 (2006)10.1149/1.2209304, copyright The Electrochemical Society

553 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 117.248.136.120Downloaded on 2014-10-23 to IP

554

[1]

where N is the doping density at a distance W from the Si/gate-dielectric interface, q is the elementary charge, εs is the silicon permittivity, Csc is the space charge capacitance density, and ĳs is the surface potential. Unfortunately, this easy technique cannot yield the doping profile within 2λ of the silicon/gate-dielectric interface, due to the neglect of the majority carrier density in the space charge layer (1). The extrinsic Debye length λ is given by (2VTεs/qN)1/2, where VT is the thermal voltage; for a doping density of 2X1017 cm-3, 2λ is about 26 nm at 300 K, which means that, even in the case of high channel doping, the channel region is, still, out of the reach of the above capacitance technique. Several initiatives have been undertaken to address this problem. The technique of Ziegler et al (1) is effective in obtaining the doping profile close to the interface, if the interface state trap density, Dit, is low, as is in the case of Si-SiO2 interfaces (i.e. for SiO2 gate dielectrics), and the doping profile is not sharp. At the present time, several high-Κ (Κ= dielectric constant) materials are under intensive investigation as possible candidates to replace SiO2 as the gate dielectric with EOT < 2 nm (2)-(3). Unfortunately, both the above conditions do not obtain in the MOS devices with the high-Κ gate stacks (at least, not in the current state of the high-Κ technology). In fact, the situation may be further complicated by the diffusion of impurities into the silicon sub-surface from the high-Κ gate dielectric and the gate electrode, during deposition and/or subsequent processing. Hence, there is a need for a simple and time-wise efficient, but, reliable, technique for the extraction of the channel doping density, which will be effective even when Dit is high and the implanted doping profile is sharp.

Elements of such a technique has just been reported (4); here, we present results from the application of this novel technique to a large number of devices in MOSFET and MOS capacitor configurations with different high-Ȁ materials (HfO2, HfAl2O5, ZrO2, La2O3, HfSiON, Y2Si2O7) as gate dielectrics, different high-Κ deposition methods (ALCVD, sputtering, e-gun evaporation), and gate electrode materials (poly-Si, poly-SiGe, TaN, Ti, Al). We also outline the procedure for obtaining the doping density in the depletion and the deep depletion regions.

DOPING DENSITY EXTRACTION TECHNIQUE Channel Doping Density The new technique for the extraction of the channel doping density involves use of the accumulation capacitance, instead of the depletion capacitance, as in

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sc

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sc

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ECS Transactions, 1 (5) 553-563 (2006)

) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 117.248.136.120Downloaded on 2014-10-23 to IP

555

the case of the Ziegler technique. In the new technique, the channel doping density, Nch, can be extracted as (4):

[2] where the parameters Įacc and βacc are defined by the following relation (4):

[3]

Our earlier investigation (4) unequivocally confirmed that the parallel capacitance, Cp, is an exponential function of the surface potential, ϕs, in the accumulation regime, as represented by [3], cf. Fig. 1. The parallel capacitance, Cp, which is the sum of the space charge and the interface trap capacitances, Csc and Cit, Cp = Csc + Cit, is extracted from the measured C-V data. The surface potential, ϕs, in the accumulation regime, is extracted by the integration of the measured C-V characteristic, in accordance with the following relation (4):

[4] For the extraction, the values of the gate dielectric capacitance, Cdi, and the flat-band voltage, VFB, are needed. Determination of Cdi is outlined in ref. (4). Extraction of VFB is discussed later. The surface potential quotient βacc is determined from the slope of the experimental lnCp,acc versus ĳs plot, i.e. βacc=dlnCp,acc/dĳs, and Įacc is obtained from the x-axis intercept of the same plot: lnĮacc = lnCp,acc - βaccĳs. The experimental values of Nch obtained from [2] were compared with the values of the doping density at the interface, N(0), obtained from the Ziegler technique (1), see Table I: [5] Doping Density Profile In Table I, Nsub is the substrate doping density; values of Nsub were obtained from the initial wafer resistivity data. The doping profile N(W) is obtained from the Ziegler technique (1):

[6]

( );

2

accs

accch q

Nβε

α=

).exp(, saccaccaccpC ϕβα=

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Vdi

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λϕεW

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s



556

[7]

g1 and g2 are complicated and lengthy functions of g(W/λ), which is an inverse function of W/λ (1). The functions g1 and g2 have values less than 1.0 (1). To obtain the doping profile from the Ziegler technique, one first obtains g1 from [7], then obtains W and g2, and finally N(W). The values of N(W) presented in Table I are for the MOS capacitors and are for values of W, where it is constant or has a mild profile. Nd-dep represents the doping density at the edge of the space charge layer, at the onset of strong inversion, in the case of MOSFET devices. Values of Nd-dep were obtained, for p-type silicon, using the relation:

[8] Nv is the effective density of states in the valence band, EG is the silicon band gap, k is Boltzmann’s constant, and T is absolute temperature. The term ϕs,inv is the surface potential at the onset of strong inversion; it was determined using the following criterion, Fig. 2:

[9]

Cp,inv(ĳs,inv) is the experimental value of Cp at the onset of strong inversion, while, Cp,d-dep(ĳs,inv) is the deep depletion value of Cp at the onset of strong inversion. Fig. 2 illustrates the application of the condition in [9]. Cp,d-dep(ĳs,inv) is estimated by extrapolating the experimental Cp(ĳs) curve in depletion, cf. Fig. 2. The input C-V data for all the data analysis were taken from seven carefully chosen MOSFET/MOS devices with ultrathin (EOT = 0.46-1.94 nm) high-Κ gate dielectrics, from the literature [5]-[12], cf. Table I, offering a wide variation in band offsets (φb = 2.00 –4.19 eV), effective tunneling mass (m* = 0.22-0.46 m), and dielectric constant (Κ = 14-33).

SIGNIFICANCE OF DOPING DENSITY VALUES

The reliability and the accuracy of the new technique was evaluated by using the control sample, cf. Table 1. The control sample was fabricated using only dry rapid thermal oxidation and filament evaporation under ultra-clean conditions. We avoided using any processing, that would have made the doping profile non-uniform in the silicon subsurface. We did not use any ion implantation or any high

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Table I: Comparison of the experimental values of the doping density. Nch is the channel doping density, obtained from [2]; N(0) is the interface doping density, obtained from [5]; Nsub is the doping density obtained from the initial resistivity of the substrate; Nd-dep is the deep depletion doping density (given in italics), obtained from [8]; Ndep is the depletion doping density (given in bold), obtained from [12]; and N(W) is the doping density (underlined) at distance W (given in parenthesis) from the interface, obtained from [6] and [7].

Device Nch

cm-3

N(0)

cm-3

Nsub

cm-3

Nd-dep

Ndep

N(W)

cm-3

VFB

from Ĵs

(V)

VFB

from C-2

(V)

p-Si/HfO2/poly-SiGe

MOSFET; S [5]

1.71X1017 3.28X1017 4.13X1015

3.14X1018

(30 nm)

-0.65

p-Si/HfAl2O5/poly-Si

MOSFET; ALD[6]

5.04X1017 7.70X1017 6.97X1017

3.87X1018

(25 nm)

-0.55

p-Si/ZrO2/TaN MOS; S [7] 6.16X1016 1.55X1017 2.10X1015 1.89X1015

(110 nm)

-0.65

p-Si/HfO2/Ti MOS; E [8] 1.99X1015 3.29X1015 1.40X1015 1.92X1015

(342 nm)

-0.88

n-Si/HfO2/TaN MOSFET;

CVD [9]

1.93X1017 2.10X1017 1.00X1016

4.00X1016

0.10 0.10

p-Si/HfO2/Al MOS; ALD

[10]

7.66X1017 8.24X1017 1.40X1016 1.04X1018

8.48X1017

(16 nm)

-0.03 -0.02

p-Si/La2O3/Al MOS; O of

La [11]

1.75X1017 1.59X1017 1.28X1017

1.34X1017

(52nm)

-0.11 -0.11

Control sample:

p-Si/SiO2/Al MOS; O

1.20X1015 1.10X1015 0.80-

1.20X1015

1.20X1015

1.38X1015

(388 nm)

-0.99 -0.99

S Ł Sputtering; ALD Ł Atomic Layer Deposition; E Ł Electron beam evaporation; CVD Ł Chemical Vapor Deposition; O Ł (Thermal) Oxidation.



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temperature annealing; this was a simple MOS capacitor, and rapid thermal oxidation was the only high temperature step, but the duration of the entire temperature profile was only 30 s. This sample had a mid-gap interface state density of 2X1010 cm-2V-1 and no measurable gate dielectric leakage current. The excellent agreement between the results, obtained for the control sample from the new and the Ziegler techniques, confirms the reliability of the former. Table 1 shows that, for the control sample, values of the interface doping density from the Ziegler technique, channel doping density from the new technique, and the doping density from the initial silicon wafer resistivity were all same. The doping profile obtained from the Ziegler technique (not shown here) was flat for the control sample, confirming that the Ziegler technique works well, if the doping density has no or mild profile and the interface trap density is low.

In the case of the high-Ȁ gate dielectrics, for six samples, the values of the

interface doping density N(0) obtained from the Ziegler technique, are not very different from the values of the channel doping density Nch obtained from the new technique. For the remaining high-Ȁ sample, N(0) is much higher than Nch. It is possible that in the high-Ȁ samples, both interface traps as well as bulk traps in the silicon space charge layer may be present. The experimental data of Table 1 and the N(W) data indicated strong doping profiles for five high-Ȁ samples, while for the p-Si/HfO2/Ti and the p-Si/La2O3/Al MOS capacitors, the doping profile is more or less flat. It is worth mentioning that the p-Si/HfO2/Ti MOS capacitor was fabricated without using any process (8), which could have resulted in a strong doping profile, and the low channel doping density in this case reflects clean processes used. The much higher channel doping density than the corresponding substrate doping concentration, could be explained in the case of the MOSFET devices, by channel implantation, as in the case of the p-Si/HfAl2O5/poly-Si MOSFET (6), however, in the case of the MOS capacitors, cannot be explained by channel implantation; this may indicate diffusion of impurities into the silicon subsurface, during the deposition of the high-Ȁ gate dielectric and subsequent device processing (e.g. PDA), or during the deposition of the metal gate electrode (9). These impurities may be giving rise to both shallow as well as deep traps in the silicon space charge region, and may be responsible for the low channel mobility, which is a very serious problem in high-Ȁ transistors (2-3).

FLAT-BAND VOLTAGE

The flat-band voltage has always been an important parameter for assessing the quality of an MOS device; it is even more so now for the high-Ȁ transistors for a number of reasons. The flat-band voltages are very high, irrespective of what the high-Ȁ material is, what its deposition technique is, and what the gate electrode is. Reducing and controlling the flat-band voltage has become a serious challenge for the development of the high-Ȁ technology. The flat-band voltage shift reflects both the fixed charges in the gate dielectric bulk and the interface trap charges at flat-band. Since, the latter is difficult to determine, independently, for the high-Ȁ devices, as mentioned earlier, the flat-



559

band voltage has become a measure of both the fixed and the interface trap charges.

Determination of the flat-band voltage is simple if the doping density is

uniform in the silicon sub-surface and there is no carrier confinement in the accumulation layer (13); otherwise, its extraction becomes complicated. Presence of unknown contamination and impurities in the silicon sub-surface will further complicate the situation. To determine the flat-band voltage, VFB, we have employed the following empirical relation; cf. the relation in [3]:

[10]

In other words, at ϕs = 0, the ratio of the experimental Cp to αacc, i.e. the intercept of the linear part of the Cp versus ĳs plot with the ϕs = 0 line, is √2. This procedure is illustrated in Fig. 2. The condition of [10] first yields the integration constant K of [4]; the voltage corresponding to ϕs = 0, then, yields VFB. Table I presents the values of VFB obtained from the ĳs(V) plots. The reliability and the accuracy of the new approach for the determination of VFB was evaluated in the following manner, by using the control sample, cf. Table I. As already discussed, the control sample has a uniform and low doping density, a low interface trap density, and a thin gate dielectric. For such a sample, the intercept of the C-2(V) characteristic with the voltage-axis can yield a reliable value for the flat-band voltage (14): [11] The C-2(V) characteristics of the control sample (see Fig. 3) was a perfect straight line in depletion and weak inversion (over a surface potential ĳs range of 0.081 to 0.459 V); its intercept with the voltage axis gave exactly the same value, i.e. -0.99 V, of the flat-band voltage VFB, as from the experimental ĳs(V) characteristic, cf. Table I. The excellent agreement, displayed in Table I between the values of the flat-band voltage VFB of the control sample, obtained from the two approaches, confirms the validity of the approach represented by [10]. It may be noted that, in the voltage range of -0.90 to -0.50 V, cf. Fig. 3, the control sample had a dĳs/dV of 0.95 and a C/Cp of 0.94 to 0.96. For some high-Ȁ devices, the C-

2(V) characteristics were found to be linear over a major part of the depletion region, cf. Fig. 4. For these devices, values of VFB could be obtained from these characteristics, cf. Fig. 4 and Table I. Surprisingly, the agreement is good between these two sets of flat-band voltages, and this again confirms the validity of the approach represented by [10].

2=acc

pC

α

( ) . , ,tanN ,1d

, ,2 s2scpFB

s

CCCandtconsdV

ifVVNq

C ≈≈=≈−=− ϕε



560

If the C-2(V) characteristic is a straight line in the depletion regime, then, a value for the depletion doping density Ndep can be obtained from its slope, using the following relation, if the conditions of [11] are satisfied:

[12] Values of Ndep have been presented in Table 1, for those devices for which the C-

2(V) characteristics were linear in the depletion regime. These values agree with the trend of the doping profile suggested by values of N(0), Nch, Nd-dep, and N(W) (not presented here), obtained by various means, as outlined earlier.

The genesis of the empirical relations in [9] and [10] is the assumption that

these ratios, which obtain in the classical analysis, remain more or less unchanged by carrier confinement effects. The genesis of the empirical relation in [2] is the assumption that the pre-factor in the Csc(ĳs) relation, namely Įacc, cf. [3], has the same dependence on Nacc, with or without carrier confinement effects, and remains unaltered by the nature of carrier occupancy – Fermi-Dirac or Boltzmann occupancy. The most serious limitation to these relations is the interface trap density; these relations can be expected to work satisfactorily as long as Cit is small compared to Csc, in accumulation for Eq. [2], at the onset of strong inversion for [9], and at flat-band for [10].

The new technique for the extraction of the doping density and the flat-

band voltage will work, when the classical techniques fail due to one, some or all of the following factors: a sharp doping profile, significant carrier confinement effects, high interface trap density, and contamination of the silicon sub-surface during processing.

4. CONCLUSIONS A new extraction technique has been outlined for obtaining the channel doping density, and the doping density away from the Si/gate-dielectric interface. The reliability of this technique was tested by applying this technique to a carefully fabricated control sample with constant doping density. The new technique was applied to seven carefully chosen high-Κ MOSFET and MOS devices from the literature. The values of the doping density obtained by this technique were compared with the values of the interface doping density and the doping profile obtained from the Ziegler technique. The latter gave higher values of doping density, most likely due to a high interface trap density and/or a sharp doping profile. The experimental results indicate diffusion of impurities into the channel region during the deposition of the gate dielectric and subsequent post-deposition annealing.

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ACKNOWLEDGEMENT

Financial support from the Department of Science and Technology, New Delhi and the National Science Foundation, Washington, DC, is gratefully acknowledged. Dharmendar Reddy appreciates partial financial support from Dean, Resource Planning and Generation, Dean of Academic Affairs, and Department of Electrical Engineering, Indian Institute of Technology, Kanpur-208016, India and also partial travel support from National Science Foundation (Grant # ECS-0535679) to present this paper.

REFERENCES 1. K. Ziegler, E. Klausmann, and S. Kar, Solid-State Electron., 18, 189 (1975). 2. S. Kar, D. Misra, R. Singh, and F. Gonzalez, Editors, Physics and Technology of High-Κ Gate Dielectrics - I, PV 2002-28, The Electrochemical Society Proceedings Series, Pennington, NJ (2002). 3. S. Kar, R. Singh, D. Misra, H. Iwai, M. Houssa, J. Morais, and D. Landheer, Editors, Physics and Technology of High-Κ Gate Dielectrics -II, PV 2003-22, The Electrochemical Society Proceedings Series, Pennington, NJ (2003). 4. S. Kar, S. Rawat, S. Rakheja, and D. Reddy, IEEE Trans. Electron devices, 52, 1187 (2005). 5. Q. Lu, H. Takeuchi, X. Meng, T.-J. King, C. Hu, K. Onishi, H.-J. Cho, and J. Lee, p.86, 2002 Symposium on VLSI Technology Dig. Tech. Papers (2002). 6. J.-H. Lee, Y.-S. Kim, H.-S. Jung, J.-H. Lee, N.-I. Lee, H.-K. Kang, J.-H. Ku, H. S. Kang, Y.-K. Kim, K.-H. Cho, and K.-P. Suh, p.84, 2002 Symposium on VLSI Technology Dig. Tech. Papers (2002). 7. R. Nieh, R. Choi, S. Gopalan, K. Onishi, C. S. Kang, H.-J. Cho, S. Krishnan, and J. C. Lee, Appl. Phys. Lett., 81, 1663 (2002). 8. H. Harris, K. Choi, N. Mehta, A. Chandolu, N. Biswas, G. Kipshidze, S. Nikishin, S. Gangopapadhyay, and H. Temkin, Appl. Phys. Lett., 81, 1065 (2002). 9. C. H. Lee, J. J. Lee, W. P. Bai, S. H. Bae, J. H. Sim, X. Lei, R. D. Clark, Y. Harada, M. Niwa, and D. L. Kwong, p.82, 2002 Symposium on VLSI Technology Dig. Tech. Papers (2002). 10. Y.-S. Lin, R. Puthenkovilakam, and J. P. Chang, Appl. Phys. Lett., 81, 2041 (2002). 11. Y. H. Wu, M. Y. Yang, A. Chin, W. J. Chen, and C. M. Kwei, IEEE Electron Device Lett. 21 (2000) 341. 12. M. Houssa and J. L. Autran, Appl. Phys. Lett. 81 (2002) 709. 13. E. H. Nicollian and J. R. Brews, MOS (Metal-Oxide-Semiconductor) Physics and Technology, Wiley Interscience, New York, 1982. 14. S. Kar and W. E. Dahlke Solid-State Electron. 15 (1972) 221.



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Fig. 1: Experimental parallel capacitance, in the strong accumulation regime, Cp,acc = Csc,acc + Cit,acc, versus the surface potential, ϕs, for five MOS devices (on p-type silicon) containing different high-Κ gate dielectrics, cf. Table I.

Fig. 2: The experimental parallel capacitance Cp versus surface potential ĳs for the p-Si/HfAl2O5/poly-Si MOSFET (6). This plot illustrates the application of the condition in [10] to find the flat-band voltage VFB, and also of the condition in [9] to find the surface potential ĳs,inv (= 0.97 V) corresponding to the onset of strong inversion.



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Fig. 3: C-2 versus bias V characteristics of MOS capacitor on p-Si with SiO2 gate dielectric (control sample). Fig. 4: C-2 versus bias V characteristics of MOS capacitors on p-Si with different gate dielectrics: HfO2 (10); La2O3 (11); and ZrO2 (12).

C-2

(µF/

cm2 )-2



Determination of the channel doping density in MOS devices with high-k devices

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