Comprehensive Performance Benchmarking of III-V and Si nMOSFETs (Gate Length = 13 nm) Considering...

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 3, MARCH 2015 713

Comprehensive Performance Benchmarking of III-Vand Si nMOSFETs (Gate Length = 13 nm)

Considering Supply Voltageand OFF-Current

Raseong Kim, Member, IEEE, Uygar E. Avci, Member, IEEE, and Ian A. Young, Fellow, IEEE

Abstract— Comprehensive performance benchmarking resultsfor III-V and Si nanowire nMOSFETs (gate length of 13 nm)are reported based on the atomistic full-band ballistic quantumtransport simulation including the effects of parasitic resistanceand capacitance. After optimizing the source/drain doping forIII-V nMOSFETs (to balance source exhaustion versus tunnelingleakage), the current, capacitance, and switching delay (CV/I)metrics are compared across InAs, GaAs, and Si devices withdifferent crystal orientations at various supply voltage (VDD) andOFF-current (IOFF) targets. III-V nMOSFETs are projected toimprove over Si (e.g., up to ∼50% reduction in gate-loaded CV/I)for low-power operation (low VDD, low IOFF) while they loseadvantage in the high-performance (high VDD, high IOFF target)region. We also provide analytical models for the effects of carriereffective mass and physically explain how the performancecomparison of III-V versus Si changes with device scaling.

Index Terms— III-V semiconductor materials, MOSFET,nanoscale devices, nanowires (NWs), semiconductor devicemodeling.

I. INTRODUCTION

ALTERNATIVE channel materials such as III-Vs arebeing actively explored to continue the MOSFET scaling

and satisfy the required performance metrics [1]. The mainmotivation of the studies of III-V nMOSFETs has been theexpectation of high current drivability. This is based on thehigh electron mobility in III-V materials, which is expectedto result in high drain currents in the classical MOSFETtheory [2]. One thing to note here is that the high electronmobility values quoted for III-Vs are frequently the valuesmeasured for bulk materials [3]. In extremely scaled devices,however, high bulk mobility may not necessarily mean thehigh current drivability. Fundamental device physics suchas quantum effects [4] and ballistic transport [5] becomesincreasingly important, so it is critical to consider all relevantphysical aspects (not only the simple mobility-based model)to correctly project the performance of nanoscale MOSFETs.

Manuscript received October 27, 2014; revised December 6, 2014; acceptedDecember 22, 2014. Date of publication January 20, 2015; date of currentversion February 20, 2015. The review of this paper was arranged by EditorM. J. Kumar.

The authors are with the Components Research, Intel Corporation,Hillsboro, OR 97124 USA (e-mail: [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2015.2388708

There have been theoretical studies that project performanceof III-V versus Si nMOSFETs [6]–[10]. They comparecurrent–voltage (I–V ) characteristics obtained by advanceddevice simulation models, such as ballistic quantum transportsimulation [6]–[8] and Monte Carlo simulation [9], [10].In many studies, I–V s are compared at high drain voltages,i.e., ID versus VG for VD = VDD, where ID , VG , VD , and VDDare the drain current, gate voltage, drain voltage, andsupply voltage, respectively. Low or medium drain voltagecharacteristics (e.g., linear current (ID,lin), effective inverterdrive current (Ieff) [11]), however, are also important in circuitperformance and should be considered for benchmarking.In addition, the effect of parasitic source/drain (S/D)resistance (RSD) is not being considered in many studies (dueto the limited number of drain bias points) while it turns out tobe a critical issue that limits the current drivability [7]. We alsonote that, while not addressed in many of previous studies,the capacitance–voltage (C–V ) characteristics are also criticalwhen evaluating the material options because they determinethe power consumption (CV 2) and the switching delay (CV/I ).Finally, we notice that most of previous benchmarkingstudies focus only on the high-performance (HP) operationprojected in the International Technology Roadmap onSemiconductors (ITRS) [1], e.g., comparison for anOFF-current (IOFF) target of 100 nA/μm for a VDD around0.6–0.8 V. However, as applications such as portable orwearable devices arise and power consumption (e.g., batterylife) become more of an issue, low-power operation withsmaller VDD and low IOFF is now also very relevant totransistor performance benchmarking [12].

In this paper, we present comprehensive performance bench-marking results based on atomistic full-band ballistic quantumtransport simulation [13] for III-V and Si nanowire (NW)nMOSFETs with a gate length (LG) of 13 nm, which issimilar to the ITRS node of the year 2018 [1]. For III-V,we focus on InAs and GaAs, where InGaAs results will be inbetween. We present current, capacitance, and switching delaymetrics for various VDD and IOFF targets considering parasiticcomponents, such as RSD and gate fringing capacitance. As aresult of this benchmarking, we will be able to clarify theoperating region where III-V nMOSFETs improve over Si.For insights into the physics, we also present a physical model

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714 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 3, MARCH 2015

Fig. 1. (a) Schematic of the GAA NW nMOSFET. (b) Cross-sectional view(xz plane with y at the NW center). Device dimensions are similar to thoseconsidered in [12].

TABLE I

MODEL DEVICE PARAMETERS FOR S/D DOPING

AND CRYSTAL ORIENTATIONS

and analytical/numerical simulation results to explain how theperformance comparison of III-V versus Si changes as wemove from large-scale to small-scale devices.

This paper is organized as follows. In Section II, we explainthe model device and the simulation approach. In Section III,we present simulation results and compare performancemetrics across III-V and Si nMOSFETs. In Section IV,we discuss how the performance of III-V versus Si changeswith device scaling and provide physical explanation. Theconclusion is provided in Section V.

II. APPROACH

Fig. 1 shows the model device diagram. We consider gate-all-around (GAA) NW nMOSFETs with LG = 13 nm,EOT = 0.8 nm, ts = 4.7 nm, and LS = L D = 10 nm,where EOT, ts , and LS /L D are the equivalent oxide thickness,square wire thickness, and the S/D lengths, respectively.As shown in Fig. 1(b), we assume undoped channel anduniform S/D doping profiles with abrupt junctions with nogate overlap or underlap. Table I summarizes model deviceparameters for S/D doping density (NSD) for each materialand crystal orientations. For III-Vs, as discussed in [14],optimum NSD is chosen to balance source exhaustion versussource–drain (S-D) tunneling leakage and maintain goodsubthreshold swing (SS) (or the inverse subthresholdslope). We treat two transport directions, x = [100](confinement directions y/z = [010]/[001]) and x = [110](y/z = [1̄10]/[001]). For (001) wafer, x = [100] (〈100〉 NW)corresponds to the lateral (in-plane) wire with a 45° rotation,whereas x = [110] (〈110〉 NW) represents the lateral wirewith a 0° or 90° rotation.

To obtain I–V and C–V characteristics for the modeldevice, we run atomistic full-band self-consistent ballisticquantum transport simulation using the sp3d5s∗ tight-bindingmodel [15], [16] and nonequilibrium Green’s functionmethod [13]. For the tight-binding model, spin-orbit couplingis not included for numerical simplicity while it is physically

Fig. 2. Simulation results (ballistic and intrinsic with no RSD) for (a) ID–VGand (b) gm –VG for VD = 0.6 V with Vth shifted for IOFF = 100 nA/μm.(c) Extracted SS versus ID . For all results in (a)–(c), NSD is optimizedfor III-V materials (Table I) to maintain a good SS in the OFF-state [14].In addition to the optimum NSD case, (c) also shows how the SS degrades forhigh NSD for the InAs 〈110〉 NW devices. For high NSD values, SS increases,and low IOFF targets cannot even be satisfied due to the S-D tunnelingleakage [14].

justifiable for conduction band transport in nMOSFETs [14].(For more band structure results, such as the dispersion(E–k), density-of-states (DOS), bandgap, and the effectivemass (m∗), also refer to [14].) All simulations are at 300 K.To compare performance across different devices, we shift thethreshold voltage (Vth) to meet the IOFF target (at VG = 0 V,VD = VDD) for a given VDD, and we sweep IOFF and VDDvalues to cover a wide range of operating conditions. Forbenchmarking, NW device quantities are scaled by the wireperimeter (or the effective width). Note that there may be othernormalization methods for NWs (e.g., width, width + spacebetween NWs, etc.), but the relative comparison results acrossdevice materials will not change.

III. RESULTS

A. I–V Characteristics

Fig. 2(a) and (b) shows simulation results for ID versus VG

and transconductance (gm = ∂ ID/∂VG) versus VG forVD = 0.6 V with Vth shifted for IOFF = 100 nA/μmat VDD = 0.6 V. The results are for intrinsic (no RSD) ballistictransport. As shown in the extracted SS versus ID of Fig. 2(c),for the NSD values chosen for each material in Table I, the

KIM et al.: COMPREHENSIVE PERFORMANCE BENCHMARKING OF III-V AND Si nMOSFETs 715

Fig. 3. Simulation results for ID–VD for different VG values (IOFF =100 nA/μm, VDD = 0.6 V). (a)–(c) RSD = 0 � · μm. InAs has little orienta-tion dependence, and ID is low due to the low DOS. GaAs 〈100〉 NW showslow ID , but GaAs 〈110〉 shows higher ID due to the improved DOS withstill high υinj [14], [17], [18]. For III-Vs, VD,sat is higher due to the lowerDOS (high Fermi degeneracy), and linear current is low (RON is high) dueto the smaller number of bands [19]. (d)–(f) Results for RSD = 200 � · μm.Current levels are significantly lowered, and VD,sat increases for all devices.

SS values remain near-ideal (∼60 mV/decade at 300 K) inthe OFF-state. This is critical to III-V materials, especiallyto InAs due to its light m∗ and S-D tunneling. As shownin Fig. 2(c), relatively high NSD (e.g., 2 × 1019 cm−3) isokay for a high IOFF target (e.g., 100 nA/μm), but for lowerIOFF (e.g., 10 pA/μm), NSD should be lower to satisfy theIOFF target and maintain good SS. As shown in Fig. 2(a),III-Vs show a ballistic ID comparable to or lower than thatof Si (while the detailed comparison depends on the biascondition; ID and gm of III-Vs are higher than those of Si at alow VG while they cross over at high VG). As also discussedin previous theoretical studies [6]–[8], this is different fromthe expectation from the classical MOSFET theory, whereIII-V materials with light m∗ (fast carriers, high mobility) willperform better than heavy-m∗ (slow carriers, low mobility)materials such as Si. This is the effect of light m∗ and smallDOS on the interplay of charge density versus carrier velocity.In Section IV, we will explain the effects of m∗ on MOSFETperformance in more detail and discuss how the trend changeswith device scaling (large- versus small-scale MOSFETs)through analytical models and numerical simulations.

Fig. 3 shows simulation results for ballistic ID–VD withdifferent VG’s (IOFF = 100 nA/μm for VDD = 0.6 V)for RSD = 0 � · μm and RSD = 200 � · μm (a practical,current-day value [1] including both S/D components). We first

discuss the intrinsic device (no RSD) results in Fig. 3(a)–(c).For InAs in Fig. 3(a), there is little orientation dependencebetween 〈100〉 and 〈110〉 NWs because only one subband fromthe � valley is relevant [14]. For GaAs in Fig. 3(b), however,there is significant orientation dependence. While GaAs 〈100〉NW shows low ID , GaAs 〈110〉 NW shows improved ID dueto its better DOS with still high carrier injection velocity (υinj),coming from the confinement of L valleys [14], [17], [18].For Si, there is also orientation dependence (changes in theunprimed and primed valleys [20]). In Fig. 3(a)–(c), as alsomentioned for Fig. 2, current levels of III-Vs are comparableto or lower than those of Si. This is due to the small DOSof III-Vs. As will be discussed in Section IV, this resultsin the relative loss of charge density in III-Vs and maydegrade the drive current despite the high carrier velocity(DOS bottleneck [21]). In Fig. 3(a)–(c), we also see twoother characteristics of III-V devices. First, the saturation drainvoltage (VD,sat) is higher for III-Vs. This characteristic isevident as at VG = 0.6 V, ID saturates at VD ∼ 0.4 V for InAsin Fig. 3(a) while it saturates at VD ∼ 0.2 V for Si in Fig. 3(c).The high VD,sat of III-Vs comes from the low DOS, whichgives a high Fermi degeneracy (high EF –EC , where EF is thesource Fermi level, and EC is the conduction band edge in thechannel) in the ON-state. This requires a higher VD to removethe carrier injection from the drain and saturate the current [5].The second characteristic difference of III-Vs is the low ID

in the linear region (Ilin) (or high RON = (∂ ID/∂VD)−1). Thelow Ilin comes from the small number of bands in III-Vs.In NW devices, Ilin is proportional to the number ofmodes [19], where each mode comes from each subband.For III-V NWs, only a small number of bands are relevant(one subband from �-valley for InAs, a few subbands from� and L valleys for GaAs) while for Si NWs, there aremany bands participating in the carrier transport. Therefore,Ilin(InAs) < Ilin(GaAs) < Ilin(Si) in Fig. 3(a)–(c). Notethat the two characteristics (high VD,sat versus low Ilin)of III-V devices come from different but related physicalorigins (small DOS versus small number of bands). Next,we include RSD = 200 � · μm in Fig. 3(d)–(f). We seethat the current levels are significantly lowered comparedwith the intrinsic results in Fig. 3(a)–(c). While the generaltrends in Fig. 3(a)–(c) are still there (e.g., orientationdependence, low Ilin and high VD,sat of III-Vs), theRSD washes out the large current level differences acrossmaterials and increases VD,sat for all cases. This clearlyshows that RSD is a critical parameter in MOSFET I–Vperformance [7].

B. Metrics for Current

Based on the ID–VG and ID–VD simulation results,we calculate current performance metrics for variousVDD’s and IOFF targets. Fig. 4 shows the VDD sweep(IOFF = 100 nA/μm) results for ballistic ID,lin, ID,sat, and Ieffwith and without RSD, where ID,lin is the linear current,ID,sat is the saturation current, and Ieff is the effectiveinverter drive current [11]. Definitions and bias conditions forthese current metrics are summarized in Table II. (The Ieff


Fig. 4. VDD sweep of ballistic current metrics, ID,lin, ID,sat , andIeff [11] (IOFF = 100 nA/μm for each VDD) with (a)–(c) no RSD and(d)–(f) RSD = 200 � · μm. Bias conditions for each metric (Table II) arealso shown. The VDD sweep range is from 0.3 V to the highest availablefrom the numerical simulation result. III-Vs show lower ID,lin. For ID,sat ,III-Vs and Si are comparable at low VDD, while Si outperforms at high VDD.Ieff shows similar trends as in ID,sat . Insets of (b) and (c): enlargementsof the low VDD region (dotted box). Only 〈110〉 NW results shown forsimplicity.

TABLE II

DEFINITIONS AND BIAS CONDITIONS FOR CURRENT METRICS

in Table II corresponds to the inverter output falling delaydue to nMOSFET.) As discussed in Fig. 3, III-Vs show lowID,lin (high RON) in Fig. 4(a) while the difference reduceswhen RSD is included in Fig. 4(d). For ID,sat, III-Vs andSi are comparable at a low VDD while Si outperforms athigh VDD, and Ieff shows similar trends. One thing to noteis that Ieff of III-Vs may be relatively worse, especially forthe intrinsic case in Fig. 4(c), due to the higher VD,sat anddegraded IH (i.e., ID at VG = VDD may not be saturated yetat VD = VDD/2). From this point on, we focus on the Ieffwith RSD = 200 � · μm as a main current metric.

Fig. 5(a)–(c) shows the VDD sweep results for ballisticIeff with RSD = 200 � · μm for various IOFF targets,100 nA/μm, 5 nA/μm, and 10 pA/μm, which correspond toHP, LOP (low operating power), and LSTP/LP (low stand-bypower/low power) in ITRS [1], respectively. In Fig. 5(d)–(f),we show the relative change of Ieff at each VDD from that ofthe Si reference, which is chosen to be the Si 〈110〉 NW device

Fig. 5. VDD sweep of ballistic Ieff for various IOFF targets. (a) 100 nA/μm.(b) 5 nA/μm. (c) 10 pA/μm with RSD = 200 � · μm. (d)–(f) Changes ofIeff at each VDD relative to the Si 〈110〉 NW device. Positive % (direction ofgreen arrows) means Ieff performance improvement relative to the Si baseline.III-V improves over Si at lower VDD’s, and the improvement is greater forlower IOFF targets. Insets of (b) and (c): enlargements of the low VDD region(dotted box). Only 〈110〉 NW results shown for simplicity.

[in-plane NW with no rotation on (001) wafer]. It is clearlyshown that III-V improves over Si at lower VDD’s, and theimprovement is greater for lower IOFF targets. A physicalintuitive explanation is that for low VG -drive above Vth(e.g., lower VDD for the same IOFF target, lower IOFF targetfor the same VDD), the induced channel carrier densityis small so that the low DOS of III-V is less of an issuewhile the high υinj of III-Vs still helps in increasingthe current. As VG -drive increases (high VDD, high IOFF

targets), however, III-Vs lose advantage over Si regardingthe drive current due to the DOS bottleneck. (Recall that weobserved similar trends in ID–VG and gm–VG in Fig. 2, whereIII-Vs perform better than Si for low VG while they crossover at high VG .) One thing to note in Fig. 5(f) is that atextremely low IOFF and small VDD (e.g., VDD < 0.4 V forIOFF = 10 pA/μm), the advantage in Ieff for III-Vs startsdecreasing. This is because all transistors start approaching thesubthreshold region, where the MOSFET current is dominatedby the SS coming from the thermal limit, regardless of thedevice material.

C. Metrics for Capacitance

For capacitance benchmarking, we define

Ceff = QG(VG = VDD, VD = 0) −QG(VG = 0, VD = VDD)

VDD(1)


Fig. 6. (a)–(c) VDD sweep of Ceff,totV2DD (see text for definition) for

different IOFF targets (100 nA/μm, 5 nA/μm, and 10 pA/μm), whereCeff,tot includes the device component and the parasitic fringing capacitance,Ceff,tot = Ceff,dev + CF . CF is assumed to be 0.6 fF/μm with the Millereffect [1]. (d)–(f) Change of Ceff,tot from the Si 〈110〉 NW device. III-Vsshow improvement [capacitance reduction, green arrows (negative %)] overSi due to the small DOS.

where QG is the total gate charge. The Ceff in (1) repre-sents the average gate capacitance for a given VDD includingthe Miller effect. Here, we consider two components,Ceff,dev and CF . The Ceff,dev is from the device QG , whichis the total charge in the model device (Fig. 1) for the givenVG and VD bias conditions obtained through the numericalsimulation. The CF is the gate fringing capacitance, whichis a fixed, parasitic component. We consider the total value,Ceff,tot = Ceff,dev + CF , where we use CF = 0.6 fF/μmfrom ITRS [1]. Fig. 6(a)–(c) shows Ceff,totV 2

DD (power con-sumption) versus VDD for different IOFF targets. [Note thatCeff,dev defined by (1) [and therefore Ceff,tot in Fig. 6] doesnot depend on RSD; ID is either zero (VG = VDD andVD = 0 V) or very small (VG = 0 V and VD = VDD,OFF-state) so that the terminal voltage drops due to RSD arezero or negligible.] We see that the capacitance (and also thepower consumption) is smaller for III-V devices. Fig. 6(d)–(f)shows the relative change of Ceff,tot from the Si reference.III-Vs show improvement over Si (capacitance reductionor power saving), reaching ∼26% and ∼13% reductionin Ceff,tot for InAs and GaAs, respectively. This is due tothe smaller DOS of III-Vs, which gives smaller quantumcapacitance and results in smaller gate capacitance in scaledMOSFETs. More about this effect will be discussedin Section IV. Also note that without the parasitic CF , the

Fig. 7. (a)–(c) VDD sweep of gate-loaded CV/I (Ceff,totVDD/Ieff ) changefrom the Si 〈110〉 NW device for different IOFF targets and RSD. III-V showsimprovement (delay reduction, green arrows) for most of the VDD rangeconsidered due to the reduction of Ceff,tot (Fig. 6), and it improves morefor lower VDD and lower IOFF targets due to the Ieff improvement (Fig. 5).(d)–(f) VDD sweep of interconnect-loaded CV/I (CwVDD/Ieff with a constantCw) change from the Si 〈110〉 NW device. III-Vs intercept Si (longer CV/I )as VDD increases. The intercepting VDD increases for lower IOFF targets.

capacitance benefit of III-Vs would have been larger [e.g., upto ∼70% and ∼35% reduction of Ceff,dev for InAs and GaAs,respectively (not shown)].

D. Metrics for Switching Delay

Finally, we compare the switching delay (CV/I ) perfor-mance. Fig. 7(a)–(c) shows the VDD sweep of the relativechanges of Ceff,totVDD/Ieff from the Si reference for differentIOFF targets and RSD = 200 � · μm. (The actual values forCeff,totVDD/Ieff are not shown; however, they can be calculatedfrom Figs. 5 and 6.) Note that this is the gate-loaded CV/I ,where the load capacitance comes from the device gate capac-itance. The CV/I improves (less delay and faster switching)for III-Vs for most of the VDD values considered while itimproves more for lower VDD and lower IOFF targets. Thereare two components to this result. First, Ceff,tot is smaller forIII-Vs than Si for all of the available VDD range (Fig. 6),which contributes to the global reduction of the gate-loaded CV/I . Second, Ieff improves for III-Vs over Si forlower VDD and lower IOFF targets (Fig. 5), which results inmore CV/I reduction with VDD and IOFF scaling.

Note that the gate-loaded CV/I is not the end of thestory because the load capacitance may come from othercomponents such as interconnects. Therefore, we also consider


the interconnect-loaded CV/I , which we define as CwVDD/Ieffwith Cw being the interconnect wire capacitance. For a first-cutanalysis, if we assume that the Cw is the same across devicematerials and the load capacitance comes solely from Cw

(a pure interconnect-loaded case), we can relatively com-pare the CV/I (without assuming any particular Cw value),as shown in Fig. 7(d)–(f). Note that this is basically com-paring 1/Ieff across devices. The interconnect-loaded CV/Istill improves (less delay) for III-Vs over Si at low VDD’s,and the improvement is larger for low IOFF targets, but themain difference from the gate-loaded results in Fig. 7(a)–(c)is that III-V devices cross over Si (III-Vs delay becomeslarger) at a lower VDD. For IOFF = 5 nA/μm, for example,the gate-loaded CV/I of InAs remains smaller than thatof the Si reference for up to VDD ∼ 0.7 V in Fig. 7(b)whereas for interconnect-loaded CV/I , InAs crosses over Si atVDD ∼ 0.55 V in Fig. 7(e). This is because for theinterconnected-loaded CV/I , the benefit of reduced Ceff,tot(Fig. 6) is not there, and only the Ieff contribution (Fig. 5)survives. For actual devices where the load capacitance comesfrom both gate capacitance and interconnects, the CV/I com-parison across III-V and Si devices will be in betweenFig. 7(a)–(c) (gate loading only) and Fig. 7(d)–(f) (intercon-nect loading only).

E. Summary and Discussion

From the comparison results so far, we conclude that III-VnMOSFETs, when optimally designed (e.g., S/D design fortunneling leakage) for the LG = 13-nm device consideredin Fig. 1, have performance benefits over Si nMOSFETsat low-power (low VDD, low IOFF target) operation, whilethey may lose advantage in the HP region (high VDD andhigh IOFF target). To better visualize this trend, in Fig. 8,we present 2-D color and contour plots of VDD and IOFF

sweeps for the changes of Ieff , Ceff,tot , gate-loaded CV/I , andinterconnect-loaded CV/I of III-V (InAs and GaAs) 〈110〉NW devices from the Si 〈110〉 NW device. For Ieff , III-Vsimprove over Si as VDD and IOFF decrease. [Note that forextremely low VDD and IOFF (lower left corner), the benefitsof III-Vs disappear because all transistors are approaching thesubthreshold region.] As VDD and IOFF increase, Ieff of III-Vsbecomes inferior to that of Si. Also note that the 0% contourof the GaAs 〈110〉 NW device [Fig. 8(e)] is shifted moreto the right compared with InAs [Fig. 8(a)], which meansthat GaAs 〈110〉 NW has better HP capability. For Ceff,tot,III-Vs improve over Si (capacitance reduction) in all IOFF

and VDD regions considered while the amount of reductionis larger for InAs [Fig. 8(b)] than in GaAs [Fig. 8(f)]. Forgate-loaded CV/I , III-Vs improve over Si (delay reduction)for all IOFF and VDD regions considered, and the improvementis larger for smaller IOFF and VDD. [Again, at the lower leftcorner (subthreshold operation), the transistor performancetends to merge.] For interconnect-loaded CV/I , there existbreak-even lines [0% contours from Ieff in Fig. 8(a) and (e)],and III-Vs improve over Si (delay reduction) at a lowVDD and IOFF target while they lose advantage (delay increase)at a high VDD and IOFF target.

Fig. 8. 2-D color and contour plots of VDD and IOFF sweeps for the changes(in percentage) of Ieff , Ceff,tot, gate-loaded CV/I , and interconnect-loadedCV/I of (a)–(d) InAs 〈110〉 NW and (e)–(h) GaAs 〈110〉 NW devices fromthe Si 〈110〉 NW device (Si reference). III-V nMOSFETs have performancebenefits over Si for low-power (low VDD and low IOFF target) operation.

Next, we comment on the effect of scattering. In this paper,we discuss quantum ballistic transport results. We understand,however, that comparing ballistic current may be unfair toIII-Vs because carriers scatter less than in Si due to lowerscattering rates. When scattering is considered, we expect thatthe 0% contours for Ieff in Fig. 8 will shift to the right, makingthe III-V devices improved for a wider range of VDD and IOFF

target. This will in turn improve the CV/I performance ofIII-Vs. Note that for Ceff,tot, the results are not expected tochange with scattering because it is related to electrostaticsrather than to carrier transport. While it is very challengingand beyond the scope of this paper to treat scattering withinthe quantum transport simulation framework, more studies(e.g., full band Monte Carlo simulation) of the scatteringeffect on III-V versus Si comparison will be a very usefulcomplementary work.

Finally, we mention that the results presented in this paperare for nMOSFETs, which may be the half of the story.Performance benchmarking for different material options forpMOSFETs (e.g., Ge versus Si) using a similar approach willbe a very useful follow-up study.


Fig. 9. Schematic of the model devices to compare performance of III-Vand Si nMOSFETs at (a) large scale (LG = 45 nm, thin body/SG) and(b) small scale (LG = 13 nm, NW/GAA).

TABLE III

PARAMETERS FOR THE MODEL DEVICES IN FIG. 9

Fig. 10. Atomistic ballistic quantum transport simulation results forID versus VG (VD = 0.6 V and IOFF = 100 nA/μm) for (a) LG = 45 nmand (b) LG = 13 nm devices (Fig. 9 and Table III). (a) For the large-scaledevice (MOS limit), III-V gives higher current than in Si. (b) For scaleddevices (quantum capacitance (QC) limit), performance of III-Vs and Si iscomparable and depends on the operating condition.

IV. DISCUSSION: EFFECTS OF MOSFET SCALING

In this section, we discuss the effects of m∗ and DOSon MOSFET performance and explain how the performancecomparison of III-V versus Si changes with device scaling.First, we run atomistic quantum transport simulation (approachdiscussed in Section II) for large-scale (LG = 45 nm)and small-scale (LG = 13 nm) III-V and Si nMOSFETs.Fig. 9 and Table III show the model device diagrams andparameters. For LG = 45 nm, we assume a thin-body single-gate (SG) device with a relatively large EOT (1.1 nm).For LG = 13 nm, we use the same GAA NW structurediscussed in Fig. 1. The idea is to run simulations for III-V(In0.7Ga0.3As) versus Si for the same structures at large-scaleand small-scale devices and see how the relative performancechanges with scaling. Fig. 10 shows the simulation resultsfor ID versus VG (VD = 0.6 V and IOFF = 100 nA/μm).For LG = 45 nm in Fig. 10(a), In0.7Ga0.3As clearlyoutperforms Si. This is consistent with the experimental resultsthat showed improved drive current for III-Vs in relativelylarge scale devices [22]. For GAA NW structure in Fig. 10(b),however, In0.7Ga0.3As and Si show comparable ID , and thecomparison depends on VG . (Note that this is in line with the

TABLE IV

MOSFET THEORY AND EFFECTS OF CARRIER EFFECTIVE MASS

results in Fig. 2, where III-Vs showed ID improvement for alow VG while Si outperformed at a high VG .)

To physically and intuitively explain the numericalsimulation result, we introduce an analytical model. Table IVsummarizes the MOSFET theory [virtual source or top-of-the-barrier (TOB) model [5]] that describes the effect of m∗.Basically, the current (I ) is the product of two components,virtual source charge (Q) and injection velocity (υinj). Q isgiven as CG(VG–VT ), where CG is the gate capacitance, andVG–VT is the gate voltage drive. CG is the series combinationof two components, gate oxide capacitance (Cox) and thequantum capacitance (CQ), where CQ is proportional to theDOS of the channel material. Note that in large-scale devices[e.g., large EOT (small Cox), thick body (high DOS)], CQ ismuch larger than Cox (Cox/CQ � 1) so that CG ∼= Cox andQ ∼= Cox(VG − VT ), as in the classical MOSFET theory [2].In this limit (MOS limit), the light m∗ results in the boost ofcurrent due to the increase of υinj, as shown in Table IV. Thecondition, Cox/CQ � 1, however, does not hold anymore asdevice scaling continues. As EOT scales down and multigatestructures [e.g., double gate (DG), GAA] are introduced,Cox increases. On the other hand, CQ decreases due toquantum confinements in thin body or NW devices. Thisresults in CG (and Q) reduction, CG < Cox, and the reductionis greater for smaller CQ . In the limit of Cox/CQ � 1(quantum capacitance (QC) limit), CG ∼= CQ , and CG has aDOS dependence. To exemplify the effects of m∗, we treattwo cases, ideal 1-D channel (DOS ∝ √

m∗) and ideal2-D channel (DOS ∝ m∗). From the overall m∗-dependencein Table IV, we see that lighter m∗ may not help (1-D) or mayeven degrade the current (2-D). This is because the loss of Q(due to the light m∗ and small DOS) is large so that it mayeventually cancel out the gain in υinj.

To provide more insights into the physics, we presentsimple calculation results in Fig. 11. We assume three casesin Fig. 11(a)–(c) to study the channel dimensionality and gateoxide capacitance. We then sweep the m∗ of the channelfrom heavy to light values and calculate the ballistic cur-rent using the semiclassical TOB model with an ideal gatecontrol [23]. (Note that the effect of LG is not relevantto this simple TOB model with ballistic transport and idealelectrostatics.) Fig. 11(d)–(f) shows the m∗ sweep of ballistic


Fig. 11. Semiclassical single-band TOB [23] calculation to explore the effectof m∗. Model devices with (a) SG/large EOT/2-D channel, (b) DG/smallEOT/2-D channel, and (c) GAA/small EOT/1-D channel. The m∗ of channelis swept from m0 to 0.01m0. (d)–(f) ID,sat (VDD = 0.6 V and IOFF =100 nA/μm) versus m∗ for the devices in (a)–(c). Blue dashed lines in (d)–(e)represent the optimum m∗ where ID,sat is maximized. Shaded area representsthe region where the average CQ is smaller than Cox. Two red dots are form∗ = 0.05m0 (light m∗ as in III-Vs) and m∗ = 0.2m0 (heavy m∗ as in Si).

ID,sat for the three model cases. For the 2-D SG/large EOTdevice [Fig. 11(a)], ID,sat first increases with decreasing m∗(MOS limit) and then starts decreasing as m∗ decreasesfurther to the QC limit. For the 2-D DG/small EOT device[Fig. 11(b)], ID,sat versus m∗ shows similar trends, but theoptimum point moves to the heavier m∗ [dashed blue linesin Fig. 11(d) versus (e)]. For the 1-D GAA/small EOT device[Fig. 11(c)], ID,sat versus m∗ first increases and then saturatesas m∗ decreases, as shown in Fig. 11(f). In Fig. 11(d)–(f),we also mark the results for m∗ = 0.05m0 (light m∗ asin III-Vs) and m∗ = 0.2m0 (heavy m∗ as in Si) with m0being the free electron mass. For 2-D SG/large EOT, lighterm∗ clearly gives ID,sat improvement, as in our numericalsimulation result for the large-scale device in Fig. 10(a). For2-D DG/small EOT or 1-D GAA/small EOT, however, thelight and heavy m∗’s show less difference, as in our numericalsimulation results for the small-scale devices in Fig. 10(b)and Section III. This suggests that the performance com-parison of III-Vs versus Si strongly depends on the gategeometry. Finally, we note that while the simple modelin Fig. 11 assumes an ideal SS (through device engineeringsuch as S/D doping), it becomes increasingly challengingto achieve it for extremely light m∗ material due to theS-D tunneling in short channel devices [14].

V. CONCLUSION

In this paper, we presented performance projection of III-Vand Si nMOSFETs through quantum transport simulation

for relevant future structures with LG = 13 nm. From thecomprehensive comparison results for current, capacitance,and switching delay metrics, we see that III-V nMOSFETs,when optimally designed (S/D design for tunneling leakageand material/orientation for band structure), have performancebenefits over Si for low-power (low VDD, low IOFF target)operation while they may lose advantage at the HP (high VDD,high IOFF target) region. We also presented analytical modelsand simple calculation results to explain the effects of m∗on the MOSFET performance and how that affects theperformance comparison of III-V versus Si with devicescaling. We expect that the results reported here will provideinsights into the physics of material choices for futuretransistor technology.

ACKNOWLEDGMENT

The authors would like to thank G. Dewey, J. Kavalieros,R. Rios, C. E. Weber, R. Kotlyar, and T. Ghani at IntelCorporation for their helpful discussions.

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Raseong Kim (M’11) received the Ph.D. degreein electrical and computer engineering from PurdueUniversity, West Lafayette, IN, USA.

She is currently a Senior Process TD Engineerwith Intel Corporation, Hillsboro, OR, USA.She has been involved in research on charge-basedexploratory IC devices.

Uygar E. Avci (M’05) received the Ph.D. degreein applied physics from Cornell University, Ithaca,NY, USA.

He joined Intel Corporation, Hillsboro, OR, USA,in 2005, where he has focused on novel memorydevices and demonstrated industry-leading floatingbody cell memory. He is currently a Principal Engi-neer, leading the research for charge-based beyond-CMOS devices and circuits.

Dr. Avci is also an Associate Editor of the IEEETRANSACTIONS ON ELECTRON DEVICES.

Ian A. Young (F’95) received the Ph.D. degree inelectrical engineering from the University of Cali-fornia at Berkeley, Berkeley, CA, USA.

He is currently a Senior Fellow and the Director ofExploratory Integrated Circuits with the Technologyand Manufacturing Group, Intel Corporation, Hills-boro, OR, USA.

He is the Editor-in-Chief of the IEEE Journal onExploratory Solid-State Computation Devices andCircuits.

Comprehensive Performance Benchmarking of III-V and Si nMOSFETs (Gate Length = 13 nm) Considering...

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