EEEB273 Sem. 1 09/10 BJT Current Source

Dr Fazrena Hamid 1

Chapter 10 (Part 1): IC Biasing and BJT Current source

Content • Current mirrors and current source • Improvements of current mirror circuits, Widlar and Wilson

current mirror

• Multitransistor current mirror

Introduction • for discrete circuit: use voltage-divider resistor network

• for integrated circuit: o resistor unsuitable: consume large

area on IC and must use large

(microfarad) capacitor

o biasing uses constant current

sources

Current source circuits • Simplest: two-transistor current source

need to improve approximation of IO = IREF

need to improve stability of IO by having higher RO

(output resistance)

• Improved current source topologies basic three-transistor: better approximation of IO =

IREF

Cascode: higher RO by factor of β Wilson: higher RO by factor of β/2 Widlar: higher RO by (1 + gmRE’)

EEEB273 Sem. 1 09/10 BJT Current Source

Dr Fazrena Hamid 2

Two transistor current source

• also called current mirror: two matched transistors, Q1 & Q2 • Q1 is diode-connected • Q1 & Q2 have the same VBE voltages • Reference current IREF established by R1 :

1R

VVVI BEREF

−+ −−=

Current relationships:

• Sum currents at collector of Q1

• IC1 = IC2 and β/22 CB II =

• Output current β2

12

+== REF

OC

III

# Design Example 10.1

# Ex 10.1, TYU 10.1

EEEB273 Sem. 1 09/10 BJT Current Source

Dr Fazrena Hamid 3

Significance of output resistance

• Finite Early voltage, VA thus ro is finite.

• Stability of IO is affected by the bias conditions in the load circuit

If VBE << VA, then

A

O

OOCE

O

V

I

rRdV

dI==≅

22

11

# Example 10.2

# Ex 10.2

EEEB273 Sem. 1 09/10 BJT Current Source

Dr Fazrena Hamid 4

Improved current source circuits

1) Basic three-transistor current source

Current relationships:

• Sum currents at collector of Q1 • IC1 = IC2 and β/22 CB II =

• Output current )1(

21

3

2

ββ ++

== REFOC

III

Reference current IREF is:

11

3 2

R

VVV

R

VVVVI BEBEBEREF

−+−+ −−≅

−−−=

Advantages:

• Better approximation of IO to IREF

• IO less sensitive to variation in β

# Example 10.3

# Ex 10.3, TYU 10.2

EEEB273 Sem. 1 09/10 BJT Current Source

Dr Fazrena Hamid 5

2) Cascode current source

• Improved output resistance, RO ≅βro4 (proven by small-signal analysis)

• IO = IREF

3) Wilson current source

• Improved output resistance, RO ≅ (β/2) ro3

• Current relationship similar to three-transistor current source, i.e.

# TYU 10.3

( )

++

×==

ββ 2

21

13 REFCO III

EEEB273 Sem. 1 09/10 BJT Current Source

Dr Fazrena Hamid 6

4) Widlar current source

For low load currents suitable for IC implementation

Current relationship:

• Assume β >>1 and Q1 & Q2 are identical

• (1) Equate collector currents with respective VBE voltages

o Solving the VBE voltages

o Substract one VBE voltage from

the other

• (2) Loop equation (KVL) with RE

• Combining equations to obtain

=

O

REFTEO

I

IVRI ln

# Design example 10.4

# Ex 10.4

# Example 10.5 Note: To find IO (given R1 and RE): trial & error

# Ex 10.5

EEEB273 Sem. 1 09/10 BJT Current Source

Dr Fazrena Hamid 7

Output resistance of Widlar

Output resistance Ro is a factor of (1 + gmRE’) larger (proved by small-

signal analysis)

Where RE’=RE||rπ

• Note: In ac equiv cct below, Ro1 is very small signal ground

#Example 10.6 (Computer verification)

• RO (Widlar) = 36.6 MΩ % change in IO is 2.28 %

• RO (2 transistor) = 75.8 kΩ % change in IO is 13.2 %

# Ex 10.6

( ) ( )( )πrRgrRgrR EmoEmoO ||11 22

'

22 +=+≅

EEEB273 Sem. 1 09/10 BJT Current Source

Dr Fazrena Hamid 8

IC fabrication and mismatched transistor

• In IC fabrication adjacent transistors are well-matched • If transistors are mismatched, then IS1 ≠ IS2

o Neglecting Early effect and base currents

=

1

2

S

SREFO

I

III

o Can use different sizes of transistors to

obtain IO ≠ IREF

• IC resistors can be any value

Output voltage swing

• For two-transistor c.s.: maximum output swing depends on VCE2(min) i.e. VCE (sat) 0.1 to 0.3 V

• For cascode & Wilson c.s.: VOUT(min) = VBE + VCE (sat)

above V- 0.7 to 0.9 V

• In low-power circuits, the increase in VOUT(min) is critical.

EEEB273 Sem. 1 09/10 BJT Current Source

Dr Fazrena Hamid 9

Multitransistor current mirror

• To generate multiply load currents from a single

reference current

• For all N transistors and QR

are matched, with VA

infinity:

β)1(

1

....21 N

IIII REFONOO +

+===

Multioutput transistor current source

• Collectors are connected, so IO ≠ IREF

I1 = I2 = I3 = IREF IO = 3IREF

• Transistors are connected in parallel to increase effective

B-E area, hence output current is increased.

Symbols of two, three and

N transistors in parallel

EEEB273 Sem. 1 09/10 BJT Current Source

Dr Fazrena Hamid 10

Generalized current mirror

• Obtain several IO‘s as multiples of a single IREF

• pnp to ‘source’ current • npn to ‘sink’ current • Effect of finite β: approximation IO to (N.

IREF) less accurate as N

increases

# Design Example 10.7

# *Ex 10.7