IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 27, NO. 4, OCTOBER 2012 1727

Analysis, Design and Control of a UnifiedPower-Quality Conditioner Based on a

Current-Source TopologyPedro E. Melín, Student Member, IEEE, José R. Espinoza, Member, IEEE, Luis A. Morán, Fellow, IEEE,José R. Rodriguez, Fellow, IEEE, Victor M. Cardenas, Member, IEEE, Carlos R. Baier, Member, IEEE, and

Javier A. Muñoz, Member, IEEE

Abstract—This paper presents a three-phase unified power-quality conditioner based on current source converters(CSC-UPQC), including the design guidelines of the key compo-nents, an appropriate control scheme, and a selection procedureof the dc current level. Particularly, the ridethrough capabilitycriterion is used to define a minimum dc current level so that theCSC-UPQC achieves the same characteristics as a UPQC basedon voltage-source converters in terms of voltage disturbancecompensation in the point of common coupling (PCC) and loadpower factor compensation. A 1.17 MVA load fed from a 3.3 kVsystem is used to show the proposed design procedure, and a labo-ratory prototype is implemented to show the system compensatingsags and swells using low switching frequency in the CSC andmaintaining a unitary displacement power factor in the PCC.

Index Terms—Current source converters, nonlinear control,power quality (PQ), unified power-quality conditioner (UPQC).

NOMENCLATURE

Point of common coupling voltages.

Point of common coupling currents.

Series stage capacitor voltages.

Shunt stage capacitor voltages.

Shunt stage inductors currents.

Load voltages.

Load currents.

Modulating vector.

DC current.

Manuscript received November 16, 2010; revised March 30, 2011, August10, 2011, January 11, 2012, and April 10, 2012; accepted April 23, 2012. Dateof publication June 25, 2012; date of current version September 19, 2012. Thiswork was supported by the Chilean Government under Project FONDECYT111-0794. Paper no. TPWRD-00878-2010.P. E. Melín, J. R. Espinoza, and L. A. Morán are with the Electrical Engi-

neering Department, Concepcion University, Barrio Universitario, Concepción4070409, Chile .J. R. Rodriguez is with the University Federico Santa Maria, Valparaiso,

Chile.V. M. Cardenas is with the Universidad Autónoma de San Luis Potosí, Engi-

neering, Zona Unviersitaria, San Luis Potosi, San Luis Potosi 78290, Mexico.C. R. Baier and J. A. Muñoz are with the Electrical Engineering Department,

Concepcion University, Concepcion, Chile.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TPWRD.2012.2199524

Load voltage angle.

PCC power factor.

Load power factor.

Harmonic order.

Stationary coordinates.

Rotating coordinates.

I. INTRODUCTION

T HE power-quality (PQ) problems affect customers andsuppliers at the same time [1], [2]. Fortunately, the re-

cent developments in PWM converters have allowed their use inshunt and series active filters in order to mitigate the aforemen-tioned problems minimizing the hassle of resonance problemsas in passive filters [3], [4]. Series active filters can compensatefor problems associated with the supply voltage, and shunt ac-tive filters can compensate for problems associated with currentharmonics and poor load power factor.The unified power-quality conditioner (UPQC) in this paper

is based on the union of a series active filter and a shunt ac-tive filter sharing a common dc reactor [5]. The resulting equip-ment is installed close to a critical load (Fig. 1) and it has theability to compensate simultaneously with the PCC voltage andload power factor. Currently, the study of these topologies usingVSCs is well documented [6]–[8] but not using current sourceconverters (CSC), which are used as an alternative to the VSC,for instance, in medium-voltage (MV) drives [9]. The use ofCSC in UPQCs should add the advantages: 1) rapid response toaccommodate voltage disturbances due to the existence of just afirst-order filter stage and 2) natural protection against short cir-cuits due to the dc link reactor. Previous works concerning theUPQC based on current source converters (CSC-UPQC) havepresented control strategies but they do not consider: 1) a deepanalysis of the topology; 2) component and controllers designguidelines, 3) considerations for choosing an operating point,nor 4) the natural limited compensation capability of the equip-ment [10], [11]. This work reviews the aforementioned consid-erations and proposes design guidelines for the components andcontrol scheme parameters. The design guidelines are used tocharacterize a UPQC for a 1.17 MVA linear load fed from a3.3 kV system, and a laboratory prototype is implemented andtested.

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1728 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 27, NO. 4, OCTOBER 2012

Fig. 1. UPQC application.

II. UPQC-BASED-ON CURRENT SOURCE CONVERTERS

A. Description and Operation

A back to back approach based on CSCs is used in the pro-posed UPQC [Fig. 2(a)]. The topology is connected to the distri-bution line through passive filters aimed at mitigating thegenerated by the switching of the power valves of the CSCs.The topology, in combination with the proposed control

scheme, is able to modify the voltage of the load and thecurrent drained from the PCC . For the case of compen-sating the voltage disturbances in the PCC, the series activefilter stage injects a voltage in a controlled manner for com-pensating either a sag [Fig. 2(d)] or a swell [Fig. 2(e)], whilethe load power factor is compensated by modifying either thecurrent in the PCC by means of the shunt filter currentor modifying the phase of the load voltage by means of theseries active filter voltage [Fig. 2(c)]. In this paper, the loadpower factor compensation is achieved using a fixed angle ,while the shunt active filter stage: 1) compensates the phaseshift introduced by the LC filter, 2) compensates small varia-tions in the load power factor, and 3) maintains constant the dclink current, reducing the losses in the LC filter compared tocompensating the full power factor with this stage. Then, theangle of the load voltage is chosen as

(1)

where is the load displacement angle, is the PCC powerfactor, and is the displacement angle in the PCC.

B. Modeling

The topology is modeled using the approach presented in[12]. Hence, according to Fig. 2(c), one can write

(2)

(3)

(4)

(5)

(6)

(7)

The ac currents ( and ) and dc voltages ( and )are pulsewidth-modulated (PWM) signals and they satisfy

(8)

(9)

(10)

(11)

where and correspond to the average modulatingvectors of the switching functions and , respectively,and and correspond to the gain of the PWM technique( for the SPWM case).Finally, one can write in a synchronous frame

(12)

(13)

(14)

(15)

where

(16)

and is the ac network frequency.

C. DC Current and Ridethrough Capability

The losses in the topology are a function of the dc currentlevel, so the lower dc current in the topology, the lower thelosses are, while a higher dc link inductance implies a biggerequipment size and internal resistance, increasing the losses dueto the factor. However, as shown later, reducing the dccurrent level or the dc inductor size has implications on theCSC-UPQC compensation capability, especially in terms of thePCC voltage compensation range.From (2) and considering that the voltage to be injected

through the series stage is conveniently defined by

(17)

where is the load desired rms voltage and definingas the ratio of the PCC voltage to the nominal load voltage as

(18)

( for swell and for sag), it is possible toobtain the required dc current from the state variable model foran operating point as

(19)

where

(20)

(21)

MELÍN et al.: ANALYSIS, DESIGN AND CONTROL OF A UNIFIED PQ CONDITIONER 1729

Fig. 2. UPQC based on current-source converters. (a) Power topology. (b) Equivalent circuit per phase . (c) Phasorial diagram for nominal conditions.(d) Phasorial diagram for a sag condition. (e) Phasorial diagram for a swell condition.

Using (19), one can conclude that higher the term is,the lower the required dc current is. On the other hand, by ne-glecting the losses (just to find the next expression), one showsthat the load power is defined by

(22)

where is the power provided by the PCC defined by

(23)

and and are the power provided by the seriesstage and the shunt stage of the UPQC, respectively. In steadystate, is equal to and is equal to zero, then theUPQC must either inject or absorb the power difference in thePCC under transients conditions by means of the series stage,which either drains or injects this power into the dc side, thus

(24)The power transferred from the dc side into the ac side during

the period by the CSC in the series stage can also bedefined by

(25)From (25), one can conclude that compensating perturbations

in the PCC voltagewill produce a change in the dc current. How-ever, the higher the dc current or the higher is, the higherthe UPQC capacity is to compensate for voltage disturbances atthe expense of higher losses in the topology and higher size and

cost of the equipment. On the other hand, (19) shows that thereis a minimum dc current required to compensate a disturbancedefined by without bringing the series CSC into overmod-ulation ( or ). Then, it is necessaryto obtain this current for a given load and a desired range ofvoltage disturbances to compensate. Finally, a dc current levelfor nominal operation higher than the minimum dc current isconsidered and the dc reactor using (25) is finally chosen.

III. KEY DESIGN GUIDELINES

The CSC–UPQC can be simplified as presented in Fig. 3(a)and (b) for the fundamental component and any harmonic com-ponent, respectively, for designing purposes. Differently, the dcinductor design considers a compensating range for voltage dis-turbances.

A. Design Guidelines for the Shunt Stage

The resonant frequency of the LC filter is

(26)

For design purposes, one can further simplify the CSC in theseries stage as Fig. 3(c) shows, considering it an open circuit andthe load and the capacitor in the series stage like an impedance

[Fig. 3(e)] in series with the LC filter defined by

(27)

These results are used to design the LC filter according to[13], where and are calculated to obtain a desirablefrequency response, THD for the current in the shunt stage

1730 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 27, NO. 4, OCTOBER 2012

Fig. 3. Simplified circuit of CSC-UPQC. (a) Equivalent circuit for fundamental frequency. (b) Equivalent circuit for harmonics . (c) Simplified circuit for theshunt stage analysis. (d) Simplified circuit for the series stage analysis. (e) Simplified circuit with equivalent impedance for the shunt stage. (f) Simplified circuitwith equivalent impedance for the series stage.

Fig. 4. and for different values of (p.u). (a) 100 . (b) 100 .

, and THD for the capacitor voltage ne-glecting and then its effect in the current harmonics mustbe evaluated considering .

B. Design Guidelines for the Series Stage

From Fig. 3(b), it is possible to further simplify the UPQC asFig. 3(d) shows in order to obtain an equivalent impedancein parallel with through the coupling transformer [Fig. 3(f)]defined by

(28)

In order to ensure a desired THD in the capacitor voltage,is considered in the calculations of the value of .

The THD of the injected voltage is defined by

(29)

where corresponds to the fundamental component of thevoltage in and corresponds to the harmonic of thevoltage in and are defined by

(30)

(31)

where is the gain of the PWM technique for the harmonicand is the maximum PWM current injected by the CSCin the series stage and is defined by

(32)

and corresponds to the CSC modulation index in the seriesstage. Considering (30) and (32), one can obtain

(33)

Then, considering (29)–(31) and (33)

(34)

is introduced for a particular PWM technique as

(35)

and Fig. 4(a) shows for the SPWM technique as a functionof the modulating index and various normalized carrier fre-quencies . Hence, using (34), becomes

(36)

C. DC Reactor Design Guidelines

The dc reactor should accumulate enough energy to compen-sate sags/swells in the PCC voltage and limit the THD of the dccurrent defined by

(37)

where is the harmonic in the dc current and is thecontinuous component of the dc current. Because the voltage

MELÍN et al.: ANALYSIS, DESIGN AND CONTROL OF A UNIFIED PQ CONDITIONER 1731

harmonics on the dc side of the topology are defined by the sum-mation of the dc voltages in each CSC, the voltage harmonic

in the dc side of the topology becomes

(38)

therefore, each dc current harmonic is given by

(39)

where and correspond to the dc voltage harmonicgain of the PWM technique for the harmonic of the series andshunt CSC, respectively. The highest dc harmonic voltage gainis achieved when the modulation index is the highest and thiscondition occurs—according to (19)—for the CSC in the seriesstage. Therefore, it is possible to simplify the dc link voltageharmonics computation considering just the series stage modu-lation index and using (30) as

(40)

Hence, considering (37), (39), and (40) one has

(41)

In the series stage, the capacitor voltage and the PWMcurrent of the CSC are defined by

(42)

(43)

respectively, combining (41)–(43), one has

(44)

where corresponds to the contribution of distortion of themodulating technique and it is defined as

(45)

Finally, solving for in (44), one gets

(46)

Fig. 4(b) shows for the SPWM technique as a function ofthe modulation index for different values of the normalizedcarrier frequency . Thus, (46) gives the dc inductor size as afunction of a desired THD of the dc current.The ridethrough capability criterion is also considered in the

design procedure to ensure the ability to compensate for voltage

disturbances (25). Defining the initial current as a pro-portion of the current after the disturbance hence

(47)

and (25) can be written as

(48)

where can be obtained for an extreme case of sag/swell tobe compensated and corresponds to the number of net-work cycles. Clearly, (48) shows that by increasing the dc cur-rent, the required size decreases; however, the losses willincrease because of the higher . The design of shouldconsider a minimum current required to compensate the distur-bance , which can be obtained from (19) and an accept-able variation of the dc current during the disturbance . Fi-nally, the inductor should be chosen considering (46) and(48), selecting the value that meets both conditions.

IV. CONTROL SCHEME

A control scheme based upon an inner input/output lineariza-tion technique is proposed since the system is nonlinear (Fig. 5).This approach ensures the desired dynamic within the operatingregion and enables designing outer controllers based on the sys-tems parameters and the modulating technique [14], [15].

A. Series Stage Control

The control objectives of the series stage are regulating therms value and the phase of the load voltage by manip-ulating the components of the series capacitor voltage .Considering (12)–(15) and in order to have a linear relation for, the input/output linearization technique suggests defining

an auxiliary input vector as

(49)The previous expression allows defining the CSC inputs

according to the auxiliary inputs and system state variables[Fig. 5(a)] as

(50)

Hence, a first-order relationship between the capacitorvoltage and is obtained as

(51)

The resulting system is a pure integrator and it could be con-trolled by a P regulator, but small variations in the parameterswould generate a steady-state error since in (50) cannot beexactly computed. Then, a PI regulator is proposed as

1732 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 27, NO. 4, OCTOBER 2012

Fig. 5. Proposed control scheme. (a) Control scheme for the series stage. (b) Control scheme for the shunt stage.

(52)

then

(53)

In order to compensate for the zero in (53), a first order filterbetween and is defined [Fig. 5(a)], allowing atypical second order relationship between and . Theparameters of the PI can be defined as a function of a desirednatural frequency and damping ratio as

(54)

(55)

Finally, the reference for can be obtained from (17). Forthe loop, tuning is recommended to use a natural frequencyat least five times greater than the switching frequency of theCSC. Otherwise, the delay should be considered in the model.

B. Shunt Stage Control

In order to control the PCC power factor and the dccurrent , the control strategy will be based on regulatingby the shunt stage as a slave loop, and a master controller

is synthesized to control the and , Fig. 5(b). The inputsare not present in the dynamics (14), so the input/output

linearization technique requires deriving this expression untilthe inputs appear. Hence

(56)

using the state variable model (12)–(15), one can write

(57)

where

(58)

(59)

(60)

(61)

and is the angular frequency of the ac network and is theresonance angular frequency of the LC filter (26).The second derivative of is a nonlinear function of the

state variables, disturbances, and system entries. Imposing a de-coupled behavior for requires an auxiliary input as

(62)

where it is possible to define in matrix form as

(63)

with

(64)

(65)

MELÍN et al.: ANALYSIS, DESIGN AND CONTROL OF A UNIFIED PQ CONDITIONER 1733

Then, equating (57) and (63) and solving for

(66)

The dynamic between and is defined by (62); how-ever, small variations in the parameters will lead to small errorsin the computation of (66) and steady-state errors. This is over-come by adding an integrative block [Fig. 5(b)] betweenand the current reference as

(67)

resulting in a third order relationship between and

(68)

Then, using the ITAE criterion, one can obtain the constants, , and for a desired settling time of this loop [14].

C. DC Current Control

A master loop over the control loop to regulate the dc cur-rent is added Fig. 5(b). Neglecting the loses of the CSC (just toobtain the next expression), it is possible to write a power bal-ance between the ac side and dc side of the topology as

(69)

defining an auxiliary input as

(70)

then, an appropriate reference for the control loop using(69) and (70) becomes

(71)

where

(72)

corresponds to the power taken by the topology, including thelosses in the CSCs and the dc reactor in the term andthe power either consumed or injected by the series stage in theterm , where is the dc voltage of the CSC in theseries stage that can be calculated as

(73)

The auxiliary input defined in (70) requires the computa-tion of (71) and small parameter variations that will lead tosteady-state errors. Therefore, a PI regulator between the auxil-iary input and a dc current reference given by

(74)

is added leading to a second order relationship betweenand as

(75)

A first order filter between and is added to com-pensate the zero [Fig. 5(b)]. Finally, the previous block allowsa standard second order relationship between and .Thus, it is possible to define the PI parameters as a function of adesired natural frequency and damping ratio for thisloop as

(76)

(77)

Because the dc link current loop is the master loop, it isadvised to set its settling time at least 5 times slower than .

D. Power Factor Control

This loop basically sets the reference for the inner loop fora given power factor reference . The PCC power factorcan be defined as

(78)

where and are the reactive and active power, respec-tively, and are defined in the rotating frame by

(79)

(80)

Defining conveniently an auxiliary input as

(81)

therefore can be used to control the by defining theappropriate reference as

(82)Hence, the dynamic response of the power factor loop is given

by the dynamic of the loop. The final block diagram is de-picted in Fig. 5(b).

V. CASE OF EXAMPLE

A load of 1.17 MVA with a 0.85 inductive power factor feedfrom a 3.3 kV, 50 Hz is used as a theoretical example. The pa-rameters are shown in Table I, and the control parameters andcriteria are shown in Table II. The SPWM technique is set to usea carrier frequency of 750 Hz (15 p.u.) for the CSCs modulationand the LC resonance frequency is set at 3.5 p.u. Using(28), considering that , an acceptable(10%) and (36), the series capacitor becomes

(83)

1734 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 27, NO. 4, OCTOBER 2012

TABLE ICSC-UPQC PARAMETERS

TABLE IICONTROLLERS PARAMETERS

Fig. 6. Minimum dc current versus for various PCC power factors .

In order to obtain the size using the ridethrough capabilitycriterion, the relationship between and is depicted inFig. 6 for kpcc from 0.7 to 1.2 for different values of . Theplot shows that while the is closer to the unity, the lower isthe dc current required by the CSC-UPQC. Considering a min-imum dc current equal to 235 A for 0.75 and 1,

7 ms/20 ms, where the dc current must be compen-sated by the shunt control loop and a nominal dc current equalto 270 A 1.15), then using (48)

(84)

On the other hand, imposing a (20%) fordesign purposes one has by using (46)

(85)

Fig. 7. Experimental steady-state waveforms for 1 and 1.

Because the value of obtained by the ridethrough capa-bility criterion meets the THD criterion, the value obtained in(84) should be finally considered.

VI. EXPERIMENTAL RESULTS

A low-power prototype was assembled in order to test the the-oretical approach. The equipment was designed to compensatea 2 kVA inductive load (0.8 lagging power factor) (Table I). TwoDSP TMS320C6713 systems are used to implement the controlscheme algorithms in order to control independently the shuntstage and the series stage using the parameters that are shown inTable II calculated by using the proposed design procedure andguidelines. The expressions shown in Fig. 5 were properly con-verted to discrete mathematics using standard control theory.The tests were implemented using a load nominal voltage of 74V and 5 A in the dc link current.Fig. 7 shows the CSC-UPQC operation under nominal con-

ditions meaning no sag/swell but unitary displace-ment power factor in the PCC . The PCC currentis in phase with the PCC voltage showing unitary displacementpower factor in the PCC.Using a programmable three-phase voltage source, the

system was tested under a sudden 17% swell 1.17) andsudden 10% sag 0.9) conditions, which are presentedin Figs. 8 and 10, respectively. In both cases, the CSC-UPQCis able to compensate for the PCC voltage perturbation byholding the load voltage in the desirable value in less than oneac cycle. In both cases, there is a dc current variation becausethe energy is transiently either injected (for a swell) or drawn(for a sag) from the dc link. The proper dynamic operation con-firms that the shunt stage control loop prevents the dc currentvalue from decreasing beyond the minimum value required forcompensation and goes back to the desired value in less than250 ms, without affecting the performance of the power factorcorrection and load voltage. Finally, Figs. 9 and 11 show theoperation of the CSC-UPQC in steady state under a sustainedswell (17% 87 V in the PCC, CH1) and sag (10% 67 V

MELÍN et al.: ANALYSIS, DESIGN AND CONTROL OF A UNIFIED PQ CONDITIONER 1735

Fig. 8. Dynamic behavior for a step up (17% swell) of the PCC voltage. (Thepcc voltage is used to trigger the scope.)

Fig. 9. Steady-state waveforms for and a permanent swell of 17%of the PCC voltage.

Fig. 10. Dynamic behavior for a step down (10% sag) of the PCC voltage. (Thedc link current is used to trigger the scope.)

in the PCC), respectively. The plots show that the equipmentis able to keep the desirable condition for the PCC (unitarydisplacement power factor) and load (constant rms voltageclose to 74 V).

Fig. 11. Steady-state waveforms for and a permanent sag of 10%of the PCC voltage.

VII. CONCLUSIONS

A CSC-based UPQC in combination with an appropriate con-trol strategy based on the input/output linearization is presented.This allows the design of the controllers independent of the op-erating point and only dependent on the topology capacitorsand inductors size as well as the PWM technique. The resultingtopology in combination with the control scheme can providecurrents and voltages as required by the references independentof the operating point and for all of the desired compensationrange as in voltage-source-based topologies. A low power lab-oratory setup confirms the theoretical considerations as variousstatic and dynamic tests demonstrate the performance.

REFERENCES

[1] E. W. Gunther and H. Mehta, “A survey of distribution system powerquality-preliminary results,” IEEE Trans. Power Del., vol. 10, no. 1,pp. 322–329, Jan. 1995.

[2] M. F. McGranaghan, D. R. Mueller, and M. J. Samotyi, “Voltagesags in industrial system,” IEEE Trans. Ind. Appl., vol. 29, no. 2, pp.397–503, Mar./Apr. 1993.

[3] H. Akagi, “Trends in active filters line conditioner,” IEEE Trans. PowerElectron., vol. 9, no. 3, pp. 263–268, May 1994.

[4] H. Akagi, “New trends in active filters for power conditioning,” IEEETrans. Ind. Appl., vol. 32, no. 6, pp. 1312–1322, Nov./Dec. 1996.

[5] H. Fujita and H. Akagi, “The unified power quality conditioner: Theintegration of series active filters and shunt active filter,” IEEE Trans.Power. Electron., vol. 13, no. 2, pp. 315–322, Mar. 1998.

[6] M. H. H. Chen, “Modeling and controlling of unified power qualityconditioners,” in Proc. Conf. Rec., Hong Kong, China, pp. 413–435.

[7] C. Sepúlveda, J. Espinoza, L. Moran, and R. Ortega, “Analysis anddesign of a linear control strategy for three-phase UPQCs,” in Proc.Conf. Rec., Nov. 2004, vol. 3, pp. 3060–3065.

[8] L. Landaeta, C. Sepúlveda, J. Espinoza, and C. Baier, “A mixedLQRI/PI based control for three-phase UPQCs,” in Proc. Conf.IECON, Nov. 2006, pp. 2494–2499.

[9] P. Kenneth, “Current-source converter for AC motor drives,” IEEETrans. Ind. Appl., vol. IA-8, no. 6, pp. 679–683, Nov. 1972.

[10] D. Graovac, V. Kati, A. Rufer, and J. Kne, “Unified power quality con-ditioner based on current source converter topology,” presented at theConf. Rec. Elect. Power Eng., Graz, Austria, Aug. 2001.

[11] K. Vadirajacharya, P. Agarwal, and H. Gupta, “A simple controlstrategy for unified power quality conditioner using current sourceinverter,” in Proc. Conf. Rec. IPEC, May 2008, pp. 1219–1223.

[12] P. Melin, J. Espinoza, N. Zargari, M. Sanchez, and J. Guzman, “Mod-eling issues in three-phase current source rectifiers that use dampingresistors,” in Proc. Conf. Rec., Jan. 2007, vol. 2, pp. 453–458.

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[13] N. Zargari, G. Joos, and P. Ziogas, “Input filter design for PWMcurrent-source rectifiers,” IEEE Trans. Ind. Appl., vol. 30, no. 6, pp.1573–1579, Nov./Dec. 1994.

[14] J. Espinoza and G. Joos, “State variable decoupling and power flowcontrol in PWM current-source rectifier,” IEEE Trans. Ind. Electron.,vol. 45, no. 1, pp. 78–87, Feb. 1998.

[15] P. Melín, J. Espinoza, J. Muñoz, C. Baier, and E. Espinosa, “Decoupledcontrol of a unified power conditioner based on current source topologyfor fast ACmains disturbance compensation,” inProc. Conf. Rec. ICIT,Mar. 2010, pp. 730–736.

Pedro E. Melín (S’10) was born in Chillán, Chile,in 1982. He received the Eng. degree in electronicengineering and the M.Sc degree in electrical engi-neering from the University of Concepción, Concep-ción, Chile, in 2006 and 2010, respectively, wherehe is currently pursuing the D.Sc degree in electricalengineering in multicell topologies based on currentsource converters.He is also working on the design and construction

of an electrical vehicle for solar challenges.

José R. Espinoza (S’92–M’97) received the Eng. de-gree in electronic engineering and theM.Sc. degree inelectrical engineering from the Universidad de Con-cepcion, Concepcion, Chile, in 1989 and 1992, re-spectively, and the Ph.D. degree in electrical engi-neering from Concordia University, Montreal, QC,Canada, in 1997.Since 2006, he has been a Professor in the De-

partment of Electrical Engineering, Universidad deConcepcion, where he is engaged in teaching and re-search in the areas of automatic control and power

electronics. He has authored and coauthored more than 100 refereed journaland conference papers and contributed to one chapter in the Power ElectronicsHandbook (Academic Press, 2011). Prof. Espinoza is currently an Associate Ed-itor of the IEEE TRANSACTIONS ON POWER ELECTRONICS.

Luis A. Morán (F’05) was born in Concepción,Chile. He received the degree in electrical en-gineering from the University of Concepción,Concepción, in 1982, and the Ph.D. degree inelectrical engineering from Concordia University,Montreal, QC, Canada, in 1990.Since 1990, he has been with the Electrical

Engineering Department, University of Concepción,where he is a Professor. He has written and publishedmore than 50 papers on active power filters andstatic var compensators in IEEE TRANSACTIONS.

From 1997 to 2001, he was Associate Editor of the IEEE TRANSACTION ON

POWER ELECTRONICS. He has extensive consulting experience in the miningindustry, especially in the application of medium-voltage ac drives, largepower cycloconverter drives for SAG mills, and power-quality issues. Hismain areas of interest are ac drives, power quality, active power filters, flexibleac transmission systems, and power protection systems.Prof. Morán is the principal author of the paper that received the IEEE Out-

standing Paper Award from the Industrial Electronics Society for the best paperpublished in the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS during1995, and was the coauthor of the paper that was awarded by the IAS StaticPower Converter Committee in 2002. In 1998, he received the City of Concep-ción Medal of Honor for achievement in applied research.

José R. Rodriguez (M’81–SM’94–F’10) receivedthe Engineer degree in electrical engineering fromthe Universidad Federico Santa Maria (UTFSM),Valparaiso, Chile, in 1977 and the Dr.-Ing. degreein electrical engineering from the University ofErlangen, Erlangen, Germany, in 1985.He has been with the Department of Electronics

Engineering, University Federico Santa Maria,since 1977, where he is currently Full Professor andRector. He has coauthored more than 300 journaland conference papers. He is Associate Editor of

the IEEE TRANSACTIONS ON POWER ELECTRONICS and IEEE TRANSACTIONSON INDUSTRIAL ELECTRONICS since 2002. His main research interests includemultilevel inverters, new converter topologies, control of power converters,and adjustable-speed drives.Dr. Rodríguez is a member of the Chilean Academy of Engineering. He re-

ceived the Best Paper Award from the IEEE TRANSACTIONS ON INDUSTRIALELECTRONICS in 2007, the Best Paper Award from the IEEE Industrial Elec-tronics Magazine in 2008, and Best Paper Award from the IEEE TRANSACTIONSON POWER ELECTRONICS in 2010.

Victor M. Cárdenas (M’94) received the Eng. de-gree in electronic engineering from the University ofSan Luis Potosí, San Luis Potosi, México, in 1992,and the M.Sc. and Ph.D. degrees in power elec-tronics from the National Center for Research andTechnological Development, Cuernavaca, Morelos.D.R. México, in 1994 and 1999, respectively.Since 2000, he has been with the Engineering De-

partment, University of San Luis Potosí, where heis currently Head of the Division for Research andPostgraduate Studies of the Engineering Department.

His main areas of interests are power quality, active power filters, and ac/acconverters.Dr. Cárdenas is a member of the IEEE Power Electronics Society, the IEEE

Industry Electronics Society, the IEEE Power Engineering Society, and theIEEE Industrial Electronics Society.

Carlos R. Baier (S’08–M’11) was born in Temuco,Chile, in 1979. He received the B.S.,M.Sc., andD.Sc.degrees in electrical engineering from the Universityof Concepcion, Concepcion, Chile, in 2004, 2006,and 2010, respectively.Since 2009, he has been a Professor in the Depart-

ment of Industrial Technologies, University of Talca,Talca, Chile, where he is teaching in the areas of au-tomatic control and power electronics. His researchinterests include improved control techniques formulticell converters, new multilevel topologies, and

high-energy-efficient improvements for medium-voltage converter topologies.

Javier A. Muñoz (S’08–M’12) was born in Concep-ción, Chile, in 1983. He received the B.S. (Hons.),M.Sc., and D.Sc. degrees in electrical engineeringfrom the University of Concepcion, Concepcion,Chile, in 2007, 2009, and 2012, respectively.Since 2011, he has been with the Department of

Industrial Technologies, University of Talca, Curico,Chile, where he is currently teaching dynamic sys-tems and robotics. His research interests include dig-ital control of modular multilevel converters to im-prove power quality.