1

A X/X Spread-Spectrum Transponder for Secure Communication

L. Simone, F. De Tiberis, F. Barletta, D. Gelfusa, S. Cocchi, F. Argentieri, R. Viola, I. Martinazzo, M. Delfino, P. Panella, F. Felici, R. Novello, M. C. Comparini

Alcatel Alenia Space – Italy Via Saccomuro 24 – 00131 Rome (Italy)

lorenzo.simone@aleniaspazio.it Abstract— Aim of this paper is to provide an overview of Alcatel Alenia Space – Italy (AAS-I) Spread-Spectrum Transponder platform placing emphasis on its advanced features for secure Telemetry, Tracking & Command (TT&C) applications.

TABLE OF CONTENTS

1. INTRODUCTION......................................................1 2. SST MAIN FEATURES............................................2 3. SST PLATFORM ARCHITECTURE..........................3 4. DIGITAL SIGNAL PROCESSING..............................5 4. KEY PERFORMANCE..............................................7 5. FURTHER DEVELOPMENTS ...................................7 REFERENCES .............................................................8

1. INTRODUCTION

AAS-I state-of-art for on-board secure TT&C equipment is represented by the X/X Direct-Sequence Spread-Spectrum Transponder (X/X SST, see Figure 1 and 2) which has been designed and developed in the frame of Koreasat 5 program [1]. The SST has the function to receive telecommands sent from the ground control station, to allow ranging function , to transmit the telemetry data of the satellite to the control ground station and to transfer the data of the Broadcasting Message (BM) to the SHF Beacon transmitter for down-link broadcasting. All these functions are implemented exploiting the technique of spectrum spreading through the Direct-Sequence quadrature modulation of the up-link and down-link carriers with a binary pseudorandom sequence. The spreading code frequency of a few Mchip/s and the data rates of the order of a few kbit/s leads to high processing gain thus allowing cope with very strong in-band jammer.

The SST design is based on a combination of advanced signal processing algorithms and modern technological implementation. The SST core based on a digital architecture leads to the following advantages with respect to a fully analogue solution:

• Receiver automatic re-configuration (for signal tracking loop bandwidths) according to the received signal input power;

• Easy implementation of narrow loop bandwidths;

• Inclusion of data demodulation capability;

• Data rate flexibility with easy matched filtering implementation;

• Interface optimization based on the extensive use of command and telemetry housekeeping in digital format (i.e. MLC and DS16, respectively);

• Design flexibility with transponder tuning based on programmable constants;

• Digital modulation capabilities.

Input Filter

DC/DC Converter

Digital Module

Receiver Analogue Module

Transmitter Analogue Module Figure 1 – X/X SST: mechanical design

Figure 2 – X/X SST: set-up for vibration test (FM model)

2

2. SST MAIN FEATURES

The following tables summarize the SST features and performance.

SST Platform: General Features Mass 3.6 kg Power Consumption 25 W (for +12 dBm output power in X-band) Power Bus Interface User defined Telemetry and Telecommand Interface User defined (1553 is also supported).

Table 1 – SST Platform: general features

SST Platform: Receiver Side Capabilities General Nominal up-link carrier frequency Fr S/C/X/Ku/Ka Modulation format UQPSK Up-link I/Q Power Ratio Selectable in the range from +10 dB to –10 dB Receiver noise figure < 2.5 dB In-Phase / Quadrature Channel PN chip rates The chip rate is programmable up to 3.5 Mchip/s. PN code length (chips) Programmable by remote command PN code family User Defined (non-linear code are supported) Data format NRZ Data rate Selectable by MLC in the range: 7.8125 ÷ 128000 bps Receiver Performance Receiver noise figure < 2 dB Maximum Doppler shift ±1500 Hz Signal acquisition threshold ≤ 34 dBHz @ maximum Doppler shift Signal acquisition time < 10 sec @ 2.5 Mchip/s Signal tracking threshold < 32 dBHz Maximum Doppler rate 300 Hz/s @ tracking threshold Implementation loss < 1 dB both for I- and Q-channel

Table 2 – SST Platform: receiver side features

SST Platform: Transmitter Side Capabilities General Nominal down-link carrier frequency S/C/X/Ku/Ka Modulation format UQPSK Down-link I/Q Power Ratio Programmable with 0.1 dB step Transmitted Power The following figures are supported:

• S-band: up to 5 W • X-band: up to 4 W • K-band: up to 1 W

Integrated Phase Noise (for X-band) ≤1.2 deg rms in the range from 10 Hz to 2.5 MHz In-Phase / Quadrature Channel PN chip rates The chip rate is programmable up to 3.5 Mchip/s. PN code length (chips) Programmable by MLC PN code family User Defined (non-linear code are supported) TLM Data format NRZ

Table 3 – SST Platform: transmitter side features

3

The spread-spectrum transponder platform developed by AAS-I has advanced features with makes it a step forward with respect to similar equipment available on the market as summarized hereafter.

Full support of the ESA and NASA spreading code family with on-board selection based on memory load command.

Support of non-linear spreading code providing robust anti-jamming performance— The non-linear code are user-defined and implemented in a dedicated space-qualified rad-hard FPGA to be inserted in the SST digital section as an add-on.

Up-link QPSK demodulation capabilities—The up-link Q-channel can be used simultaneously with the Telecommand (usually modulated on the up-link I-channel) thus providing an additional communication channel to be used for broadcasting services.

Up-link I:Q power ratio flexibility—The up-link I:Q power ratio can be varied in the range from 10 dB to –3 dB allowing the ground-station to optimize the command and ranging performance according to the system level requirement and operation scenarios.

Command data rate flexibility—Memory Load Command (MLC) can be used to select the actual data rate according to the mission profile and the intrusion scenario. A spread-spectrum receiver with flexible bit rate is suited to cope with a hostile environment. In particular, in presence of strong jammer, the bit rate can be reduced allowing a larger receiver integration time and hence a higher symbol energy. Such a flexible mode of operation is very attractive in secure communications. In addition, a significant advantage of this approach is an increased reliability since any unexpected system losses result in a reduced rate rather than in total disabling.

Full programmability of the up- and down-link frequencies with a frequency resolution of a few Hz—This special feature directly derives from the frequency plan based on the Fractional-N synthesis technique.

Special DSP design for anti-jamming—The sequential detection for code detection is optimized by means an adaptive thresholding scheme based on jammer power estimation. This approach allows to successfully acquiring the up-link signal even in presence of strong jammer interference.

Down-link I:Q power ratio flexibility—The down-link I:Q power ratio can be varied in the range from -6 dB to +6 dB with step 0.2 dB.

The large flexibility supported by the SST in terms of PN code family and PN code length, can be exploited by MLC

allowing for a complete in-orbit spread-spectrum receiver reconfiguration.

3. SST PLATFORM ARCHITECTURE

The X/X SST top-level block diagram is reported in Figure 3.

Receiver Analogue Section

The SST receives the up-link signal from the antenna subsystem. The Input Filter provides a wide-band filtering of the received signal thus minimizing the effect of the adjacent interference signals.

The Front-End perform low-noise amplification (noise figure < 2.5 dB) and image filtering. The Front-End output is mixed with the local oscillator for frequency conversion down to the receiver intermediate frequency (IF) equal to 13F0 (i.e. 130 MHz), being 4F0=40 MHz the reference frequency provided by the internal oscillator (OCXO or TCXO) or by the external Ultra Stable Oscillator (USO). Dedicated commands allow to select the internal or the external reference.

The Fractional-N synthesis technique is used to generate the proper LO frequency (FLO) starting from the reference frequency at 4F0. The Fractional-N synthesizer is controlled through a serial interface by the digital section. With this approach it is possible for the in-flight selection of the proper LO for the desired up-link channel.

The IF Section performs the signal filtering and amplification in order to provide the proper level to the ADC input. A wide-band AGC is employed to keep the signal-plus-noise power constant at the ADC input in order to minimize the noise which arises from the analogue-to-digital conversion. The AGC loop bandwidth has been dimensioned taking into account the system requirement on pulse jamming. The carrier frequency at the ADC input is 13F0+Fd, being Fd the offset frequency due to the Doppler shift and oscillators instabilities while the ADC is clocked at 4F0. This particular sampling process intrinsically produces the spectrum shifting at lower frequency, thus eliminating the need for a further frequency translation before the analogue-to-digital conversion. With this approach a consistent reduction of the equipment complexity and power consumption is achieved along with an improvement in terms of design reliability and robustness.

The IF bandwidth is fixed by means a customized SAW device ensuring excellent out-of-band rejection and anti-aliasing filtering.

4

Digital Module

TM streams

Receiver Analogue Module

FRX

ADC

µPRAM

PROM

DAC

DC/DC Converter Module

SST ASIC

FRX @ X-BandFTX @ X-Band, 12 dBm

F0=10 MHzFIF = 13F0+Fd

Rx Section

Tx Section

F0

FTX

RF Input Filter

Amplifier&

detectorSAW

PLLSynthesizer

ATTATT

BPF Low-PassFilter

SAWFilterSAWFilter

Buffer Card

Transmitter Analogue Module

4F0

Demodulated I&Q channels

ATT

AGC

F0

PLLSynthesizer

PLLSynthesizer

FL0

FL0,2 FL0,1

Figure 3 – X/X SST: top-level block diagram

Digital Section

The SST digital section is reported in the Figure 4 that shows the SST ASIC, the Microprocessor, the ADC, the DAC and the data memories.

The converted samples are managed by the SST ASIC Rx section performing the following main functions:

• Down-conversion of IF samples to Baseband In-Phase and Quadrature signals;

• Receive and track a spread-spectrum forward link signal;

• Provide BM and TC demodulated signal.

The SST ASIC Tx section includes the following signal processing blocks:

• Baseband filtering to perform data shaping

• Transmitter code NCO and PN code generators

• Direct Digital Frequency Synthesis section

The carrier modulation section (complex Quadrature modulator/phase modulator) modulates the Baseband data on a carrier.

The proposed SST ASIC Tx section architecture ensures wide flexibility in terms of data rate, shaping filtering and spreading codes. In particular, the SST ASIC Tx section provides the required modulation functions supporting a large set of modulation formats. The SST ASIC Tx section output is fed into the DAC for the digital-to-analogue conversion and then low-pass filtered in order to eliminate the replicas of the wanted signal. Two frequency conversions are used to translate the signal up to the down-link frequency.

A Microprocessor is devoted to digital section management and data handling functions. The chosen hardware/software partitioning allows a great flexibility in terms of functions, algorithms and design parameters: the high-rate signal processing functions and the synchronization algorithms are implemented in the SST ASIC, while the receiver management is implemented in the software domain.

5

SST ASIC

ADC

DACMicroprocessor

Memories

Figure 4 – SST digital section Transmitter Analogue Section

The transmitter analogue section is based on a double up-conversion scheme. The baseband modulated signal at the DAC output is converted to the UHF band and filtered by a SAW device. A second frequency conversion is used to translate the signal in the X-Band. After the second conversion, a mechanical band-pass filter is used to reject the image bandwidth at the mixer output and the local oscillator leakage. The transmitter output power is equal to 12 dBm with a stability versus temperature and aging better than ±0.5 dB.

4. DIGITAL SIGNAL PROCESSING

The SST signal processing core is implemented in a single-chip ASIC (the SST ASIC) carrying out both receiving and transmitting functions as detailed in what follows.

SST ASIC: Rx Section

The signal demodulation approach is based on a bank of I-Q demodulators running in parallel as depicted in the block diagram of Figure 5.

The incoming samples are down-converted to baseband by mixing with the in-phase and quadrature references at frequency 4F0. Being the digital demodulating frequency equal to ¼ of the sampling rate, the reference signals take on values {0,1,0,-1} and the mixing functions do not require multiplication. The digital mixing results in in-phase and quadrature baseband signals. The Phase Rotator rotates the baseband complex signal according to the phase estimated by the carrier tracking loop.

The Phase Rotator outputs are de-spread properly controlling the PN correlators. The PN code clock synthesis for these coders is implemented using numerically controlled oscillators under the control of the Microprocessor. The Microprocessor controls which code and which code phase is applied to each of the correlator branches as the receiver moves through its sequential acquisition states. These circuits also provide the capability to search the up-link code phases by moving the code outputs in half chip increments under control of the Microprocessor.

The code acquisition is carried out with parallel processing. Once the code phase has been acquired, a non-coherent early-late loop is used to perform the code chip tracking. Two I-Q demodulators are employed, one for the code early and one for the code late. The loop error is obtained after absolute value detection. In order to acquire and track the chip rate, a 2nd order - II type loop is implemented. In this way, no steady-state error due to the Doppler shift and oscillator instabilities is present. A third I-Q demodulator is used to perform the BPSK-modulated carrier acquisition by means a Costas loop.

6

µPfromADC

Qc

Ic

Carrier

DemodulationCorrelators

A

B

H Dec

imat

or

Det

ecto

r

AGC

Mul

tiplie

ra

b

h

Carrier NCO

AGC WORD

Rx PNCodes Rx PN

Generators

Rx PN Code

NCO

BitSynch.

DataClockSquelch

TC

BitSynch.

DataClockSquelch

BM

De-spreadI-channel

De-spread Q-channel

SST ASIC: Rx Section

BitSynch.

BitSynch.

Figure 5 – SST ASIC: Rx section

PhaseRotator

x/sin(x)Filter

CarrierNCO

Output(to DAC)

DirectSequenceSpreader

Tx PN CodeNCO

PN CodeGenerator(for TLM)

Tx PN Code frequency

PN CodeGenerator(for RNG)

TelemetryData

(redounded)

CarrierFrequency

From Rx PN CodeNCO

I-Channel Code

Q-Channel Code

I-Channel (for TM)

Q-Channel(for Ranging)

SST ASIC: Tx Section

µP

Figure 6 – SST ASIC: Tx section

The carrier acquisition is speeded-up using aided acquisition algorithms based on the code loop error information. After lock declaration the tracking proceeds using the Costas phase detector. The carrier tracking loop is a 2nd order - II type Costas loop with hard-limited in-phase channel. Once the carrier has been acquired, the code tracking is accomplished by means a coherent loop.

The in-phase signal of the de-spread carrier is applied to a Data Transition Tracking Loop (DTTL) performing BM symbol synchronization and matched filtering and squelch functionality. The base-band DTTL input signal is passed through two parallel channels: the in-phase channel monitors the polarity of the actual transitions and the quadrature channel measures the timing error accumulating

over the estimated symbol transition. The quadrature channel output is delayed by one-half symbol period and then multiplied by the in-phase channel output. The multiplication results is the loop error signal, that is proportional to the estimate of the timing error. Subsequently, the loop error signal is filtered by the loop filter with the resulting output being used to control the timing generator.

Likewise, the quadrature component of the de-spread signal is applied to a dedicated DTTL performing TC symbol synchronization, matched filtering and squelch functionality.

7

SST ASIC: Tx Section

The SST ASIC Tx section (see Figure 6) has a large flexibility due to the DDS-based architecture. In particular, coherent and not-coherent down-link modes are supported. In addition, a mixed-mode is supported in order to ensure the continuity of the telemetry link even in case of on-board receiver tracking loss. This feature is particularly important fo secure communication system in which it is not tolerable to have any loss of telemetry data. The mixed-mode is based on the following items:

• The carrier frequency is derived from the on-board local oscillator.

• The chip rate on the I-channel (i.e. TM) is derived from the on-board local oscillator..

• The chip rate on the Q-channel (i.e. Ranging) is coherent with the up-link chip-rate.

Practically, in mixed-mode the down-link telemetry channel is not-coherent and, therefore, it is not affected by the SST receiver status. On the other hand, the ranging is supported at code level, properly synchronizing the down-link code on the Q-channel with the received one. Finally, the down-link carried frequency is directly derived from the on-board local oscillator.

4. KEY PERFORMANCE

This section summarizes the SST receiver performance in terms of acquisition and demodulation. For this purpose, the following equipment set-up is considered:

• Up-link signal:

1. UQPSK (I:Q power ratio equal to 10 dB) during acquisition

2. QPSK during tracking

• PN Chip Rate = 2.5 Mchip/s

• PN code length (I-channel) = 1023

• PN code length (Q-channel) = 261888

• Bit Rate = 1 kbit/s

The test results are reported in Figure 8 and 9 at next page, respectively for acquisition and bit error rate (BER), in presence of CW jammer.

It turns out that the overall acquisition time is less than 13 seconds for jammer-over-signal power (J/S) up to 20 dB.

Concerning the BER, the measured implementation loss with respect to the theoretical curve is less than 1 dB.

5. FURTHER DEVELOPMENTS

The X/X SST design is characterized by a very high flexibility. In fact, it is possible to replace the X-Band front-end with a S/C/X/Ku or Ka-Band front-end, leaving almost unchanged the functions implemented in the digital signal processing core. Likewise, the down-link transmitter operating in X-Band can be replaced with one working at different frequency. This versatility is the key features of AAS-I spread-spectrum transponder platform.

As an example, the novel X/Ka SST (see Figure 7) for Sicral 1b military satellite under development by AAS-I, has been directly derived from the X/X SST by:

• Replacing the X-Band transmitter with the Ka-Band transmitter;

• Inserting, in the digital section, the custom FPGA (so-called SST FPGA) for:

1. the generation of the non-linear PN codes to be used in place of those built-in the SST ASIC;

2. implementation of the Viterbi decoder for TC convolutional decoding.

Input Filter

Digital Module

DC/DC Conv. Module

Rx Analogue. Module

Tx Analogue. Module Ka-Band Hybrid

Input Filter

Digital Module

DC/DC Conv. Module

Rx Analogue. Module

Tx Analogue. Module Ka-Band Hybrid

Figure 7 – X/Ka SST for Sicral 1b: mechanical sketch

8

J/S=17 dB, ∆f=±1.5 kHz

I-Code Acq._

Carrier Acq.__

Q-Code Acq.

J/S=20 dB, ∆f=0 kHz

Figure 8 – SST acquisition performance in presence of CW jammer (∆f is the frequency offset between the up-link frequency and the receiver rest frequency)

Bit Rate = 1000 bps, Chip Rate = 2.5 Mchip/s, I:Q=0 dB

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

19 20 21 22 23

J/S (dB)

BER

BER (test)

BER (theory)

φφπ

π

dRR

QJP

b

cb ⎥

⎥

⎦

⎤

⎢⎢

⎣

⎡⋅⎟⎟⎠

⎞⎜⎜⎝

⎛⋅⎟⎟

⎠

⎞⎜⎜⎝

⎛=

−

∫ cos1erfc

212

12

0

J/Q =J/S + 3 dB (i.e. I:Q = 0 dB)Rc = 2.5 Mchip/sRb = 1000 bps

Theoretical BER Evaluation

Figure 9 – SST demodulation performance in presence of CW jammer

REFERENCES

[1] “The Koreasat 5 Secure Communication System: Design, Development & Performance”, Koreasat 5 AAS-I Team., IEEE Aerospace Conference 2006.