2008 IEEE Nuclear Science Symposium Conference Record

A Fast Binary Front-End ASIC for the RICHDetector of the COMPASS Experiment at

CERNMichela Chiosso, Ozgur Cobanoglu, Giovanni Mazza, Member, IEEE, Daniele Panieri

and Angelo Rivetti, Member, IEEE

N11-4

Abstract-The paper describes a fast binary integrated circuit.The chip was developed to read-out the multi-anodephotomultiplier tubes which equip the RICH detector of theCOMPASS experiment at CERN. The ASIC incorporates eightidentical channels, each featuring a low-noise amplifier followedby a comparator and a LVDS driver. The amplifier has apeaking time of to ns and a gain programmable from 0.4 mV/fCto 4.8 mV/fC. Two to-bits Digital-to-Analogue Converters perchannel allow independent settings of the amplifier baseline andof the discriminator threshold. The circuit works with aminimum threshold of 3 fC and handles hit rates in excess of 5MHz per channel. Implemented in a 0.35 J1m CMOS process, thechip dissipates 200 mW from a 3.3 V power supply. After theprototyping phase, six 8-inch wafers have been produced and areunder test. The new front-end electronics will be installed in theexperiment before the 2009 data taking.

Index Terms-ASIC, photomultipliers, programmable gain,Ring Imaging Cherenkov.

I. INTRODUCTION

COMPASS (COmmon Muon Proton Apparatus forStructure and Spectroscopy) is a fixed-target experimentexploiting the CERN Super Proton Synchroton (SPS) to

study nucleon spin structure and hadron spectroscopy withhigh intensity muon and hadron beams [1]. One of the keycomponents of the apparatus is the Ring Imaging CherenkovDetector (RICH) [2], which provides particle identification inthe momentum range from 3 GeV/c to 55 GeV/c. Initiallyequipped by multi-wire proportional chambers (MWPCs) withCsI photocathodes, this detector has been upgraded replacing

Manuscript received November 14, 2008. The work was fully supported bythe Italian National Institute ofNuclear Physics (INFN).

Michela Chiosso, Giovanni Mazza and Angelo Rivetti (phone: +39 0116707380; fax: +39 011 6699579; email: rivetti@to.infu.it) are with theNational Institute of Nuclear Physics (INFN), Torino - Via Pietro Giuria 1,10125, Torino, Italy.

Ozgur Cobanolgu was with the Department of Experimental Physics,University of Torino and INFN, Via Pietro Giuria 1,10125 , Torino, Italy. Heis now with the European Laboratoty for Particle Physics (CERN) - CHI2II­Geneva - Switzerland.

Daniele Panzieri is with the University of Eastern Piedmont, Departmentof Advanced Science and Technology, via Bellini 15G, Alessandria - Italyand with INFN, Via Pietro Giuria I, 10125 , Torino, Italy

in the central region the MWPCs with multi-anodephotomultipliers tubes (MAPMTs). These are read-out by theMAD4 [3], a four channel preamplifier-discriminator ASICscoupled to the FI TDC chips [4]. In the meanwhile a customintegrated circuit optimized for the COMPASS environmenthas been developed. Major modifications with respect to theMAD4 include a front-end amplifier with variable gain and onchip digital-to-analog converters to set the comparatorthreshold on a per-channel basis. This make it possible tomitigate the gain spread of the photomultipliers pixel by pixel,whilst the tuning of the high-voltage bias would allow aregulation only every sixteen channels. In addition, themaximum hit rate that a single channel can handle has beenincreased to 5 MHz, in order to cope with the augmentedbackground expected in hadron runs. Called CMAD, the newchip is fully compliant with the existing read-out system,hence only the front-end cards need to be replaced. The ASICincorporates 8 identical channels and has been produced ina 0.35 Jlm CMOS process. The circuit is hosted in a compact14mm x 14mm LQFP 128 package. The architecture of theASIC and the relevant building blocks are discussed in SectionII, the test set-up in Section III and the chip performance inSection IV.

II. ASIC ARCHITECTURE

A. General overview

The chip contains eight identical channels. This modularitywas chosen since it is the best one from the point of view ofthe overall system integration .

Shown in Fig. 1, a single channel is formed by a chargesensitive amplifier followed by a second order semi-gaussianshaper, a comparator and an LVDS driver. Inside thecomparator, a one-shot circuit can be enabled to provide anoutput signal of fixed width. A two-stage baseline restorerimplements a low-frequency feed-back loop around theshapero The purpose of this loop is to guarantee DC insulationbetween the preamplifier and the shaper and to lock the DCvalue of the shaper output (in the following referred to as "thebaseline") to a reference voltage provided by a 10 bit Digitalto Analogue converter. The output of the shaper drives one ofthe of the two comparator inputs, the other one beingcontrolled by the 10 bit threshold DAC. Low-Dropout

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c. Baseline holder

With a power supply of 3.3 V the output dynamic range is2.8 V, while the total bias current of the OTA is 1 rnA, with400 J.1.A used in the output stage.

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1. A unity gain buffer with limited slew rate (indicated asSR in Fig. 1) to prevent baseline drifts due to the ACcoupling.

2. A transconductance stage with a load capacitor toimplement a GmlC filter that limits the bandwidth anddefines the low-frequency cut-off.

3. A NMOS transistor to provide the necessary current atthe input of the shapero

It must be observed that without the baseline holder theoutput voltage Vout,DC would be defined by the differencebetween the voltage VREF applied to the positive input of theOTA and the DC level at the preamplifier output, VPRE,

according to the following equation:

V out,DC = VREF (1 + RSh)-VPRE Rsh (2)Rc Rc

where Rsh and Rc are respectively the feed-back resistance ofthe shaper and the coupling resistance between thepreamplifier and the shapero Since the baseline holder isunipolar it can regulate the output voltage only if Vout,DCdefined in (2) is smaller than the desired baseline value, inwhich case the NMOS transistor sinks the extra currentnecessary to pull up the output node. A natural choice is to setVREF equal to the nominal DC voltage of the preamp. Eq 2allows then to calculate the interval in which the baselinevoltage can be regulated for a given mismatch between VREF

and VPRE. The worst case condition occurs for the high-gainmode, where the value of Rc is smaller. In practice, theMAPMT would determine a negative-going signal, so it is ofinterest to set the baseline as high as possible to maximize thedynamic range. For this reason a nominal value of 2.8 V was

Fig. 2. Normalized pulse response.

The baseline holder [6] is used to make an AC couplingbetween the shaper and the preamplifier and to lock the outputvoltage of the front-end to the reference value set by the DAC.The circuit can be partitioned in three blocks:

OutP~

] reMP ,LVDS' .

[- ---SA: . . . ""'"

,~DAC_TH IFig. 1. Schematic ofone channel

B. Preamplifier and shapero

At the input of the channel the current pulse of the MAPMTis converted to a voltage by a transimpedance amplifier builtaround a single-ended telescopic cascode stage. Thetransimpedance gain can be adjusted independently for eachchannel with a 3-bit control, that allows to choose separatelythe values of the feed-back resistance and the ones of the feed­back capacitance. The in-band gain ranges from from 21dl to4.8 Idl in steps of 0.4 Idl. The preamplifier is coupled to theshaper via a resistor with two selectable values. The gain ofthe full front-end can hence be set from 0.4 mV/fC to 1.2mV/tL in step of 0.1 mV/tL ("low-gain mode") or from 1.6mV/tL to 4.8 mV/fC in step of 0.4 mV/tL ("high-gain mode").

One of the leading motivations for the design of CMADwas the need to cope with event rates of a least 5 MHz withan efficiency better than 99% . To have an adequate safetymargin for all possible comers of the process, the circuit wasdesigned for a maximum event rate of 10 MHz per channel.This lead to the choice of a shaping time in the range 8-10 ns,in order to allow a return to the baseline within 100 ns. Theoverall transfer function of the circuit is well modeled with athird order relationship of the form:

KT(s) = --3 (1)

(1 +s 1")

Fig. 2 shows the simulated pulse response (dots) and thecurve obtained fitting the simulated points with eq. (1). Avalue for 't of 4.6 ns is obtained, which results in a nominalpeaking time of 9.2 ns. In order to minimize the recovery timein case of large signals it was chosen to extend as much aspossible the linear dynamic range of the front-end.Additionally, a fast shaping calls for an output stage with highslew rate even if a small capacitance load has to be driven. Forinstance a signal of 2.5 V and IOns peaking time describedby a CR-RC3 shaping function has a slew rate of 400 V/J.ls. Toachieve this figure a class A circuit requires a bias current of 2rnA already for a load capacitance of 0.5 pF. Therefore it waschosen to use as core amplifier for the shaper a class ABOperational Transconductance Amplifier (OTA) [5].

Regulators (LDO) are used to generate on chip the requiredreference voltages, therefore the only additional componentsneeded on the front-end card are capacitors for power supplydecoupling.

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E. Digital to Analogue Converters.

The digital to analogue converters are based on amultiplying (MDAC) topology. The schematic of the circuit isshown in Fig. 5. The current from a reference source is

bias

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in- /'

The comparator is based on a cascade of four low-gain andhigh bandwidth differential amplifiers with diode-connectedloads and clamping transistors to reduce the time necessary torecovery from large signals. The output stage of thecomparator generates full CMOS levels that drive the LVDSoutput port. A dedicated circuit allows to add a current­controlled hysteresis [7]. The circuit is designed to resolveminimum signal of 1 mV above threshold. The comparatorwas optimized for speed, therefore relatively small transistorswere used. An offset voltage of 30 mV peak-to-peak isexpected from the Monte Carlo simulations. One input of thecomparator is driven from the front-end amplifier, while theother one is connected to the threshold DAC. The baselineDAC is used for a fine tuning of the baseline value, in such away that all channels have the same effective threshold. Thefront-end contains differential pairs in the OTA, in the Gmstage and in the slew rate limited buffer and their offset willadd to the one of the comparator. In the worst case a channelto channel offset of 40 mV peak-to-peak must becompensated. However, as discussed in the previous section,this value can be easily accommodated by the baseline DAC,while the loss in dynamic range is negligible. Each differential

cell in the comparator is biased with 150 flA, for a total powerconsumption of 2.5 mW. A one shot circuit (not shown inFig. 4) can be enabled to stretch the width of the comparatoroutput pulse to a fix duration. The circuit is sensitive to theleading edge of the comparator output and can provide pulseswith a duration between 12 ns and 200 ns.

Fig. 4. Schematic of the comparator

of signals with 3 V amplitude, IOns peaking time and 10 MHzfrequency is applied to the circuit.

D. Comparator

The buffer works in a unity gain configuration and itintroduces only high-frequency poles which do not interferewith the stability of the baseline restorer loop, which has adominant pole detennined by the capacitor filtering the Gmstage. The slew-rate limitation is implemented by transistorM7 and capacitor CL. Transistor MIl is a low-impedancebuffer which insulates the slew rate limiting circuit. Thereason for this choice is the following. The output signal of theamplifier is applied to the gate of Ml. If the unity gain feed­back is taken connecting directly the source of M7 to the gateof M2, a significant charge can be injected on CL through thegate-source capacitance of M I and M2. Since the current inM7 is limited to 200 nA, the time to restore the voltagebetween two consecutive pulses may not be sufficient and thebaseline value would still have a rate dependent component.The simulation showed that with the adopted configuration abaseline drift of less than ImV is achieved when a pulse train

Fig. 3. Schematic of the slew rate limited buffer.

3.

chosen. It is however important to have enough flexibilityaround this point, in such a way that the baseline DAC can beused to compensate for the unavoidable offsets in theprocessing chain, leaving to the threshold DAC the maximumpossible headroom for signal selection. With Eq. 2 it is easy tocalculate that a difference between VREF and VPRE of 60 mVstill allows the regulation of the baseline down to 2.3 V. VPRE

is defined by the gate-source voltage of the input transistor ofthe charge sensitive preamplifier and it is expected to changeby less than 15 mV peak-to-peak on the same chip. Therefore,the value of VREF can simply fixed for all the channels by areplica bias circuit. This will guarantee a good safety marginfor the choice both of the baseline value and of its tuningrange. The problem of the matching between VREF and VPRE isgreatly relaxed in the low-gain mode, which will be thestandard operating mode in COMPASS.

From the point of view of the overall transfer function theGm/C filter implements an AC coupling and as such it issensitive to rate-dependent drifts. The well-know solution tothe problem [6] is to insert in the chain a slew rate-limitedelement that clips the fast signal before passing them to thefilter. Slow-frequency components that must be compensatefor are left unaffected. The adopted solution is shown in Fig.

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divided by a ladder employing a transistor-only R-2Rarchitecture [8]. The advantage of this option is that the size ofthe DAC grows linearly with the number of bits. A carefuloptimization is necessary in order to minimize the sensitivityof the circuit to the offset of the op-amp. The reference currentis generated by an internal circuit controlled by an externalvoltage. In this way, the value of the LSB can be adapted tothe application. In COMPASS both the baseline and thethreshold DAC will be used with a LSB of 0.5 mV/digit. Witha reference voltage for the op-amp of 2.4 V the baseline andthe threshold can be independently adjusted in the range 2.4 Vto 2.9 V. Each DAC occupies an area of 140~m x 600 ~m anddissipates 1 mW of power. The DAC as well as the amplifierparameter are programmed via a serial interface developed tobe compatible with the existing data acquisition system of the

insulate the front-end amplifier from the comparator. In thisway the output of the front-end can be probed with anoscilloscope and a test signal can be fed directly to thediscriminator. In addition, all the outputs of the thresholdDACs can be sent to external pins to allow an accuratecharacterization. Eight CMAD cards are connected to aservice board that contains the voltage regulators and providethe interface to the acquisition card, called DREISAM andbased on the FI TDC [4]. Therefore, eight chips can be testedin parallel. The characterization of the ASICs in done with theMAPMT connected. The standard test procedure requiresdetermination and equalization of the thresholds, noise andgain measurements and full verification of the functionality ofthe digital interface.

RepeatedBit Slice

Fig. 5. Schematic of the Digital to Analogue Converter.

experiment.

IV. TEST RESULTS.

Figure 7 shows as an example the measurement of thesignal output for two different channels with two differentgain settings. In the measurement an input signal of fixed

R14C14 R6C6

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200 300 400 soo ~(J.PO

Fig. 7. Amplitude measurement via threshold scan on two channels for twodifferent gain settings.

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amplitude is applied via the calibration lines and a thresholdscan is performed. The measurement is done both in the low­gain mode and in the high-gain mode with 1.2 mV/fC and 4.8mV/fC nominal values respectively. The experimental valuesfound are 1.15 mV/fC and 4.8 mV/fC, in good agreement withthe expected ones.

The linearity of the front-end was measured in detail withthe test channel by probing directly the output of the op-amp.The result is shown in Fig. 8. A maximum nonlinearity of 20/0up to 700 fC is observed. In this measurement the gain was setto 2.8 mV/fC and the baseline to 2.7 V. Therefore a signal of700 fc corresponds to an output signal of 2 V. Since theoutput has a negative polarity a minimum voltage of 0.7 V isreached. Below this limit the linearity progressivelydeteriorates due to the saturation of the output stage of the

Fig. 6. CMAD ASIC on the final front-end board.

the front-end card, as shown in Fig. 6.The connector for the photomultiplier is visible on the left.

The board contains only passive components for biasing anddecoupling. Two calibration lines, one for odd and one foreven channels, can be used to send test signals to the chip.One channel of the ASIC contains switches that allow to

III. TEST SET-UP.

The chip is housed in LPFQ 128 pin package and mounted on

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S38532521

700600500400300200100-0.02L-- ----'

3.5:;0.. 0.8S0"'0 0.6~

.~c; 0.4l=c:

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00.01

~0

~~

"'0

~ -0.01

peak-to-peak--5 digit

525

i 0.'I O.J

~ 545Th....hoId (dlalt)

Fig. 10. S-curve and its derivative. The threshold is expressed ad DAC codes.The LSB is 0.5 mV.

Input Charge [fC]

OTA. Figure 9 show an example of threshold dispersion andequalization. The plot has on the x axis the channel numberand on the y axis the measured threshold expressed in mV.

A peak to peak variation of 23 mV is observed in this case.Depending on the gain used this may be equivalent up to 50fL. The equalization is done by adjusting in each channel thevalue of the baseline DAC and after the equalization all thethresholds fall in the same bin. Therefore., the threshold can beequalized to the accuracy of one LSB. For the worst case ofthe smallest gain this corresponds to 1.2 fL peak-to-peak or1300 rms electrons.

Fig. 8. Linearity of the front-end amplifier.

The performance ofCMAD are summarized in Table 1.

REFERENCES

[1] P. Abbon et al., "The COMPASS Experiment at CERN", NuclearInstr. AndMethod~', vol. 577, issue 3, pp. 455-518, July 2007.

[2] P. Abbon et aI. , "Design and Status of COMPASS FAST-RICH",Nuclear Instr. And Methods, vol. 567, issue 1, pp. 113-117, Nov 2006.

[3] F. Gonella and M. Pegoraro, CERN-LHCC-2001-034, pp. 204-208[4] H. Fisher et aI., "Implementation of the dead-time free Fl TDC in the

COMPASS read-out", Nuclear Instr. And Method~', vol. 461, issues 1-3,pp. 506-510, April 2001.

[5] Johan H. Huijsing, "Operational Amplfiers: Theory and Design",Kluwer Academic Publishers, 2001.

Value

TABLE ICMAD PERFORMANCE SUMMARY

2650

2645 •~

~ 2640 •=-;.: 2635 • • •-=.ce 2630.cEo-

2625 & & & & & & ••2620

0 2 4 6 8

(lIannel number

Fig. 9. Threshold values before (squares) and after (triangles) equalization.

Finally Fig . 10 shows a typical S-curve measurement. Thegain in the measurement was 1 mVffL and the noise is foundto be 2.5 fL peak-to-peak., equivalent to an ENC of 2600electrons ros. This make it possible to work with a thresholdas low as 4 fL with a good safety margin. The rateperformance of the chip were tested using a LED to emulatethe physics signal (maximum rate 100 kHz) and a lamp with asystem of optical filters to emulate the background., reaching afrequency of 10 MHz. In these conditions an efficiency betterthan 99% is found.

Parameter

TechnologyNumber of channelsLow-gain rangeLow-gain resolutionHigh-gain rangeHigh-gain resolutionResidual thresholddispersion (worst case)Noise (worst case)Peaking timeRate per channelPower consumption

CMOS 0.35 ~m80.4 mV/f(' to 1.2 mV/f('0.2 mV/f('1.6 mitt:' to 4.8 mV/f('0.4 mV/f('1300 electrons nns

2600 electrons rms10 ns> 5 MHz.20 mW/channel

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[6] G. De Geronimo, P. O'Connor and 1. Grosholz, "A CMOS baselineholder (BLH) for readout ASICs, IEEE Trans. Nucl. Sei, voL47 (3),June 2000.

[7] F. Anghinolfi et aI., "NINO: a ultra fast and low-power front-endamplifier/discriminator ASIC designed for the multi-gap resistive platechambers", Nuclear Instr. AndMethods, vol. 533, issues 1-2, pp. 183­187, Nov. 2004.

[8] K. Bult and C.1.G.M Geelen, "An Inherently Linear and CompactMOST-only Current Division Technique", IEEE Journal Solid Stateeire., vol. 27, No. 12, 1992.

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