Workshop for AMSD Virtuoso Use Model

Cadence Confidential

Cadence Design Systems, Inc.

Revision 1.3

AMS Product Engineering

April, 2009

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Cadence Confidential 2

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Contents Contents ........................................................................................................................................................ 3 Overview ....................................................................................................................................................... 5

Workshop Database Location.................................................................................................................... 7 Chapter 1 Introduction of AMSD Virtuoso Use Model ............................................................................. 9

Benefits of OSS-based AMS Netlister........................................................................................................ 9 Things to Know When Using the OSS-based AMS Netlister ..................................................................... 9 Updating Text Views That Do Not Have Design Database Information................................................... 11 The irun Run Mode .................................................................................................................................. 11

Chapter 2 Building an AMS case in ADE .............................................................................................. 12 The AMS Designer Simulator................................................................................................................... 12 Mixed-signal Design with AMSD in ADE.................................................................................................. 12

Set up the tools and start dfII............................................................................................................. 13 Importing the Verilog Module into dfII ................................................................................................ 13 Completing the mixed-signal design in Schematic Editor.................................................................. 17 Configuring the design in HED .......................................................................................................... 20 Set Up ADE Options and Customize the Connect Rule .................................................................... 25 Simulating it using AMSD in ADE...................................................................................................... 32

Chapter 3 Migrating from SpectreVerilog to AMSD............................................................................... 35 Background .............................................................................................................................................. 35 Simulating in UltraSimVerilog................................................................................................................... 36 Simulating in SpectreVerilog .................................................................................................................... 42 Simulating in AMS Designer with the Same Configuration ...................................................................... 43

An Introduction to Connect Rules and Disciplines in AMS Designer................................................. 43 Optional ............................................................................................................................................. 51

Summary.................................................................................................................................................. 52 Chapter 4 Migrating from CB to OSS AMS Netlister ............................................................................. 53

Introduction .............................................................................................................................................. 53 Purpose and Scope.................................................................................................................................. 53 Case Information...................................................................................................................................... 53 Running the Tutorial................................................................................................................................. 54 Netlisting and Simulating using CBN with ncvlog, ncelab, ncsim............................................................. 54 Netlisting and Simulating using OSSN with irun....................................................................................... 56

1. Template for creating ‘config’ view ................................................................................................ 56 2. Create the Shadow DB for Text Views to run OSSN..................................................................... 57 3. Multiple Instances of the Same Cell Name with Different Views................................................... 59 4. Running Simulation........................................................................................................................ 61

Summary.................................................................................................................................................. 62 Chapter 5 Multiple Supply based on Inherited Connection ................................................................... 63 Chapter 6 Multiple Supply based on Digital Discipline .......................................................................... 72

Introductions............................................................................................................................................. 72 Running the Tutorial................................................................................................................................. 72

Discipline-based Connect Rule Preparations .................................................................................... 72 Scope-discipline definition via Schematic under AMS-ADE context ................................................. 79 AMS simulation in ADE...................................................................................................................... 84

Chapter 7 Spectre-Turbo Integration in AMSSpectre............................................................................ 90 Introduction .............................................................................................................................................. 90 Objectives ................................................................................................................................................ 90 Case information...................................................................................................................................... 90 Running the Tutorial................................................................................................................................. 91 Result comparison and analyses ............................................................................................................. 96

Summary................................................................................................................................................ 100 Chapter 8 Co-Simulation with AMS Designer and MATLAB®/SIMULINK .......................................... 101

Introduction ............................................................................................................................................ 101 Set Up the Co-Simulation....................................................................................................................... 102

Modifying the SIMULINK model....................................................................................................... 103 Modifying the Virtuoso Schematic ................................................................................................... 108 Section 1: Run Co-Simulation in ADE with the Fixed Cell Coupler ................................................. 112 Section 2: Run Co-Simulation in ADE with simulinkCoupler ........................................................... 116 Section 3: Run Co-Simulation in MATLAB/Simulink........................................................................ 117

Summary................................................................................................................................................ 120 Learn More about the Co-Simulation Interface ...................................................................................... 121

Frame-Based and Unframed Signals .............................................................................................. 121 Event Based and Fixed Rate Simulation ......................................................................................... 122 Using the Coupler Module in Loops................................................................................................. 123

Troubleshooting ..................................................................................................................................... 124 Chapter 9 Using runams Command.................................................................................................... 127

Introduction ............................................................................................................................................ 127 runams Command Syntax ..................................................................................................................... 127 Case Information.................................................................................................................................... 127 Running the Tutorial............................................................................................................................... 128

Setting up the Tutorial...................................................................................................................... 128 Using the runams Command.......................................................................................................... 128 runams advanced applications ........................................................................................................ 133 Example 5: Corner analysis using runams ...................................................................................... 135 Example 6: Verification using runams ............................................................................................. 136

Summary................................................................................................................................................ 138 runams Limitations................................................................................................................................. 138

Chapter 10 Designing with Text-On-Top and Using the Scope Navigator with AMS Designer ............ 140 Test Case Information............................................................................................................................ 140 Setting up the Tutorial ............................................................................................................................ 140 Creating a Text-on-Top Design.............................................................................................................. 140 Creating a config View ........................................................................................................................... 144 Setting Up the Design in ADE ................................................................................................................ 147 Verifying Netlister and Run Options, Connect Rules and Model File ..................................................... 150 Using the Scope Navigator to Select Output Signals............................................................................. 152 Selecting Nets on a Schematic .............................................................................................................. 154 Running the Tutorial............................................................................................................................... 155 Summary................................................................................................................................................ 157

Overview

Virtuoso AMS Designer is noted for its advanced philosophy and concept. It is a single executable Language-based Mixed-signal simulation solution for the design and verification of the largest and most complex Mixed-signal SoCs and multi-chip designs. It is integrated and fully compatible with both the Virtuoso custom design and Incisive functional verification platform. Accordingly, AMSD supports two major use models:

• AMSD Virtuoso Use Model: ADE + OSS + irun • AMSD Incisive Use Model: irun + AMS Control File

See the following Fig 1: AMSD Use Models.

Fig 1: AMSD Use Models AMSD Virtuoso Use Model means running AMSD simulator within Virtuoso platform, which is 5x library (schematic) based, while AMSD Incisive Use Model takes the textual netlist only (including verilog/AMS modules and HPSICE/Spectre format), which is totally out of Virtuoso and launched from command-line. AMSD Virtuoso Use Model is more targeting for analog-centric design while AMSD Incisive Use Model is more for digital-centric design verification. To run AMSD in Virtuoso Environment, you need to install both IUS and IC releases, while, to run AMSD Incisive Use Model, you need to install IUS only.

AMSD Use Models

AMSD in ADE (OSS+irun)

AMSD Virtuo so Use Model (GUI Based)

IUS & IC

AMSD Incisive Use Model (Text Based)

irun + AMS Control File

IUS only

AMS Designer (with UltraSim, Spectre or

APS as analog solver)

The AMSD simulator in Virtuoso Environment is supported in both the Analog Design Environment (ADE) and the Cadence® hierarchy editor (HED). For those who use Spectre, or UltraSim, or SpectreVerilog, or UltraSimVerilog in ADE, the ADE graphical interface makes it easy to migrate to the AMS simulator. So to the new AMSD users including spectreVerilog or UltraSimVerilog users, the combination of ADE/OSS/irun is recommended. This workshop will focus on the AMSD Virtuoso Use Model. All the cases in this workshop use ADE, OSS netlister and irun simulator. If you are interested in the AMSD Incisive Use Model, please ask for ams_pe alias for the access to the workshop of AMSD Incisive Use Model, or get it from $IUS_INST_DIR/tools/amsd/samples/aium. In this workshop, the following topics will be addressed:

• Introduction of AMSD Virtuoso Use Model Briefly introduces AMS OSS netlister (OSSN) and irun use model in ADE: The benefits using OSSN, Things you need to know when you use OSS. The way irun works in ADE. • Building an AMS case in ADE Assuming you have some existing analog schematic database in Cadence Schematic Editor (Composer), and some digital (verilog in this example) modules in text, and you want to build a AMS case to run full-chip AMS simulation. This chapter will walk you through the whole process from building an AMS case in ADE and setup, to finishing the simulation. • Migrating from SpectreVerilog to AMSD This is to target the SpectreVerilog or UltraSimVerilog users. This chapter guides you migrate from the current solution to AMS Designer in ADE, a much more robust AMS solution. • Migrating from CB to OSS in AMSD Cadence has many existing AMSD users who are using Cell-based netlister. Since OSS netlister has some unique values, they might want to move OSSN as well. This is a guideline tutorial. • Multiple Supply based on Inherited Connection In this technique, the use of inherited connection attributes and CDF “netSet” properties added to schematic allow you to create special global signals and override their names selectively in a design hierarchy, so that InhConn Connect Modules can be automatically inserted with the appropriate power values. • Multiple Supply based on Digital Discipline Besides Inherited Connection, another way is using different digital discipline for multiple power supply. In this approach, scope-based discipline option is used for the tool to automatically insert the Connect Modules with expected power value. • Spectre-Turbo integration in AMSDE Spectre-Turbo has significantly improved the simulation speed and it also has well received by many users. Now this technology becomes available in AMSSpectre from version of IUS8.1 and IC612 ISR14.

• Matlab/simulink Co-simulation Co-simulation using AMS Designer and MATLAB/Simulink combines the best of system level simulation with analog and RF simulation. � Using the runams Command

The runams command allows you to run AMS Designer from the command line or from a script using the same default values used by the AMS ADE with the OSS/irun flow. This command includes options for netlisting the design and running simulations with irun.

Each topic is accompanied with a tutorial case. The cases and instructions for “Multiple Supply based on Inherited Connection”, “Multiple Supply based on Digital Discipline” and “Matlab/simulink Co-simulation” are built based on the original ones from AMS CoreComp team. Many thanks to the team! The tool versions this workshop requires:

• AMSD Environment: IC612ISR with version of 14 and later • AMSD Simulator: IUS611 and later in general, BUT IUS8.1 Base and later is required for

AMSSpectre-Turbo. Acronyms AMSD: AMS Designer simulator AMSS: AMSD with Spectre as the analog solver AMSU: AMSD with UltraSim as the analog solver AIUM: AMSD Incisive Use Model AVUM: AMSD Virtuoso Use Model CBN: AMS Cell Based Netlister OSSN: AMS Open Simulation System Netlister ACF: Analog Control File, analog control statements for analog solvers OOMR: Out Of Module Reference, references cross the modules CM: Connect Module, the converter between Analog and Digital signals Crule : Connect Rule, the file specifying which CM and what parameter values used in the design IE: Interface Element, spectreVerilog term, same thing as Connect Module BDR: Block-based Discipline Resolution, used for the design with multiple power supplies SFE: Simulation Front End analog parser

Workshop Database Location

All tutorials mentioned in this workshop are located in <Virtuoso installation directory>/tools/dfII/sample s/tutorials/AMS/ Please copy the corresponding folders in the above directory to your local directoty. Here’s a table listing the tutorial name of every chapter. Chapter Tutorial Name 1. Introduction to AMSD Virtuoso Use Model 2. Building an AMS case in ADE AMSDInADE 3. Migrating from SpectreVerilog to AMSD MigrateFromVerimixToAMSDinADE 4. Migrating from Cell-based to OSS-based netlister for AMSD MigrateFromCBNToOSSN 5. Multiple Supply based on Inherited Connections MultiPwerInhConn 6. Multiple Supply based on Digital Discipline MultiPowerDis

7. Spectre-Turbo integration in AMSD AMSSpectreTurbo 8. MATLAB/Simulink Co-simulation MATLABCosimulation 9. Using runams Command runams

Chapter 1 Introduction of AMSD Virtuoso Use Model

Starting from the IC 5.1.41 USR4 release, a new AMS netlister is available which is OSS-based, like the Spectre, Ultrasim and other netlisters. This netlister uses the Spectre CDF that is used by the netlister for the Spectre, Ultrasim, SpectreVerilog, and UltrasimVerilog simulators. Therefore, converting the Spectre PDKs to AMS is not necessary to use the AMS simulator. This netlister is hierarchical and netlists the entire hierarchy, as opposed to netlisting each cell independently. However, as this netlister is incremental, it will not re-netlist the parts of your design that have not changed.

Benefits of OSS-based AMS Netlister

Some of the important benefits of OSS-based AMS netlister are:

• It uses Spectre CDFs and spectre netlist procedures to netlist the Spectre primitives. You do not need to add ams siminfo, create ams netlist procedures or convert your PDKs. The netlister also works with Verilog views similar to SpectreVerilog and Verilog netlister.

• It does not write into the 5X library. Therefore, you do not require writable master libraries, explicit tmps, or implicit tmps.

• Debugging and the ability to run standalone simulation is expected to be simplified as the design is primarily in one netlist file, similar to Spectre, rather than spread within the 5X library or explicit or implicit library. Additionally, any netlister messages/errors will be consistent with other SpectreVerilog netlister messages/errors. For example, if you understand the messages from the Spectre netlister, you will understand the messages from this netlister also, as both are OSS-based netlisters.

• Since the OSS-based netlister does not use the 5X structure, compilation is expected to be faster.

• It works with the new irun one step method. This use model is similar to the Verilog-XL use model and it enables functionality such as -y/-v inclusions, similar to Verilog-XL. This approach is more consistent with the digital use model allowing design information to be shared easily.

• The OSS-based netlister supports VHDL modules in your design.

Note the following:

o VHDL modules are supported only at the leaf level.

o Instance binding is not supported for VHDL modules. For more information about instance binding, see the Cadence Hierarchy Editor User Guide.

Things to Know When Using the OSS-based AMS Netlist er

This section describes a few things to know when using the OSS-based AMS netlister.

• Text views must be imported into a DFII database format library, or contain Virtuoso database files

• View list and stop list of a configuration

• Instance level view binding in Hierarchy Editor and the 'uselib compiler directive

• Netlisting as analog or digital when an instance is bound to the symbol view in your configuration

• Netlisting of inherited connections

Text views must be imported into a DFII database fo rmat library, or contain Virtuoso database files

To netlist text views, the OSS-based AMS netlister requires the text views to either be imported into a DFII database format library, or contain the Virtuoso database (.cdb) files. You can use any of the following methods to do this.

Note: You can use Verilog or VHDL text files that are not netlisted by specifying them in the Library files or Library directories fields in the irun Options form.

• Import Verilog text files using the Verilog In utility.

For more information about using Verilog In, see the Verilog In for Virtuoso Design Environment User Guide and Reference.

• Import VHDL text files using the VHDL In utility.

For more information about using VHDL In, see the VHDL In for Virtuoso Design Environment User Guide and Reference.

• Use the Design - Create Cellview - From Cellview command in the schematic editor.

• Use the File - New - Cellview command in the CIW.

• Open the cell for editing in Library Manager and save it.

• If you were previously using the Cellview-based netlister and you are unsure which of the cells do not have the Virtuoso database (.cdb ) file, or have a lot of views that do not have the database, perform the steps described in Updating Text Views That Do Not Have Design Database Information.

View list and stop list of a configuration

When a design is netlisted, the instance of a cell in the design needs to be associated with its corresponding schematic or simulator primitive. This process is called switching views. The list of valid views to be used for switching is specified in the view list of your configuration.

A view that is the most detailed description desired for simulation is called a stopping view. The list of valid stopping views is specified in the stop list of your configuration. If the view located when switching views corresponds to one specified in the stop list, the expansion process for the instance is stopped, and the connectivity information for the instance is printed to the netlist file. If the view does not correspond to a stopping view, the expansion process continues.

Note: You can use the Hierarchy Editor to specify the view list and stop list for your configuration. For more information, see the Cadence Hierarchy Editor User Guide.

You can use Hierarchy Editor to specify view binding at the instance level. View binding at the instance level allows you to explicitly specify that a different view of a cell must be used for netlisting an instance of the cell. For more information, see the Cadence Hierarchy Editor User Guide.

Netlisting as analog or digital when an instance is bound to the symbol view in your configuration

By default, an instance that is bound to the symbol view in your configuration is netlisted as digital. If you want the instance to be netlisted as an analog primitive using the Spectre CDF simulation information, do one of the following:

• Open your configuration in Hierarchy Editor and replace symbol with spectre in the view list and stop list.

• Choose Simulation - Options - Netlister and add symbol in the Netlist using spectre CDF simInfo field.

Netlisting of inherited connections

Inherited connections allow you to selectively override the global signals in your design. This allows you to use multiple power supplies in a single design. If you want to implement separate power supplies (analog and digital, for example, or +3 V and +5 V) in a hierarchical design, you can assign net expressions to those global signals whose defaults you might want to override. Then you can use netSet properties to specify the new values of the signals. For more information about inherited connections, see the Inherited Connections Flow Guide and the Virtuoso Inherited Connections Tutorial.

Updating Text Views That Do Not Have Design Databas e Information

The OSS-based AMS netlister currently does not support designs with text-only views--text views that do not contain the Virtuoso database. To create the database for such views, in ADE, choose Tools - Update Cell Views

The irun Run Mode

The irun run mode is a single step run mode that uses the irun utility for the compilation, elaboration and simulation of designs. This run mode is available only with the OSS-based AMS netlister and not with the Cellview-based netlister.

The irun utility uses file extensions of input files to determine which compiler to use. For example, files with the .v extension are compiled as digital Verilog, files with the .vhd extension are compiled as digital VHDL, files with the .vams extension are compiled as AMS, and so on. After the input files are compiled, irun automatically starts ncelab to elaborate the design and then starts ncsim to simulate the design. For more information about the irun utility, see the irun User Guide.

Note: You need to install the Cadence IUS 6.1 or a later release to use the irun utility. Cadence recommends using irun from the IUS 6.11 or later releases. If you are using an IUS release earlier than IUS 6.1, ADE will use the ncverilog utility instead of the irun utility. If the ncverilog utility is used, the VHDL blocks in your design will not be netlisted.

You can specify the options for running irun using the irun Options Form and specify the compiler, elaborator and simulator options using the Compiler Options, Elaborator Options and AMS Simulator Options forms.

Netlist and Run Command

The Netlist and Run command generates the irun command using the options specified in the irun Options form.

Chapter 2 Building an AMS case in ADE This tutorial demonstrates how to set up and run the Virtuoso® AMS Designer simulator in the graphical environments in the IC612 ISR 14. It illustrates on how to prepare a design that has both Verilog® modules (Digital portion) and a schematic database (Analog portion). You need about 30 minutes to complete this tutorial, excluding the simulation run time for the design.

The AMS Designer Simulator

The Virtuoso® AMS simulator is a mixed-signal simulator that supports the Verilog®-AMS language standard. Two analog solvers, Virtuoso® Spectre® and Virtuoso® UltraSim, give designers the ability to match the simulation with the characteristics of their designs. The Spectre solver provides a proven, highly accurate simulation while the UltraSim solver provides a fast simulation suited to designs containing large numbers of devices such as transistors, resistors and capacitors. The AMS simulator is supported in both the Analog Design Environment (ADE) and the Cadence® hierarchy editor (HED). For those who use Spectre, or UltraSim or SpectreVerilog in ADE, the graphical interface makes it easy to migrate to the AMS simulator in ADE. For those who prefer using the command-line mode in design verification, the AMS simulator also provides a robust and easy-to-use command-line flow called AIUM (AMSD Incisive Use Model). You can get it from $IUS_INST_DIR/tools/amsd/samples/aium. This tutorial will walk you through the steps that ADE users need to take in preparation for using the AMS simulator.

Mixed-signal Design with AMSD in ADE

A mixed-signal design usually has two portions, Analog and Digital. Analog portion is usually in the form of schematic. The schematic can be reused directly from your previous simulation with standalone analog simulator like Spectre or UltraSim, or from analog/digital co-simulator like spectreVerilog or UltraSimVerilog. Digital portion in most of the cases is verilog. To create a mixed-signal design, you need to import the verilog modules into dfII and form a complete mixed-signal design along with analog schematic. In high-level, to simulate a mixed-signal design with AMSDE in ADE, you need to do the following (assuming the schematic data for analog and verilog modules for digital are ready).

• Importing Verilog/VHDL modules into dfII/ADE • Completing the mixed-signal design in Schematic Editor (Composer) • Configuring the design in HED (Hierarchical Editor) • Setup ADE options and Customizing the Connect Rule • Simulating it using AMSD in ADE

In the following sections, we will go through them one by one based on a design case. The example used in this tutorial is a mixed-signal 160 MHz PLL circuit that includes both a schematic database and Verilog code. The analog components include a VCO, a phase frequency detector (PFD), a charge pump and a loop filter all based on the schematic. The two digital frequency dividers are RTL-level Verilog modules, The key files and directories are:

• cds.lib : defines the associated libraries for designs, Cadence shipped standard libs, Fab foundry libs, etc.

• artist_states: stores the simulator setup settings concerning ADE. • gpdk090: the 90nm process design kit (PDK) • models: the device model files in Spectre format

• amsPLL: the library stores the PLL blocks for the schematic database • dig_source: stores the two behavioral Verilog frequency dividers • clean_up : a script clean up all the intermediate files

The key signals are:

• pll_160MHZ_sim.I3.vCNTL � The VCO’s control voltage signal • pll_160MHZ_sim.CLK_REF � A 25 MHz clock reference • pll_160MHZ_sim.CLK_160MHZ � The 160 MHz PLL output • pll_160MHZ_sim.I3.VCO_CLK � The VCO’s output voltage signal

Set up the tools and start dfII

Action 1: Set the path to IUS81 and IC612. For example,

setenv CDSHOME /cds/tools/IC612 setenv AMSHOME /cds/tools/ius81 set path= ( $AMSHOME/tools/dfII/bin $AMSHOME/tools/bin $path ) set path = ( $CDSHOME/tools/bin $CDSHOME/tools/dfII/bin $CDSHOME/tools/dfII/pvt/bin $path )

Action 2: Set up the tutorial:

%gunzip –c amsdInADE.tar.gz | tar xvf - %cd amsdInADE

Action 3: Type virtuoso & at the command line. The CIW window appears.

Importing the Verilog Module into dfII

There are several ways for you to import the verilog code into dfII:

1. Creating Cellview from Cellview in Schematic Editor For example, when you have a “symbol” view ready, you can use this approach to create a “module” view from “symbol”. The tool pops out a text editor with a framework automatically created for your verilog module. After filling up the verilog body, save it, the tool internally calls verilog parser to check the syntax for you.

2. Library Manager: File -> New -> Cell View

This way allows you to create any view you needed, symbol, schematic, verilog module, etc.

3. Using Reference Verilog in HED This is not supported in OSS netlister yet (See CCR 574079)

4. Using -y/-v feature in ADE The major general usage for –y/-v are:

-y <lib_dir>

This specifies <lib_dir> as a library directory. Library directories are unix directories containing files which contain Verilog modules. The file names in the library directory must be the same as the Verilog module contained within them. For example, the NAND2 Verilog module needs to be in a file called NAND2. Now we can add a file name extension using the +libext command-line option. Thus with:

-y <lib_dir> +libext+.v

The Verilog description of the NAND2 module needs to be named: NAND2.v in the <lib_dir> unix directory. -v <lib_file> The –v <lib_file> specifies <lib_file> a library file. The contents of the library file (like the library directory) are searched to resolve module instances. Thus, the library file may have 1000 module definition in it but if only 2 modules are needed from the library file, only these 2 modules from the <lib_file> will be complied. This is VERY different from simply placing <lib_file> on the irun comamnd-line. Placing <lib_file> on the irun command-line without –v says to compile ALL modules in <lib_file>.

Thus in ADE, only this scenario is recommended to use –y/-v : you have a top level verilog module that instantiates many sub-modules. In this case, what you need to do is to create a symbol for this top verilog module and to use –y/-v to import all the definitions for those sub-modules. The advantage of this way is that you don’t have to create the symbols for each sub-modules. Of course, you can’t see the design hierarchy in HED for this verilog part. (But you can see it from Design Browser when you use SimVision.) The –y/-v GUI can be found in ADE: Simulation -> Options -> irun

5. Using the Verilog In Verilog In is the most common ways for the user to import Verilog modules into dfII. One of its advantages is that Verilog In can import verilog module and create a symbol for it at the same time. It will be introduced in this session through the example case. Details about Verilog In, refer to the Verilog In for Design Framework II User Guide and Reference.

Action 4: Check the two existing verilog modules under the dig_source directory in a terminal.

PLL_160MHZ_PDIV.v � divider with factor 5, used for input reference clock PLL_160MHZ_MDIV.v � divider with factor 64, used for VCO’s output clock

Action 5: In the CIW, click File — Import — Verilog. The Verilog In window pops out. Action 6: In the Verilog In form, double-click on the dig_source directory, then click the

PLL_160MHZ_MDIV.v file, type amsPLL in the Target Library Name field (or use the browser to specify it) and click Add to the right of the Verilog Files To Import field. The full path of this Verilog file appears in the field. Next click PLL_160MHZ_PDIV.v file and click Add next to the same Verilog Files to Import field. PLL_160MHZ_PDIV.v will be added to the field after the PLL_160MHZ_MDIV.v file.

Action 7: Scroll down the form to Structural View Names and change the view name in the Functional field to verilog. Then click Global Net Options tab, in the Power Net Name field change VDD! to VDD1! and click OK.

Note: Only VDD and VSS are used in the example and they are not global nets. To avoid a name conflict, change the name to VDD1!.

Action 8: When the import is complete, a message appears asking if you want to see the log file. Click Yes to display the log file window.

You will see error or warning messages in this log file if something is wrong during the import process.

Action 9: Close the log file window. Action 10: Click Tools — Library Manager to open the Library Manager. Action 11: Click View — Refresh. Action 12: In the Library column, click amsPLL to show all the cells in the amsPLL library. In the Cell

column, two new cells (PLL_160MHZ_MDIV and PLL_160MHZ_PDIV) are generated.

Note: Each of the 2 new cells has a symbol and a verilog view listed. They were automatically generated by Verilog In in previous step. Note the cells: PLL_160MHZ_MDIV_answer and PLL_160MHZ_PDIV_answer were previously created and saved in the library for reference.

Importing the VHDL Module into dfII

NOTE: VHDL-In is not ready in IC612ISR14, and will be available in the following ISR. To load a VHDL source file into dfII, you may use File - new… -Cellview in CIW as a workaround. There are two ways recommended to use to import the VHDL code into dfII:

1. Library Manager: File -> New -> Cell View 2. Using the Verilog In

Note : To use VHDL In, you must have “duluth ” in your path. You may use <IC install dir>/tools/ leapfrog/bin/duluth . Due to the deferent language features of VHDL, special attention should be paid. Note:

VHDL language is case insensitive. This means that an identifier AbC is identical to abc and refer to the same object. However, Verilog and VerilogAMS are case sencitive. To keep the case sensitive in VHDL, we can enclose it with escape mark, backslash “\”, like \AbC\.

However, VHDL and Verilog/VerilogAMS expain the escaped name differently. In Verilog, an escaped name (\AbC\) is equivalent to its unescaped version of the name (AbC). However, in VHDL(-AMS), an escaped name (\AbC\) is an unique name (\AbC\). To solve this, AMS offer an option “-mixesc ” to use in elaberation.

Pls ignore this error when starting VHDL-In ** glibc detected *** double free or corruption (!p rev): 0x08c894f8 ***

Example The example is an inverter in VHDL language. Please note that the entity name, inv_VHDL contains both uppercase and lowercase. In this situation, by default the generated cell name will be all in lowercase, as inv_vhdl. If you want to keep an escaped cell name, you should add the backslash “\” around the entity name as below and then use “-mixesc ” option in the elaberation.

--Entry: inverter -- Architecture: structural library IEEE; use IEEE.std_logic_1164.all; entity \inv_VHDL\ is port ( vin: in std_logic; vout: out std_logic); end \inv_VHDL\; architecture vhdl of \inv_VHDL\ is begin vout<= not(vin); end vhdl;

The use mode of the two methods for VHDL is almost the same with that for Veilog. You may refer to Design Framework II User Guide and Reference.

Completing the mixed-signal design in Schematic Edi tor

Now we need to add the digital blocks into Schematic Editor. Action 13: In the Library Manager, open amsPLL.PLL_160MHZ:schematic .

The schematic is supposed to be the whole PLL circuit but still missing the two digital blocks you imported with Verilog In.

Action 14: Add the PLL_160MHZ_PDIV symbol and connect the nets as shown in the next figure.

Action 15: Add the PLL_160MHZ_MDIV symbol and connect the nets as shown. Click Sideways and then Upside Down button in the Add Instance form to rotate the symbol in order to meet the place requirement.

Action 16: Check and save the schematic. The completed design displays as shown.

All parts of the PLL design are finished. Before you can simulate the behavior of the design, you need to build the testbench, including the power supply and stimulus.

Action 17: Close the schematic. In the Library Manager, open amsPLL.

PLL_160MHZ_sim:schematic .

In this schematic, the testbench has been created. Notice that the power supply (VDD) is 2.5 V.

Action 18: Close this schematic and open the Library Manager.

Configuring the design in HED

Before running the AMS simulation, you need to configure the design in HED by telling the tool which cells need to use which view (schematic, module, av_extracted, etc.). Action 19: In the Library Manager, click amsPLL.PLL_160MHZ_sim .

Note: Only schematic view is available. AMSD can’t simulate a “schematic” view. You need to create a config view for AMS simulation.

Action 20: Highlight amsPLL.pll_160MHZ_sim:schematic in the Library Manager and click File ->

New -> Cell View. Action 21: In Create New File form, click type field and select config type. And then Hierarchy-Editor is

automatically selected in Open with field. The form should look like the following figure:

Action 22: Click OK. A New Configuration form opens. Enter schematic as the Top Cell View or click the field to select schematic in the list. And then click Use Template.

Action 23: Select AMS in the Template Name field and click OK.

The Global Bindings section in HED is filled with values taken from “AMS” config template. “AMS” is the unified config template for both Cell-based and OSS netlister in AMSD.

The cells in the design are bound to views depending on • What views of the cell are available • Which available view comes first in the view list

Action 24: OK to the “New Configuration” form to get the “Cell Bindings” with the default “AMS” config

template.

You can see the amsPLL.PLL_160MHZ is bound to “verilogams”. This is because it has “verilogams” view available and this view comes first in the “View List”. If you intend to simulate this DUT with the behavioral model, it is ready to go. However, in this example, we want to simulate it using “schematic” config. You need to change the view order in “View List”.

Action 25: Remove “verilogams” and “behavioral” from view list or put them after “schematic”, and hit

“Update” icon in HED. You should get the expected “Cell Bindings”.

Action 26: Click File — Save (Needed) to save the configuration.

Note: All the blocks are bound schematic view except PLL_160MHZ_MDIV and PLL_160MHZ_PDIV that are “verilog” view.

Action 27: Click Open on the left side of the hierarchy editor to open the configured schematic.

The config view for the pll_160MHZ_sim cell has been added to the Library Manager.

Set Up ADE Options and Customize the Connect Rule

This section will introduce the necessary and important steps on how to set up ADE options and especially Connect Rule (including Connect Module). Action 28: In Schematic Editor, Tools -> ADE L, to open the Analog Design Environment L. Action 29: In the ADE window, click Setup — Simulator/Directory/Host and set the simulator to ams in

the Simulator cyclic field. Click OK. Action 30: In the upper middle of the ADE window, check which analog solver will be used.

By default, it should display the simulator as ams(Spectre). If you want UltraSim as the solver, click Simulation — Solver, change the solver to UltraSim.

Action 31: Click Analyses — Choose. Then type 8u in Stop Time field. Click Enabled and OK. Action 32: Click Setup — Model Libraries. In the Model Library Setup form, click the Browse botton to

find the gpdk090.scs file from ./models/spectre directory. Click Section field and choose NN, then click OK.

In AMSD, to set up the Crule (Connect Rule) and CM (Connect Modules) properly is extremely important. There are there sets of built-in connect rules are available in IUS installation:

• Full • Full-Fast • Basic

where Full are the most accurate and Basic are the fastest. The default is Full_Fast that is recommended for the AMSD users. Additionally, in the built-in Crule/CMs, the vsup with 1.8V, 3V and 5V are provided only. If your design uses the vsup other than those three values, you need to customize the exiting one and build up your own. The following Actions will display the steps how you customize the Crules and CMs for your design. Action 33: Click Setup — Connect Rules.

This Select Connect Rules form is the major area for you to set up or customize your Crule/CMs. You may notice that the default Crule is ConnRules_18V_full_fast in the “List of Connect Rules Used in the Simulation” and “Rules Name” in the “Built-in rules” section. Because the power supply in this PLL is 2.5 V , which doesn’t exist in the Built-in rules list, you need to customize a Crule (ConnRules_18V_full_fast in this example).

Action 34: Click Customize in the “Built-in rules” section. In the Customize Built-in Rules form, change

the Description to “This is the description for My_ConnRules_25V_full_fast ”.

In the Connect Module Declarations list, the L2E_2, E2L_2, Bidir_2, R2E, E2R and ER_bidir are the default CMs used in this Crule. The R2E, E2R and ER_bidir are the CMs between Real number and Electrical (meaning analog) data type. In this example, since there isn’t any real, they will not be used. So only the CMs between Logic and Electrical need to be customized. Click on L2E_2 then vsup in the Parameters list, change 1.8 to 2.5 in Value field and click Change. Similarly, highlight both E2L_2 and Bidir_2 and change the values of the following parameters: E2L_2 vsup=2.5 vthi=1.7 vtlo=0.8 Bidir_2 vsup=2.5 vthi=1.7 vtlo=0.8 Click OK. In the Information form, which reminds you to add the customized connect rules to the list, click OK. Note, if you want to modify the default value for other parameters, follow the same steps above.

Action 35: In the Select Connect Rules form, select Connect Rules form, click Add and select the new

modified connect rules. Click Rename and edit the rule name to My_ConnRules_25V_full_fast . Click OK.

Action 36: edit the rule name to My_ConnRules_25V_full_fast . Click OK.

This is the final Crule you will use for your design. Action 37: In the ADE window, click Outputs — To Be Plotted — Select on Schematic and click

CLK_REF and CLK_160MHZ on the top level. Then repeat for vCNTL and VCO_CLK in the I3 instance.

Action 38: Simulation – Netlister and Run Options

NETLISTER AND RUN MODE

There are two AMS netlisters supported in ADE, the traditionally CB (Cell-based) netlister and the new OSS netlister. In the release of IC612 ISR with version of 14, to any new AMSD/ADE users, including Spectre ADE, UltraSim ADE, spectreVerilog and UltraSimVerilog users, the OSS netlister is recommended. To the existing CB netlister user, you may continue to use it. In this workshop, OSS netlister will be used, along with irun AMSD simulator.

RUN OPTIONS

If you select Compile Incremental/All, you will be able to compile.

If you select Elaborate Incremental/All, you will be able to compile and elaborate. Even if Compile Incremental/All is not selected, you will be able to compile and elaborate.

If you select Simulate, you will be able to simulate.

• There is no option in irun that will allow only elaboration to work.

• You can choose to only compile, elaborate or simulate the design, although by default all three are selected as shown in the screenshot. For example, if you select only Elaborate, the Simulation - Netlist command only elaborates the design. Compilation and elaboration can be incremental or for the whole design together.

A simulation will fail if you choose both Compile and Simulate. You would need to either deselect Simulate or select Elaborate as well.

• Select “Clean existing snapshot and pak files” to delete any existing simulation snapshot and .pak files before running the simulation.

This option is available for the irun run mode only.

SIMULATOIN MODE You may also notice that there are two SIMULATION MODE, Batch (normal) and Interactive (debugger). The former is default, meaning after the simulation is over, WaveScan (or Viva), the default waveform viewer, will automatically pop out with the selected waveforms loaded. The latter will call the SimVision debugger environment and you will need to control the whole simulation or interactively debug it, using the SimVision icons or TCL commands.

Action 39: In the ADE window, click Simulation - Netlist - Create. After the netlist process is finished,

click Simulation - Netlist - Display to display the Verilog-AMS format netlist.

Note: This file is for displaying purpose only. It is the same as that in the Cell-based netlister, the default netlister. In OSS netlister, it displays concatenated text in the files netlist.vams, cds_globals.vams, amsControl.scs, amsControl.tcl, etc. If you need to modify it you can edit ./simulation/PLL_160MHZ_sim/ams/config/netlist.vams . However, you have to launch AMSD simulation by invoking runSimulation script from where it is located. (Otherwise, the GUI will overwrite what you have modified.)

Action 40: Close the netlist form. Action 41: An undefined variable was detected after the netlist is created. In the ADE Simulation

window, double click the fREF variable in the Design Variables list, add 25M in Value field and click OK.

Note: You can also find the design variables used in your design by choosing Variables - Copy from Cellview.

Action 42: In the Outputs section, confirm that the Plot and Save columns are checked for all signals.

Otherwise, double click them to achieve so. Action 43: Check the runSimulation script by vi simulation/PLL_160MHZ_sim/ams/config/netlist/run Simulation

You may notice that the irun runSimulation script is much simpler than that in CB/3-step simulator flow.

Action 44: Click Session — Save State. In the Saving State form, change the name in State Save

Directory field to artist_states , change the state name to state_ams in the Save As field and click OK.

Thus, all the settings you made in the ADE Actions above has been saved in the artist state file of “state_ams ” under ./artist_states . You can load it in the future when you restart the ADE.

Simulating it using AMSD in ADE

Action 45: Confirm that simulator is ams(Spectre) in the upper area of the ADE window. Action 46: Confirm that Batch (normal) mode is selected for SIMULATION MODE by clicking

Simulation — Netlister and Run Options.

Note: Because the run time is bit long, you may shorten the transient time or skip next step. Action 47: Click the green light icon (for netlist and run). The AMSD with Spectre solver begins to run in

Batch mode. After the simulation finishes running, the WaveScan viewer automatically shows the plotted waveforms.

The transient run time is about 2 hours. The VCO control voltage signal reaches the stable value at about 7 us and the whole PLL system obtains the lock state. However, if you use Spectre-Turbo as the solver, the simulation will be much faster. Refer to the “Spectre Turbo in AMSSpectre” chapter for details.

To use SimVision debugger environment, do the following. Action 48: Click Simulation - Netlister and Run Options and click Interactive (debugger) mode for

SIMULATION MODE. Click OK. Click the yellow light icon (run) to rerun the example. Simvision starts.

Action 49: Click Simulation - Run to start the simulation. The waveforms update progressively until the

simulation completes. You can observe the detail of the waveform by zooming in on the x-axis and zooming full on the y-axis.

Action 50: Click File - Exit SimVision to return to ADE. To use UltraSim as the analog solver, do the following. Action 51: Click Simulation - Solver, change the solver to UltraSim and click OK. Action 52: Click Simulation - Options - FastSPICE (UltraSim). In the FastSPICE (UltraSim) Options

form, change Speed Option from Default (5) to Accuracy (3) and click OK.

Action 53: Click the green light icon (netlist and run) to rerun the example. Click Simulation - Run to

start the Simvision. Action 54: After the simulation is finished, click File - Exit SimVision to return to ADE.

With the UltraSim solver, the run time is about 9 minutes. Compared this with 2 hours for the Spectre solver, AMS Designer with the UltraSim solver achieves almost over 10X speedup. In general, AMS Designer with the UltraSim solver more targets the simulation and verification on full-chip design with big capacity, while spectre solver focuses on the block designs.

Action 55: Check the irun.log file (the simulation log file) by choosing Simulation – Output Log – irun

log, or vi ./simulation/PLL_160MHZ_sim/ams/config/psf/irun. log

Of course, the irun log file also automatically pops out when the simulation is started.

Action 56: Click Simulation - Netlister and Run Options and change Interactive (debugger) mode back

to Batch (normal) mode and click the green light icon (netlist and run) to rerun the example. Once the simulation is complete, the waveform appears.

Chapter 3 Migrating from SpectreVerilog to AMSD

SpectreVerilog/UltrasimVerilog was the major mixed-signal simulation solutions on the market. However, due to limitations in speed, capacity, and features, it gradually had trouble handling more complicated mixed-signal designs with new technologies. Thus, AMS Designer, the next generation mixed-signal simulation and verification tool, is becoming more and more accepted by chip designers for its powerful functionality and improved performance on today’s mixed-signal designs.

Background

The example used in this tutorial is a PLL design that has a 25 M input signal and a 160 M output signal. The design has 305 mosfets, 97 resistors, 35 capacitors and more than 30 behavioral modules. The testbench for the PLL design is shown in Figure 1. Inside the I3 component, the PLL_160MHZ_PDIV(I23) outputs a 5 MHz reference signal for the loop. PLL_160MHZ_MDIV(I24) outputs a 160 MHz signal and a 5 MHz feedback signal for PLL_FPD. When the two PD input signals are out-of-sync, the PD generates corrective pulses (UP, DN) to adjust the charge pump output voltages (vCNTL ), which controls the frequency of the VCO. Whenever the PLL is locked, the FBCLK and 5MHZ_CLK signals are in phase and the VCO control signals v(vCNTL) are stable.

Fig 1. Testbench for the PLL Circuit

In this tutorial, you first simulate the PLL with UltraSimVerilog/spectreVerilog, and then you rerun the simulation on the same config view in AMS Designer. The tutorial also covers the OSS netlister, ncverilog flow, -v/-y, compiled VerilogA, Fastcross and other AMS features. The recommended software versions are IC612, MMSIM 7.0 and IUS8.1 . Action 1: Come to the tutorial directory.

%gunzip –c migrateFromVerimixToAMSDinADE.tar.gz | t ar xvf - %cd migrateFromVerimixToAMSDinADE

Action 2: Set up the environment variable then start icfb.

% source SETUP % virtuoso &

Simulating in UltraSimVerilog

Action 3: Invoke the Library Manager from the Command Interpreter Window (CIW) by clicking Tools

— Library Manager . Action 4: In the Library Manager, click amsPLL for Library and click pll_160MHz_sim (scroll down to

find it) for Cell . There are two Views. Double click config in the View panel. In the Open

Configuration or Top CellView form (Figure 2), click Yes for both options and click OK.

Fig 2. Open Configuration or Top CellView Window

The hierarchy editor (HED) and the Schematic window open as shown in Figure 1.

Action 5: In the Schematic window, click I3 and then press the key e. In the Descend form (Figure 3),

click schematic for View Name and click OK to descend into and edit the I3 component. The Schematic in Figure 4 opens.

Fig 3. Descend Form

Fig 4. Schematic for the PLL Component I3 Action 6: In the Schematic window, start the Analog Design Environment (ADE) by clicking Launch —

ADE L . Notice the words Simulator:spectre in the middle of the bar under the menus in the ADE Simulation window.

Action 7: Change the simulator to UltraSimVerilog by clicking Setup — Simulator/Directory/Host (see Figure 5). In the Simulator/Directory/Host form, click UltraSimVerilog in the Simulator cyclic field and click OK.

Fig 5. Simulator/Directory/Host Form

Action 8: In the ADE Simulation window, click Session — Load State to load a simulation state file.

Load the state file by clicking state_uv and OK.

Fig 6. Analog Design Environment Window

In the ADE window (Figure 6), notice that the transient simulation time is 10 u (Analysis section) and the list of nodes to plot after the simulation (Outputs section). Both are set by the state_uv state file you loaded.

Action 9: To verify model files, click Setup — Model libraries (Fig. 7). After viewing the Model Library

Setup form, click Cancel to close it.

Fig 7. Model Library Setup File

Look at the UltraSim Simulator Options by clicking Simulation — Options — Analog . This displays the Simulation Mode, Speed Option and Post-layout Method. See the UltraSim User Guide for descriptions of these options.

Fig 8. Simulator Options Form

Action 10: Click Simulation — Options — Digital to check options for VerilogXL. The Verilog-XL

Simulation Options form opens. Notice source_file/dffr_2x_hv.v source_file/inv_1x_hv.v in the Library Files field. If you open amsPLL:dffnr_2x_hv:module , you will see that module dffnr_2x_hv calls two sub-modules: dffr_2x_hv and inv_1x_hv . Thus, you must use the –v option to include them in the design. You will see the same functionality in the AMS ncverilog flow.

Action 11: Click Simulation — Options — Mixed Signal to check Mixed signal Options (see Figure 9).

In the Convergence section set both DC Interval and Max DC Iterations to 5. This helps with

DC convergence.

Fig 9. Mixed Signal Options Form

Action 12: On the schematic, click Launch – Mixed Signal Opts – Verimix to add the Verimix pull-down

menu to the schematic window. Open the Verimix – Partitioning Options form. On this form, add module to the Digital Stop View Set after verilog and before behavioral. The Digital Stop View Set should look like this: verilog module behavioral functional hdl system verilogNetlist msps.

Action 13: In ADE, click Simulation — Netlist and Run to generate the netlist and run the simulation.

When the simulation is done, close the simulation log file forms by clicking File—Close Window .

Action 14: When the simulation finishes, the Wavescan window pops up and presents the output

signals. Notice that the top 2 signals in the Wavescan window are digital signals and that the analog signals are overlaid at the bottom. By clicking Axis — Strips you see the same plot as shown in Figure 10. From Figure 10, you can see that vCNTL oscillates at first and then gradually becomes a flat line.

Fig 10. Simulation Results in the Wavescan Window

Action 15: To see how to create IEs in UltraSimVerilog, click Verimix — Display Partition — Interactive.

The Partition Display form opens as in Figure 11 and you see different colors representing different natures of blocks in the design: analog, digital and mixed-signal. Click OK.

Fig 11. Partition Display window

In the Schematic window, click I3 and then press the key e. The Descend form in Figure 12 uses color to indicate which blocks are analog, digital and mixed signal. The blocks and lines in light brown are mixed signal blocks. In general, you will not see IEs.

Fig 12. Schematic Showing Partitions

Action 16: Review the Verimix - Interface Elements set up. The set up for AMS Designer is different.

Record the simulation time. For reference, the simulation is 8m58ss on our Solaris machine with a 1.6 G CPU.

Simulating in SpectreVerilog

The Cadence Mixed-Signal Design Environment provides two solvers: • SpectreVerilog • UltraSimVerilog. UltraSimVerilog was used to simulate the previous examples in this tutorial. If you want to run the SpectreVerilog simulation, follow these steps. Action 17: In the ADE Simulation window, change the simulator from UltraSimVerilog to SpectreVerilog.

Click Setup — Simulator/Directory/Host. A new window (the same as Fig. 5) opens, choose spectreVerilog from the list and click OK.

Action 18: Close the Wavescan window. Click File — Exit to close Wavescan. Action 19: Click Session — Load State to load the simulation state. In the Load State form, select

state_sv and click OK. Action 20: Click Simulation — Netlist and Run to start the simulation. The spectreVerilog solver

requires more time than UltrasimVerilog to finish the simulation. As a reference, the simulation lasts 60 m on our Solaris machine with a 1.6G CPU.

Simulating in AMS Designer with the Same Configurat ion

To run AMS, you might assume that a new config is required for AMS and that it should be generated in the Hierarchy Editor (HED). However, this is not true if you are using the OSS netlister. You can reuse the same config, unless you want to make changes only in the AMS config without affecting your UltraSimVerilog config. There are two netlisters for AMS in ADE.

• The Cell Based netlister is the original netlister for AMS. The Cell Based netlister requires an ams siminfo when it generates the individual verilog.vams netlist files within the 5X library structure. For more information about this netlister, consult the AMS manual.

• The Open Simulation System (OSS) netlister is available from IC 5.1.41 USR4. You can use the

OSS netlister when you migrate from SpectreVerilog / UltraSimVerilog to AMS. The OSS netlister uses the existing spectre views, as do UltraSim and UltraSimVerilog. The OSS netlister generates a netlist file called verilog.vams that includes all the modules needed for compilation. This is very similar to the Spectre/UltraSim/spectreVerilog/UltraSimVerilog flow in that the final netlist is one file. The OSS netlister for AMS works in essentially the same way as it works for Spectre or UltraSim.

Action 21: In the ADE window, change the simulator from UltraSimVerilog to AMS. Click Setup —

Simulator/Directory/Host to open the Simulator/Directory/Host form (see Figure 5). Click ams for Simulator. Then click OK to close the form.

Action 22: Close the Wavescan window if it is still open. In Wavescan, click File — Exit.

Action 23: Load the simulation state file. Although you use the same config for UltraSimVerilog and

AMS, you will need different simulation settings. Click Session — Load State and select state_amsu for State File and click OK.

An Introduction to Connect Rules and Disciplines in AMS Designer

The AMS simulator uses disciplines, connect modules, and connect rules in place of A2D and D2A interface elements. A discipline denotes an object as analog or digital (with, for example, an electrical or logic discipline). When you connect objects of different disciplines, connect rules determine which connect modules to insert between the objects. The inserted connect modules convert signals to values that are appropriate for each discipline. To tailor conversion of your design, you can modify connect rule parameters, such as supply voltage or rise time, that are used in the connect modules. For more information about disciplines, connect rules, and connect modules, see Chapter 11, "Mixed-Signal Aspects of Verilog-AMS," "Cadence Verilog-AMS Language Reference." For guidance on using the forms mentioned above, click the Help button located on each form. Cadence provides some sample connect rules in the following directory: $AMSHOME/tools/affirma_ams/etc/connect_lib/. The sample connect rules are called Built-in Connect Rules (CRs) and they are ready to be used in ADE. However the built-in CRs only work for some selected voltage supplies (for example, 1.8 V, 3 V and 5 V) and you might need to modify the parameters to customize a built-in CR to fit your design. In addition, if the built-in CRs are not sufficient, advanced designers can write their own specific CRs and include them in the simulation. In this example, the voltage supply is 2.5 V, so we can customize the 3 V build-in CR to fit the simulation.

Note: Cadence provides built-in CRs for full-fast, full and basic CRs. To speed up the simulation for complicated designs, full-fast models are recommended. You can get more information about CRs in the AMS manual. In this specific example, since we don’t need a bi-directional CR, we can choose the simplest CR..

Action 24: Click Setup — Connect Rules to create specify and customize connect rules in AMS in ADE.

Fig 13. Select Connect Rules Form

Action 25: In the Select Connect Rules form (see Figure 13), from the Rules Name cyclic field, select

connectLib.ConnRules_3V_basic . Click View and look at the content of the connect rule. Then, click Customize to customize this built-in rule.

Action 26: In the Customize Built-in Rules form (similar to Figure 14), change the Description to This is

the description for My_ConnRules_2_5V_mid .

Highlight E2L_0, L2E_0 and Bidir_0 together in the Connect Module Declarations section and the shared parameters will display in the Parameters section. Modify the values of these parameters: vsup=2.5 , vthi=1.6 , vtho=0.8 and tr=0.2n , by clicking on each of the parameters, one by one, modifying its value and clicking Change after each modification. Now the form looks like Figure 14.

Fig 14. Customize Built-in Rules Form

Action 27: Click OK to exit the Customize Built-in Rules form and click OK on the Information pop up. Action 28: Click Add in the Select Connect Rules form and it should look like Figure 15. Notice that the

Type is Modified built-in .

Fig 15. Select Connect Rules Form

Note: In the Select Connect Rules form, you are setting the global connect rules that apply to the whole design. However, there are certain scenarios where a designer might want to have multiple connect rules in the same design. You can set disciples on a net, cell, instance, or library and you can set multiple connect rules accordingly. For details, please see the AMS Designer manuals.

Action 29: Click OK to exit the Select Connect Rules form. Action 30: Click Setup — Model Libraries to check model libraries setup (similar to Figure 7) and then

Cancel that form. Action 31: In the ADE Simulation window, click Simulation — Solver to select the analog solver.

Fig 16. Select the Analog Solver

The simulator in AMS Designer uses one of two analog solvers AMS-Spectre uses the Spectre solver AMS-Ultra uses the UltraSim, fastspice solver Select UltraSim to use the AMSUltra, the UltraSim fastspice solver (Figure 16) and click OK to close the Choose Solver form.

Action 32: Click Simulation — Netlister and Run Options to open the Netlister and Run Options form (similar to Figure 17). Choose OSS-based netlister with irun and enable Clean existing snapshot and pak files. For details about the setings, consult Chapter 2 Building an AVUM case.

Action 33: Click OK to close the Netlister and Run Options form.

Fig 17. Netlister and Run Options Form

Action 34: Click Simulation — Options — FastSPICE(UltraSim) to look at the UltraSim options

(Figure 18).

The FastSPICE (UltraSim) Options form contains simulation mode, speed and post-layout options. Refer to the UltraSim User Guide for more details on these options.

Action 35: If interested, you are encouraged to check other option forms. There are option forms for the

netlister, compiler, elaborator, AMS simulator and NC-Verilog. Please notice that at the

bottom of the AMS form Main Tab, there is an Additional arguments, +ncelabargs+"-iereport" field. It is described later.

A designer can set options for ncverilog by clicking on Simulation – Options - AMS. This form should be well known to SpectreVerilog users. Notice that –v/-y/-f support in the ncverilog flow is the same as for the previous UltraSimVerilog run that contained source_file/dffr_2x_hv.v source_file/inv_1x_hv.v in the Library Files field. The form should look like Figure 19. Click on Cancel to close the form.

Fig 19. NC-Verilog Options Form

Action 36: Click Simulation — Netlist and Run to generate the netlist and run the simulation. Action 37: After the simulation is done, review the log file. Scroll up to the top of the log file to see the

following text.

----------IE report -------------

Automatically inserted instance: pll_160MHz_sim.I3.I11.I15.net18__E2L__logic (merged ): connectmodule name: E2L, inserted across signal: net18 and ports of discipline: logic Sensitivity infomation: No Sensitivity info Discipline of Port (Ain): electrical, Analo g port

Discipline of Port (Dout): logic, Digital p ort Drivers of port Dout: No drivers Loads of port Dout: No loads

This reports the IEs inserted in the design. You must use the –iereport option to the ncelab command to display the IE report. From this report you can see all the info about each IE, for example: name, net, discipline, and so on.

Action 38: Scroll down in the log file form, after seeing the info for the UltraSim version and build time

until you see the following messages.

File read: /net/bj2lnx22/d01/export/lsong/Workshop/AMSdemo/Mig rate_2_AMSD/models/spectre/resd_va.va Opening directory amsControl.ahdlSimDB/ (775) Opening directory amsControl.ahdlSimDB/4003_AMSdemo_Migrate_2_AMSD_mo dels_spectre_resd_va.va.ahdlcmi/ (775) Opening directory amsControl.ahdlSimDB/4003_AMSdemo_Migrate_2_AMSD_mo dels_spectre_resd_va.va.ahdlcmi/SunOS5.8+gcc/ (775) Installed compiled interface for resd_va.

These lines report the new feature supporting the verilogA compiledC flow from IUS583. It is commonly used now in spectre and UltraSim and it gives a significant performance boost in many cases particularly when you are using Verilog-A to model CMOS devices such as mosfets, resistors and capacitors. It also supports bsources. Note that the compiledC VerilogA work is not in 5.1.41 USR4, but will be in an ISR following 5.1.41 USR4. You can check the logfile for lines similar to the following to check if you are using a version of 5.1.41 that supports the CompiledC VerilogA flow.

Action 39: A new feature in IUS583 is called Fastcross. It speeds up the simulation. If you scroll to the

end of the logfile, you see the report on Total global time steps: 1230952. Comparing this to the previous version, the new feature reduces the number of steps. The reduction varies from case to case. This feature is enabled by default from IUS583

After the simulation is done, close the simulation log file forms by clicking File — Close Window .

Action 40: The Wavescan window opens to plot output signals when the simulation finishes. Click Axis

— Strips to see the plot shown in Figure 20. When you compare this to Figure 10 you see that they are the same. This indicates that the migration is successful.

This tutorial is about migrating from spectreVerilog and UltraSimVerilog to AMS Designer, so it is interesting to compare the partitions created in AMS Designer with the partitions from the UltraSimVerilog simulation to see if they are the same. Action 41: In the Schematic window, click AMS — Display Partition — Initial ize and then AMS –

Display Partition - Interactive . The Partition Display window (Figure 21) opens. You can compare the different colors representing the different natures of the blocks in the design: analog, digital and mixed-signal. Click OK.

Fig 21. Partition Display Window

Action 42: Check the Schematic window as shown in Figure 22. Notice that the block and lines in light

brown are mixed-signal and in general they have CRs inserted.

Comparing Figure 22 to Figure 11, you can see that this example is partitioned the same way by both UltraSimVerilog and AMS Designer. AMS adds many new features. You can check the CR and discipline setup from both the Schematic window and the ADE Connect Rule Setup form.

Fig 22. Schematics in Partition

Action 43: Please write down the simulation time. As a reference, the AMSUltra simulation lasts

5min47s on our Solaris machine with a 1.6 G CPU.

Optional

AMSD has two analog solvers (Spectre and UltraSim) so you might want to try using AMSSpectre as the solver in this example. Action 44: Click Results — Save to save the output data before you rerun this simulation. Otherwise

the output of the previous run will be overwritten by the new run. Click OK in the Save Results form.

Action 45: In the ADE Simulation window, click Simulation — Solver and change the analog solver to

spectre as in Figure 16. Action 46: Click Simulation — Netlist and Run to start the simulation. Compared to AMSUltra,

AMSSpectre requires more time to finish the simulation. As a reference, the AMSSpectre simulation lasts 60 m on our Solaris machine with 1.6 G CPU.

Action 47: Compare the results of the AMSUltra solver with the results of the AMSSpectre solver.

Summary

The spectreVerilog and UltraSimVerilog solvers and the AMS solver are Cadence mixed-signal solutions. AMS Designer has many advantages including better performance (33% in this case), a more powerful digital solver (NCSim vs. Verilog-XL), powerful connect rules (CR), flexible discipline definitions, bi-directional CR support and more language support (VerilogAMS, VHDLAMS, SystemVerilog, SystemC). Previously the migration to AMS Designer was considerably more difficult because you had to convert Spectre siminfo to ams siminfo. This tutorial illustrates a straightforward and easy way to use the OSS netlister, and ncverilog which helps you leverage the advantages of AMSD without extra work.

Chapter 4 Migrating from CB to OSS AMS Netlister

Introduction

Until IC 5.1.41 USR3, the Cellview-based Verilog-AMS Netlister (CBN) was the only Verilog-AMS netlister integrated in ADE. However, with the increasing, impressive features of AMSD over Verimix (SpectreVerilog and UltraSimVerilog), there was the business need to migrate users of Verimix to AVUM. The CBN needs ‘ams’ CDF simInfo in the PDKs. The users of Verimix have ‘spectre’ CDF simInfo in their PDKs, and hence, to use the CBN, they have to create ‘ams’ CDF simInfo. This limitation resulted in the incubation of the new OSS-based Verilog-AMS Netlister (henceforth, referred to by the acronym ‘OSSN’ in this chapter). The OSSN was introduced in IC 5.1.41 USR4 and IC 6.1.0. After about two years of rigorous usage and subsequent enhancements, the OSSN now not only covers all the important features of CBN, but also provides features that the CBN does not support (for example, the ‘irun’ command of AMSD).

Purpose and Scope

This tutorial is to show how smooth and seamless it is to migrate from CBN to OSSN. The intended readers of this tutorial are existing users of CBN who are familiar with the AVUM, and the terminology and usage of ADE. Users who are not familiar with AVUM may first refer to Chapters 1 and 2. This section shows how CBN cases works with OSSN.

• Runing the tutorial case using CBN. • Runing the tutorial case using OSSN with the same “config” view.

Walking through this chapter, you’ll also have a view of OSSN’s new features/enhancements and new simulator related interface. (marked with )

• ADE “Netlister and Run Options” interface update • Dealing with “symbol” view and “spectre” view • Creation of the shadow • The same cell name with different view names

The recommended software versions are IC612 ISR#14 or later for ADE, and IUS8.1 or later for AMS.

Case Information

This tutorial example is a mixed-signal PLL circuit that consists of schematic, Verilog language design-units. The schematic contains the following analog components: a VCO, a phase frequency detector (PFD), a charge pump, and a loop filter. The two digital frequency dividers are RTL-level Verilog modules. The testbench for the PLL design is shown next:

Key directories are gpdk090 90 nm process design kit (PDK). models Model-files in Spectre syntax. amsPLL Library that contains the PLL blocks for the schematic. dig_source Directory that contains the two behavioral Verilog and VHDL frequency dividers.

Running the Tutorial

Action 1: Come to the tutorial directory.

% gunzip –c migrateFromCBNToOSSN.tar.gz | tar xvf - % cd migrateFromCBNToOSSN

Action 1: Set up the environment-variable ‘TUT_DIR’, and start the ‘virtuoso’ workbench.

Netlisting and Simulating using CBN with ncvlog, nc elab, ncsim

Action 2: Open ADE window. Verify that simulator is set to ‘ams’. Choose

amsPLL.pll_160MHz_sim:config as the design. Load state state_CB from directory

“./artist_states ”. Action 3: Open Netlister and Run Options window from Simulation menu, and notice that “Cellview-

based netlister with ncvlog, ncelab, ncsim” is chosen.

Note that there’re only two netlister and run modes, instead of separate netlister and run options. That means “OSS Netlister with ncvlog, ncelab, nsim” mode is removed. In fact, with the new advanced AMS utility irun , this combination is never needed. Also ncverilog is replaced by irun , and that means from IC612 ISR14, you may use irun in place of ncverilog in ADE.

Action 4: Click the green light at the right-bottom of the ADE window to netlist and simulate the design.

When the simulation completes successfully, you will see the results in a WaveScan window.

Netlisting and Simulating using OSSN with irun

1. Template for creating ‘config’ view

AVUM now provides a single, consolidated template named ‘AMS’ for creating ‘config’ views to

run AMS. This template is honored by both CBN and OSSN. The consolidated template ‘AMS’ has ‘spectre spice’ as the ‘Stop List’.

The existing config from CBN contains symbol as a stop view. If the OSSN finds an instance

bound to ‘symbol’ view, by default, the instance is treated as ‘digital’, and netlisted in Verilog syntax. To avoiding getting a wrong result, when the OSSN finds any cell bound to symbol view, a warning is issued asking the user to specify whether the cell bound to symbol is to be treated as digital or analog. If it is to be treated as analog (spectre CDF simInfo is to be read), then symbol should be added to the "Simulation->Options->Netlist->Netlist using spectre CDF simInfo" field. You may find below lines in CIW.

\o ++++++++++++++++++++++++++++++++++++++++++++++++ ++++++++++++++++++++++ \o \o INFO (184) : The following cells will be netlist ed without using the spectre CDF \o simulation information, because the y are bound to view symbol: \o *** Library - analogLib Cell - pm os4 *** \o *** Library - analogLib Cell - nm os4 *** \o *** Library - analogLib Cell - vs ource *** \o To use the spectre CDF simulation i nformation, do one of the following: \o - Open your configuration in Hierar chy Editor and replace "symbol" \o with "spectre" in the view list an d stop list.

\o - Choose Simulation->Options->Netl ister and add "symbol" \o in the "Netlist using spectre CDF simInfo" field. \o \o ++++++++++++++++++++++++++++++++++++++++++++++++ ++++++++++++++++++++++

2. Create the Shadow DB for Text Views to run OSSN

NOTE: The Interface of Create Shadow DB is not ready in IC612ISR14, and will be available in the following ISR. To Create shadow DB for a existing text view, you may open the text view from CIW or Library Manager and do “:wq” in the VI window as a workaround. And in this tutorial shadow DB is already created for every text view.

OSSN requires the Shadow CDBA. In order for the OSSN to walk the design it needs to have certain information such as the module name and the port list. The shadow is not needed for the CBN. This enhancement provides an easy way for the user migrating from CBN to OSSN.

The shadow DB can be created via VerilogIn, CV2CV or simply opening up the text in the Library

Manager and doing a “write” action in the text editor (“:wq”). Action 5: Close the WaveScan window and simulation log window. In ADE, load state state_OSS

from directory “./artist_states ”.

Open Netlister and Run Options window from Simulation menu. Notice that the “OSS-based netlister with irun” is selected.

Action 6: Select Simulation->Netlist->Create to create the netlist. You will find that netlisting is

unsuccessful. This is because a text view does not have shadow DB. You can read the name of lib-cell-view that does not have the shadow DB from the error message in CIW or in the netlister’s log file.

Action 7: ADE lets users check their design to find the missing shadows, and create them. In ADE,

choose Tools -> Update Cell Views… to invoke the Create Shadow window.

There are two use-models. The “For config” model takes the lib-cell-view of the config, walks through the design and creates shadow DB in all text views that do not have a shadow DB.

Action 8: The design specified at ADE is taken as the default config. Click OK to check all cellviews.

After a moment, a pop-up window appears informing the user how many cellviews have been updated with shadow DB.

Action 9: You can also try the other use-model “For Cell Views” to create shadow DB for specific

cellview. Choose “For Cell Views” and specify amsPLL.inv:verilogams as the lib-cell-view.

Click OK and after a moment, a pop-up window appears informing you that no view needs to be updated, thereby implying that the lib-cell-view you chose already has the shadow (you just updated all cellviews in ‘amsPLL’ library).

Action 10: Click Close and open Simulator->Netlist->recreate to netlist again. The netlist finishes

successfully.

3. Multiple Instances of the Same Cell Name with Di fferent Views

Action 11: In the CIW, open amsPLL.pll_160MHz_sim:config in the Hierarchy-Editor and choose

View->Tree. Decent into pll_160_MHZ_sim.PLL.PLL_VCO .

Notice that in pll_160_MHZ_sim.PLL.PLL_VCO, the cell inv has multiple instances of different views, and some are from different libraries. ------INVP2 (invLib.inv:verilog) ------INVP3 (invLib.inv:veriloga) ------INVP4 (amsPLL.inv:verilogams) ------INVP5 (amsPLL.inv:schematic)

Action 12: Check the netlist for the four instances INVP2 to INVP5 mentioned in Action 12. In ADE,

choose Simulation->Netlist->Display to read the definitions of the instances INVP2, INVP3, INVP4, and INVP5.

You will see that definitions of instances INVP2 and INVP4 (of the same cell ‘inv’,

albeit different libraries) are preceded by “`uselib ” statements, so that the instances are bound to the correct text file.

Read the definition of the instance INVP3. The name of the master-cell is extended to lib_cell_view so that the instance is bound to the correct VerilogA module.

Now, read the definition of the instance INVP5 a. You’ll see that the name of the master-cell of INVP5 is inv4 , and not inv. You may search for inv4 in the netlist. The name of the cell, whose schematic view is instantiated, is mapped to a different name (in this example, inv is mapped to inv4 ).

------------------------------ ùselib file=/home/ruilin/work/CBToOSS/amsPLL/inv/verilogam s/verilog.vams inv INVP4 ( INV_4_P, INV_3_P); ùselib inv4 INVP5 ( INV_5_P, INV_4_P); invLib_inv_veriloga INVP3 ( INV_3_P , INV_2_P ); ùselib file=/home/ruilin/work/CBToOSS/invLib/inv/v erilog/verilog.v inv INVP2 ( INV_2_P, INV_1_P);

`uselib

------------------------------ ------------------------------ // Library - amsPLL, Cell - inv, View - schematic // LAST TIME SAVED: Apr 29 02:03:34 2008 // NETLIST TIME: Apr 29 18:58:52 2008 `timescale 1ns / 1ns (* cds_ams_schematic *) module inv4 ( vout, vin ); ------------------------------

NOTE: 1) If you have schematic view and only one text view with same cell name, the netlist may be wrong using IC612ISR14, the fix will be available in the following ISR. Pls refer to CCR579486. 2) “instances with the same cell name in diferent hierachy in the schematic” is not supported using IC612ISR14, this feature will be available in the following ISR. Pls refer to CCR 569545.

4. Running Simulation

Action 13: Open Netlister and Run Options window from Simulation menu. Notice there is a the new

field “Clean existing snapshot and pak files” when turning on “OSS-based netlister with irun” . This is disabled by default. It can be enabled to remove all exiting pak files.

Action 14: In ADE, choose Simulation -> Options -> Run. The design will simulate

successfully, and a WaveScan window will open automatically to display the plotted signals.

Summary

The the CBN and the OSSN are two Netlisters serves for AMS netlisting. OSSN, after two-year enhancement, is more and more widely accept in the design field. Furthermore, OSSN has many supports for the new AMS utility irun , which will make it more popular in the futher.

Chapter 5 Multiple Supply based on Inherited Connec tion

The Mixed-signal designs with multiple power supplies are becoming more and more popular. In this kind of design, the information of certain power supplies needs to be shared between analog and digital circuitry, i.e. what power value the logic 1 should be converted, or what voltage threshold should be used to control when the analog signal should be converted to logic 0 or logic 1. As AMS Designer supports Automatic Inserted Connect Module (AIUM), how to enable this capability through AIUM is a key. In AMS Designer, there are two major techniques allowing you to do so properly.

• Multiple Supply based on Discipline Please refer to the Chapter of “Multiple Supply based on Digital Discipline”.

• Multiple Supply based on Inherited Connection In this technique, the use of inherited connection attributes and CDF “netSet” properties added to schematic allow you to create special global signals and override their names selectively in a design hierarchy. For detailed information on inherited connections, refer to the Virtuoso Schematic Composer User Guide. In this example, the multiple supplies based on Inherited Connection will be discussed. To demonstrate this inherited connection technique, a simple schematic buffer design was used and simulated in AMS Designer. Screen shots describing the setup, how-to-run instructions will follow. Come to the tutorial directory.

% gunzip –c MultiPwerInhConn.tar.gz | tar xvf - % cd MultiPwerInhConn

Set up the environment variable and then start virtuoso.

Action 1: Understand the design with multiple power supplies The design name is multiSupply_InhConn.AICM_InhConn . This particular example has 3 power supplies demonstrating the 3 process technologies that need to simulate together in this mixed-signal circuit. The top level testbench is shown in Figure 1.

Figure 1: Top level schematic: multiSupply_InhConn.AICM_InhConn The three power supplies are:

VDD! = 1.8V vdd33! = 3.3V vdd5! = 5V in which, VDD! = 1.8V is the global power supply, the instance I0 needs vdd5! = 5V as the power while I1 needs vdd33! = 3.3V. Note: the netSet property added on I0 and I1 . The vdd net expression in I0 will get overridden with the global value vdd5! = 5V. The vdd net expression in I1 will get overridden with the global value vdd33! = 3.3V. Figure 2 shows the hierarchy of I0 . All AICMs inserted at this level inherit the vdd su pply of 5V, as determined by the net expressions inside of the AIC M. Notice that a netSet propert was added to I28 , which is VDD! = 1.8V. AICMs under I28 will inherit the 1.8V for vdd.

NetSet property for I0

Figure 2: Contents of cell AICM_leaf1, instance I0

Action 2: Add netSet property The example database provided has netSet properties added already. However, here is how to add it. In Schematic Editor:

a. go to the top schematic by Design - Hierarchy - Return to Top b. Edit - Properties - Objects, right click on I0.

NetSet Property for I28

Inside instance I0

Figure 3: Edit Object Properties

c. In the Edit Object Properties, check “user” in Show section if it is not, to extend the user-defined CDF form (Figure 3).

d. Click Add to open Add Properties form (Figure 4):

Figure 4: Add Property

e. Fill the form as shown above. Note: the Type must be “netSet” f. Similarly, add netSet properties to I1 and I0.I28

Action 3: Check the ADE L setup by loading the prepared artist state file, state_ams from ./artist_states .

Check the Netlister and Run Options to make sure you will use OSS netlister and Interactive (debugger) simulation mode. The purpose using SimVision debugger here is to more easily explain how the design netlist containing Inherited Connect works with the Crule/CMs that are targeted for Inherited Connection.

Check the device model file. Especially, check the Connect Rule is set up correctly (Figure 5).

Figure 5: Select Connect Rules

In this example, ConnRules_inhconn_mid is used. Action 4: Check the Inherited Connection Connect Module

a. Click Customize in Select Connect Rules, and Customize Built-in Rules pops out b. Highlight E2L_inhconn in Customize Built-in Rules, and hit View Connect Modules. This opens

built-in CM module in Verilog-AMS format (Figure 6). Please read the comments.

Figure 6: The built-in inhconn CM Action 5: Start simulation with SimVision and check the design netlist

a. Hit the green light to start simulation b. Right click on “AICM_InhConn” and choose “Send to Source Browser” in the Design Browser.

The Source Browser opens with the netlist for top schematic (Figure 7).

Since the built-in CM use vdd and vss for the property names, it would be convenient to use vdd/vss in your design as well for netSet property

The built-in inhconn CM pre-defines the inhconn attributes as net expression

The net expression names, vdd and vss , are used as variables throughout the built-in code in order to allow for supply level flexibility.

Figure 7: the Verilog-AMS netlist for AICM_InhConn

c. Similarly, you may check the netlist for lower-level blocks of I0 and I1 . Combining Action 4 and 5, the variable vdd in inhconn CM takes different values from different design blocks based on the netSet properties given.

Action 6: Check the automatically inserted CMs (AICM)

a. Key in TCL command “scope –aicm –recur –all ” in SimVision Console b. Look at the outcome in Picture and there are totally 10 CMs inserted automatically in this design

(Figure 8). This number can be verified with –iereprot option. Action 7: Exam

a. Can you find out the locations where the 10 CMs are inserted in this design? b. What are the appropriate vsup values individually for those 10 CMs?

netSet property placeholder encompassing lower level leaf cells. The vdd was assigned as vdd33! in I1 while as vdd5! in I0.

Figure 8: The10 CM automatically inserted in this design Action 8: Check the simulation results

a. Click on I0 (AICM_leaf1) in Design Browser, and send A1_in and A1_out signals into waveform viewer.

b. Click on I0.I28 (AICM_leaf3) in Design Browser, and send A_in and A_out signals into waveform viewer.

c. Click on I1 (AICM_leaf1) in Design Browser, and send A1_in and A1_out signals into waveform viewer.

d. Click on I1.I28 (AICM_leaf3) in Design Browser, and send A_in and A_out signals into waveform viewer.

e. Hit run icon to start simulation f. Check the waveforms of those key signals in waveform viewer. See Figure 9.

Figure 9: Final simulation results showing proper voltage levels Figure 9 shows the final simulation results with the red cursor denoting the “high” levels of the pulses. All of the levels are correct and allow proper translation from digital to analog and back again. You may need to click the icons for zooming out fully and fitting data on Y-axis to get the full size of waveforms. Note: To enable cross probing between the schematics and Simvision waves, from Composer do Options->Editor->Cross Selection = on. This will highlight the corresponding signals as you select nets in the schematics.

Chapter 6 Multiple Supply based on Digital Discipli ne

Introductions

Multiple Power Supplies are common practice in mixed-signal design. The challenge occurs when different voltage domain nets cross the analog and digital boundary. In such scenario, connect modules need to know whether the logic 1 should be converted to 2.5V or 1V, or if the electrical 1V should be converted to logic 0 or logic 1. There are two major solutions in AMS simulation to handle multiple power supplies across the A and D boundaries.

• Multiple Supply based on Inherited Connection Please refer to the Chapter of “Multiple Supply based on Inherited Connection”.

• Multiple Supply based on Digital Discipline In this chapter, we demonstrate the Discipline-based CR solution with example. The setup requirements:

1. Discipline-based connect Rule 2. Discipline definition on the design via Composer schematic under the AMS-ADE context.

The advantage of discipline-based solution:

1. No global signal needed in CM as well as in design 2. Support different ports with different supplies in same cell and no leaf schematic cell underneath 3. Support multiple vthes and tr/tf time or any multiple parameter values in the CR

The example database is AMS_disCR.tar.Z

Come to the tutorial directory.

% gunzip –c MultiPowerDis.tar.gz | tar xvf - % cd MultiPowerDis

Set up the environment variable and then start virtuoso.

% source sourceme % virtuoso &

Discipline-based Connect Rule Preparations

There are two ways to prepare discipline-based Conn ect Rule

• Directly create by your own in the text editor.

• Create from AMS-ADE GUI.

Directly create discipline-based and custom CR

You can directly create your own discipline-based CR in text editor. You could reference Cadence built-in non discipline-based CR in the IUS software hierarchy, for example $IUS_HIER/tools/affirma_ams/etc/connect_lib/Connect Rules5.vams To:

• Add disciplines definition • Changing the parameter value accordingly • Keep the default section

In this example, we have created the discipline based CR, my_connectLib/ConnRules_discipline.vams , as shown below. `include "disciplines.vams" connectrules ConnRules_discipline; // Logic_12 discipline section, logic 1 -> 1.2V connect L2E #( .vsup(1.2), .vthi(0.6), .vtlo(0.3), .tr(0.4n ), .tf(0.4n), .tx(0.4n), .tz(0.4n), .rlo(200), .rhi(200), .rx(40), .rz(10M)) i nput logic_12, output electrical; connect E2L #( .vsup(1.2), .vthi(0.6), .vtlo(0.3), .tr(0. 4n)) input electrical, output, logic_12; connect Bidir #( .vsup(1.2), .vthi(0.6), .vtlo(0.3), .tr(0. 4n), .tf(0.4n), .tx(0.4n), .tz(0.4n), .rlo(200), .rhi(200), .rx(40), .rz(10M)) inout electrical, inout logic_12; // default section, logic 1 -> 2.5V connect L2E #( .vsup(2.5), .vthi(1.75), .vtlo(0.75), .tr( 1n), .tf(1n), .tx(1n), .tz(1n), .rlo(200), .rhi(200), .rx(40), .rz(10M)) ; connect E2L #( .vsup(2.5), .vthi(1.75), .vtlo(0.75), .tr( 1n)) ; connect Bidir #( .vsup(2.5), .vthi(1.75), .vtlo(0.75), .tr(1 n), .tf(1n), .tx(1n), .tz(1n), .rlo(200), .rhi(200), .rx(40), .rz(10M)) ; endconnectrules The basic idea in discipline-based connect rule is that we use customer discrete discipline in the digital port to determine the A to D and D to A “currency exchange rate 1.2” and default logic discipline for the “currency exchange rate 2.5” For those digital ports, which have custom discipline “logic_12 ”, we will pass 1.2V to vsup. For example, when input is logic_12 discipline and output is electrical, the logic value “1” will convert to 1.2 V to analog side and any voltage greater than 0.6 convert to logic 1

Create discipline-based and custom CR from AMS-ADE

Action 1: Invoke ADE L and open worklib.foo_top:config

Action 2: In ADE window, click Setup -> Simulator to make sure simulator is “ams” and simulation dir is ./simulation ;

Action 3: In ADE window , Setup -> Connect Rule, the “Select Connect Rules” form appears.

Action 4: In Connect Rule form,

• Turn on “built-in” option • Select rules name “ConnectLib.ConnRules_18V_full_fast” • Click button “Customize”

Customer Built-in Rules form appears. Note, we are going to create our own connect rule based on Cadence built-in Connect Rule.

Action 5: In the form of “Customerize Built-in Rules”

L2E_2 is a logic input and electrical output interface. The direction on corresponding discipline on should be : direction 1 input : logic_12 direction 2 output : electrical

Action 6: Change the Vsup parameter from 1.8 to 1.2. Click “Change” button in the low side GUI.

Keep changing the rest of the parameter value in “Parameters section” if necessary . Action 7: Once you have done the parameter value change for L2E_2 click “Change” button in the

upper side GUI . Action 8: Select E2L_2 , and repeat the same process in action 5-6 to define the discipline and

change parameter values. In this case,

Direction 1 input : electrical Direction 2 output : logic_12 Vsup = 1.2, Vthi = 0.6 Vtlo = 0.3

Action 9: Select Birdir_2, and repeat the same process in action 7-8 to define the discipline and

change parameter value , in this case,

Direction 1 inout : logic_12 Direction 2 inout ; electrical Vsup = 1.2 Vthi = 0.6 Vtlo =0.3

Action 10: In “Customize Built-in” Form, look into the “Connect Module Declaration” and Move the scroll

bar from left to right. Please notice that:

• Parameter values have been changed • Directions and discipline names have been added

Click OK button in this form, and Information form appears.

Click OK button in this form. Action 11: Go back to “Select Connect Rule” form and click “Add “ button

Please notice that, we have create new Connect Rule connectLib.ConnRulles_18V_full_fast1 based on built-in connectLib.ConnRules_18V_full_fast. In order to reuse this new Connect Rule in design, we can copy it to local my_connectLib .

Action 12: With connectLib.ConnRulles_18V_full_fast1 highlighted click button “Copy” in form above.

The new form appears. Choose “File” as the “objective” in Copy to section. Input the file name and connect rule as below. You may use “Browse…” when needed.

File : ./my_connectLib/ConnRules_my_12V.vams Rules Name : ConnRules_12V_discipline Click OK in this form. Note : You can overwrite the existing one in the database by click on YES in prop-up box.

Now we have done the 1.2V discipline-based connect rule (logic_12). Since we don’t have 2.5V built-in connect rule , so that we need to modify existing Cadence built-in 5v connect rule to create a custom 2.5V connect rule. In this example database, we only have 1.2v and 2.5v , so that we can use DEFAULT discipline which is logic and electrical for 2.5V connect rule. That said , we don’t need to define any discipline in the 2.5V Connect rule. Action 13: Go back to “Select Connect Rules” form, turn on “built-in” option and select rules name

“connectLib.ConnRules_18V_full_fast”. Click on “Customize” button, and then “Customize Built-in Rules” form appears.

Action 14: Repeat action 6 -11 except not to do the direction/discipline definition.

The value of parameter form L2E_2 Vsup =2.5 E2L_2 Vsup = 2.5 Vthi = 1.75 Vtlo = 0.75 Birdir Vsup =2.5 Vthi = 1.75 Vtlo = 0.75

Note : We don’t need to add the direction and discipline in this from since we will use default discipline for 2.5V custom connect rule.

Action 15: Repeat action 12-13. “Select Connect Rules” form Copy this customized connect rule to

File :./my_connectLib/ConnRules_my_25V.vams Rule name : ConnRules_25V

Now we have done the Connect Rule preparation via AMS-ADE GUI . Note:

If you’re using “Cellview-based netlister with ncvlog,ncelab,ncsim” mode, you should copy the modified Connect Rules to a library-cell-view (5x) structure. To do this you need

• Choose “Library” as the “objective” in Copy to section. • Choose library and input Rules Name. • Manually compile the Connect Modules. You may refer to compile_CR.cmd as an

example.

Scope-discipline definition via Schematic under AMS -ADE context

Action 16: Invoke the schematic window from ADE->Session->schematic window.

Please Notice that, after we select “ams” simulator in ADE. The “AMS” pull down button shown up in Composer tool bar.

Descend down to instance foo10 and zoom to a clear view of instance foo20

Please notice that

1. Pre_pll_12 analog net -> E2L -> in12 digital port If the voltage value on pre_pll_12 is greater than Vthi = Vsup * 0.5 = 0.6 V , This value should be converted to logic 1 to digital port in12

2. Pre_pll_25 analog net -> E2L -> in25 digital port

If the voltage value in pre_pll_25 is greater than Vthi =Vsup * 0.70= 2.5V * 0.7= 1.75 It should be converted to logic 1 to digital port in25

3. out25 digital port -> L2E -> post_pll_25 analog net

Logic 1 in out25 should be converted to 2.5V to post_pll_25 net

4. out12 digital port -> L2E -> post_pll_12 analog net Logic 1 in out12 should be converted to 1.2V to post_pll_12 analog net

5. Pre_vdd12 analog net -> E2L -> A port in buf_d5 instance If the voltage value in pre_vdd12 is greater than Vthi = Vsup * 0.5 = 0.6V It should be converted to logic 1 to digital port A

6. Z digital port in buf_d5 instance -> L2E -> post_vdd12 analog net

Logic 1 in Z port should be converted to 1.2 V to post_vdd12 net

7. Pre_vdd25 analog net -> E2L -> A port in buf_d6 instance If the voltage value in pre_vdd25 is greater than Vthi = Vsup * 0.7 = 2.5*0.7=1.75 It should be converted to logic 1 to digital port A

8. Z digital port in buf_d6 instance -> L2E -> post_vdd25 analog net Logic 1 in Z port should be converted to 2.5 V to post_vdd25 net. Since we have defined in logic_12 discipline, connect rule. So that for those 1.2V A/D boundaries , we need to define the logic_12 on the port of the instance via Composer

Action 17: In Schematic window, choose AMS -> Default Discipline Selection -> Instance Terminal. Form appears.

Such information window may pops up, too. You may click “Close” to ignore it.

Action 18: In this form , Click “Discipline” button , and new form appears.

Type the logic_12 discipline name in the form and click Add. Keep it highlighted and click “OK”.

Action 19: Go back to “Default Digital Discipline Selection” form. Click on Select Button and go to

schematic to select in12 port in instance foo20.

Action 20: Go back to “Default Digital Discipline Selection” form. Click “Add” button. Now , You should

see this form setup as below.

Repeat the action 4-5 to select following ports and add to the form Instance foo2 port out12 Instance buf_d5 port A

Instance buf_d5 port Z After you have done all the selection, the “Default Digital Discipline Selection” form will look as below.

Action 21: In the form above , select all the instance (as highlighted) and click “Copy To Cell view” So

that we can resume this setup by click “Copy from Cell View” Note : This discipline setup also can be saved/loaded in ADE state. Click “OK” in this form. Now we have done the scope-based discipline setup in design via Schematic.

AMS simulation in ADE

In the previous sections, we have done the preparation of

1. Discipline-based and custom Connect Rule - Directly create in text editor and compiled it into my_connectLib, single connect rule,

my_connectLib.ConnRules_discipline - Create connect rules created by AMS-ADE, my_connectLib.ConnRules_25V &

my_connectLib.ConnRules_12V_discipline

We can either choose ConnRules_discipline

Or ConnRules_25V + ConnRules_12V_discipline

2. Set Scope-based discipline via schematic. This setup also can be saved into ADE state. The

options of this setup in ADE state form is “ Discipline Selection”. We are ready to start AMS simulation in ADE now.

Use single connect Rules ConnRules_discipline

This connect rule has been directly created by text editor and compiled into the my_connectLib Action 22: Go back to ADE window. Ensure simulator is “ams”; simulation dir is ./simulation.

Load state from ./artist_states dir, State name : state_ams_no_setup .

Note: This state only contains the basic setup such as hdl.var file and stop time for tran analysis. Please make sure you are using “OSS-based netlister with irun” Mode in Netlister And Run Options window.

Action 23: In ADE -> Setup -> Connect Rule, in Select Connect Rules form. If

“ConnectLib.ConnRules_18V_full_fast” is selected by default, highlight it and click delete. We will select the connect rule which we have directly created. Enable User-defined (irun). Type ConnRules_discipline as the “Rules Name” and use Browse button to add ./my_connectLib/ConnRules_discipline.vams to the “Connect Rules/Modules Files” section. Click “OK” to confirm it.

Note: There’re two sets of options for user-defined Connect Rules, one is for “ncvlog,

ncelab, nasim” and the other is for “irun”. With the “Cellview-Based Netlister with ncvlog, ncelab, ncsim” mode, every module

should be in library-cell-view (5x) structure. So for a user created Connect Module file, we have to manually compile it into the 5x structure. However, using “OSS Netlister with irun” mode, there’s no 5x structure involved, so the user created Connect Module file can be directly included and compiled in the same way as the other source file. “OSS Netlister with irun” mode provides a much easier way when the user write their Connect Module file themselves.

When “OSS-based Netlister with irun” mode is used, you can still load the Connect Rules created in 5x structure. If you’ve saved the Connect Rules into your local library, you may just load the VerilogAMS file, in your local library, <library>/<cell>/connect/verilog.cams, in case you’re migrating from Cell Based Netlister to OSS Netlister.

Action 24: Ensure Simulation -> Run Options , interactive mode was turned on. Note: We will view simulation result in Simvision, so that the interactive mode is required . Action 25: Kick-off simulation , Simulation -> Netlist and Run. Simvision GUI appears

Action 26: In Simvision GUI, choose Files -> Source command script, and select file name, restore.tcl.sv. Note that in this example , we have pre-saved the signal probing setup in restore.tcl.sv. If you delete it for any reason, please use the one in ./multi_power_dis

Action 27: In Simvision window, Simulation -> Run. Once simulation complete , Select all signal in

waveform and View -> Zoom -> Full Y.

Check with the simulation waveform and the simulation results are CORRECT ! The 1st group signals values are: Pre_pll_12 (0-1.2V) -> in12 (logic 0 -> logic 1) Out12 (logic 0 -> logic 1) -> post_pll_12 (0->1.2V) The 2nd group signals values are : Pre_vdd12 (0->1.2V) -> buf_d5.A ( logic 0 -> logic 1) Buf_d5.Z (logic 0 -> logic 1) -> post_vdd12 (0V -> 1.2V) The 3rd group signals values are: Pre_vdd25 (0->2.5V) -> buf_d6.A ( logic 0 -> logic 1) Buf_d6.Z (logic 0 -> logic 1) -> post_vdd25 (0V-> 2.5V) The group 4th signals values are: Pre_pll_25 (0V->2.5V) -> in25 (logic 0 -> logic 1)

Out25 (logic 0 -> logic 1) -> post_pll_25(0V->2.5V)

Use two connect rules which have been created via A MS-ADE

Action 28: In ADE window , Setup -> Connect Rule. In the “Select Connect Rules” form, turn on the

“Use defined (irun)” option and type the two file names as below with a space in between. You may also select the two connect rule files via Browser ./my_connectLib/ConnRules_my_12V.vams

./my_connectLib/ConnRules_my_25V.vams

Then type in the two Connect Rule names, ConnRules_12V_discipline and ConnRules_25V with a space in between.

Click Ok in the form.

Action 29: Perform action 3-6 in section 4.1. You will see the same simulation result shown in section

4.1 action 6

Chapter 7 Spectre-Turbo Integration in AMSSpectre

Introduction

Spectre Turbo technology is a capability that provides significant performance gain over the baseline Spectre product without accuracy degradation. Spectre Turbo technology enables a set of advanced technologies to give you the best performance for your requirements and given circuit application. Spectre Turbo mode is also available when the spectre simulator is used as analog solver in mixed-signal simulation in AMS Simulator. Spectre Turbo mode is supported in AMS since IUS8.1. AMS benefits a lot from this new technology, offering great performance improvement. To keep the similar speed gain as Spectre Standalone Turbo, AMS side has improved a lot on the performance of Connect Module (so that they won’t deduct the speed). Note: Similarly as Spectre standalone, performance gains are most significant on large transistor level designs. Verilog-A, Verilog-AMS behavioral, VHDL-AMS designs do not apply. The recommended software versions are IC6.1.2ISR with version of 14 and later and IUS8.1 base and later.

Objectives

This tutorial is useful for the existing AMS/ADE users and the SpectreVerilog users who want to use Spectre Turbo technology in AMS to achieve performance improvement. Users who are not familiar with AMS Virtuoso Flow or ADE may refer to Chapter1 and Chapter 2. This tutorial includes below items.

• ADE interface to set Spectre Turbo mode in AMS • Runing the tutorial case.

� Runing the case in Spectre base mode (without Turbo mode) � Runing the case in Spectre Turbo mode (with the Spectre option errpreset=moderate) � Runing the case in Spectre Turbo mode (with the Spectre option errpreset=liberal)

• Result comparison and analyses

Case information

This tutorial example is a mixed-signal 160 MHz PLL circuit that consists of both schematic and Verilog language design units. The schematic contains the following analog components: a VCO, a phase frequency detector (PFD), a charge pump, and a loop filter. The two digital frequency dividers are RTL-level Verilog modules. Key signals are pll_160MHZ_sim.I3.vCNTL The VCO's control voltage signal. pll_160MHZ_sim.CLK_REF A 25 MHz clock reference. pll_160MHZ_sim.CLK_160MHZ The 160 MHz PLL output. pll_160MHZ_sim.I3.VCO_CLK The VCO's output voltage signal.

Setting up the tutorial Action 1: Come to the tutorial directory AMSSpectreTurbo.

% gunzip –c AMSSpectreTurbo.tar.gz | tar xvf - % cd AMSSpectreTurbo

Action 15: Set up the environment variable then start virtuoso.

Runing the case in Spectre base mode Action 16: Open amsPLL.pll_160MHz_sim:config in ADE.

Make sure that ams is set as the simulator. Load state state_base in directory “./artist_states ”. Open Netlister and Run Options window from Simulation menu, and you can see “OSS-based netlister with irun” is chosen.

Action 17: Click Simulation->Netlist and Run to start simulation. AMS Spectre will take about 45m on a

Linux machine with 2.6G CPU and 15G memory. Action 18: After the simulation. A waveform window will come up to show the four key signals.

Action 19: Close the waveform and log file windows. You may save it by doing as below.

cp –r simulation/pll_160MHZ_sim/ams/config/psf/ ams _base ADE interface to set Spectre Turbo mode in AMS Action 20: Close the waveform and log file windows. Open Turbo and Paracitic Reduction option

window by Setup->Turbo/Paracitic Reduction Option..

Please notice there are three sections, Turbo, Override Accuracy (Errpreset) Default, and Parasitics Reduction. By default Turbo option is disabled. In this situation, the Override

Accuracy (Errpreset) Default is set to “Do not overide” with other options grey out. The Parasitics Reduction option is also disabled by default.

Action 21: Turn on the Turbo option, you can choose other options in Override Accuracy (Errpreset)

Default section. The meaning of each choice is listed below. Do not overide : Use the default setting (errpreset=moderate) in the analog circuit. Liberal : Override the errpreset option with errpreset=liberal Moderate : Override the errpreset option with errpreset=moderate Conservative : Override the errpreset option with errpreset=conservative

Action 22: You may also turn on Parasitics Reduction. For circuits with RC Parasitics you can use

Parasitics reduction. You can turn on Parasitics reduction with or without Spectre Turbo mode.

For more information related to Spectre Turbo option and Paracitic Reduction option, please refer to Virtuoso® Spectre Circuit Simulator User Guide

Runing the case in Spectre Turbo mode Action 23: Open Turbo and Paracitic Reduction option window by Setup->Turbo/Paracitic Reduction

Option.... Turn on Turbo mode and set Moderate as the errpreset value as below. Click OK to confirm the settings.

Action 24: Click Simulation->Run to start the simulation. AMS Spectre Tubo mode will take about 6m

on a Linux machine with 2.6G CPU and 15G memory. Action 25: After the simulation. A waveform window will come up to show the four key signals.

cp –r simulation/pll_160MHZ_sim/ams/config/psf/ ams _turbo Action 27: Open Turbo and Paracitic Reduction option window by Setup->Turbo/Paracitic Reduction

Option…. Set Liberal as the errpreset value as below. Click OK to confirm the settings. Action 28: Click Simulation->Run to start the simulation. AMS Spectre Tubo mode with errpreset=liberal

will take about 3m43s on a Linux machine with 2.6G CPU and 15G memory. Action 29: After the simulation. A waveform window will come up to show the four key signals.

cp –r simulation/pll_160MHZ_sim/ams/config/psf/ ams _turbo_liberal Action 31: Open Turbo and Paracitic Reduction option window by Setup->Turbo/Paracitic Reduction

Option…. Enable Paracitic Reduction option. Click OK to confirm the settings. Action 32: Click Simulation->Run to start the simulation. AMS Spectre Tubo mode with errpreset=liberal

will take about 3m42s on a Linux machine with 2.6G CPU and 15G memory. Action 33: After the simulation. A waveform window will come up to show the four key signals.

Action 34: Close the waveform and log file windows. (Optional) Action 35: Open Turbo and Paracitic Reduction option window by Setup->Turbo/Paracitic Reduction

Option…. Disable Turbo option with Paracitic Reduction option enabled. Click OK to confirm the settings.

Action 36: Click Simulation->Run to start the simulation. AMS Spectre with Paracitic Reduction option

will take about 3m42s on a Linux machine with 2.6G CPU and 15G memory.

Result comparison and analyses

Performance Collecting all the results above, here come a summary table. The rows are simulation mode, runtime and speedup (to the base line data).

AMS Spectre (base line)

AMS Spectre Turbo (errpreset=moderate)

AMS Spectre Turbo (errpreset=liberal)

Paracitic Reduction

AMS Spectre

Paracitic Reduction 45m 6m14s 3m43s 3m42s 46m

1 7.2 12.1 12.1 1.0 Note:

• With Turbo mode AMS Spectre (errpreset=moderate) has 7.2X speedup and AMS Spectre

(errpreset=liberal) has 12.1X speedup. • With Paracitic Reduction option on AMS Spectre shows no speed up. This is because this example

includes few RC parasitics. Accuracy Since Spectre Turbo mode in AMS Spectre provides significat performance improvement, you may also want to check the accuracy. In the following section the results from AMS Spectre Turbo mode (errpreset=moderate) and AMS Spectre Turbo mode (errpreset=liberal) will be compared with the result of AMS Spectre base mode. Action 37: Exit ADE and Virtuoso. Invoke WaveScan.

viva & A pop-up window will comes up. Click Continue.

Action 38: Choose File->Open Results, and the Result Browser window comes up.

Action 39: Double click ams_base and result from ams_base directory will be loaded. Double click

tran-tran at the right part of the window. And click the “+” mark to descent into tran-tran->pll_160MHZ->I3.

Action 40: Double click vCNTL and a waveform opens.

Action 41: Change the display mode to Append in the up right coner of the Result Browser window.

Action 42: Repeat Action 25 to Action 27 to open the vCNTL from directory ams_spectre_turbo .

You can see the two signals are overlapped.

Action 43: Hight the signal from directory ams_spectre_turbo and press Delete. Repeat Action 25 to

Action 27 to open the vCNTL from directory ams_spectre_turbo_liberal . You can see the two signals are almost overlapped. But a little wariation can be seen.

(Optional) Action 44: You may repeat Action 25 to Action 27 to check other signals saved and find they follow the

same rule.

Summary

Overall, AMS Spectre Turbo (with or without errpreset=liberal) provides 2X-10X speedup, depending on the the circuit features. Similarly, significant speedup is achieved using the Paracitic Reduction option for designs with large amount of parasitics from extracted views.

Chapter 8 Co-Simulation with AMS Designer and MATLAB®/SIMULINK

Introduction

The high level system concept is specified in the early stages of design. This process is well supported by both concept engineering and system-level simulation tools like MATLAB®/Simulink®. For example, Figure 1 shows the top level schematic for the system-level model of a wireless LAN. The transmitter blocks encode and modulate binary random data and send the OFDM signal to the channel model. This example uses a white Gaussian noise channel model. The receiver blocks demodulate and decode the channel output. Finally, the received bits are compared with the original bit stream to compute the bit error rate. The standard compatible system-level model of the wireless LAN link is assembled using standard SIMULINK library modules. You can use this system-level model as the golden reference for the implementation of the system components. During system-level simulation, the design and simulation of the analog and mixed-signal subsystem is often neglected. Consequently, effects originating from the analog RF parts of transmitter and receiver are not included in the system-level simulation. Note: This example includes an RF circuit and uses the complex base-band modeling approach. However, AMS-MATLAB co-simulation handles all kinds of circuits including base-band designs.

Figure 1: End-To-End System-Level Simulation with Simulink

The analog and mixed signal subsystems are typically designed with an analog and mixed-signal design environment like the Cadence Virtuoso® platform. Cadence Spectre/RF and AMS Designer are used to perform the simulations. Figure 2 shows the RF transmitter module design with filters, up-converting mixer and amplifier included. To speed-up the simulations in the tutorial example, the RF components are modeled in the complex base-band domain using Verilog-A. You can use the same approach to perform equivalent behavioral pass-band and transistor-level simulations.

Figure 2: Behavioral RF Front-End Transmitter Model in the Virtuoso Environment

Typically, in this environment one- and two-tone sinusoidal sources are used as stimuli for RF subsystem analysis during which characteristics of the RF subsystem design (like intercept points, noise figure and corner frequencies) are measured. In most cases it is difficult to use more realistic stimuli like modulated signals. It is also difficult to use the corresponding post-processing required for system performance evaluation. Co-simulation using AMS Designer and MATLAB/Simulink combines the best of system level simulation with analog and RF simulation. Simulink provides large libraries of DSP algorithms for both generating complicated signals and post processing. The Virtuoso Platform provides an optimal design environment for analog/RF and mixed-signal subsystems. AMS Designer is a powerful single-kernel, mixed-signal simulator for transistor level circuits and for all common behavioral languages.

Set Up the Co-Simulation

This tutorial describes co-simulation for two different flows. Each of the two flows supports a different group of users.

• The ADE flow � Run the co-simulation by starting MATLAB/Simulink from ADE. This tutorial is especially easy if you are familiar with ADE.

• The Simulink flow � Run the co-simulation from MATLAB/Simulink without starting ADE. This flow uses the runSimulation script from the ADE flow. Primarily, this flow is for users who do not use the DFII environment or who need to debug within Simulink and do not need the DFII environment to be present.

Cadence recommends using software versions IC612 ISR14 or later (for accessing to the new OSS/irun netlister), IUS81 base or later and MATLAB R14, R2006a and R2007b to run this tutorial. The total time estimated for this tutorial is about 1 hour. Co-simulation is demonstrated using the IEEE 802.11a demo shown in Figure 1. The sample designs are provided in the tutorial database libraries. Assuming that the standalone simulations are working correctly in MATLAB/Simulink and AMS Designer, only three steps are required to set up the co-simulation:

1. Insert and configure the coupler module in the SIMULINK schematic.

2. Insert and configure the corresponding coupler module in the ADE schematic.

3. Run one of the 3 co-simulations. In this tutorial, user will start from the ADE flow and generate the runSimulation script. Then go through Simulink flow. At the end, try the AMS Environment flow.

The steps are described in detail in the following sections.

Modifying the SIMULINK model

Action 1: Change to the following directory:

% gunzip –c MATLABCosimulation.tar.gz | tar xvf - % cd MATLABCosimulation

Action 2: Sourse theSETUP file.

% source SETUP

The SETUP file sets the MATLABPATH and TUT_DIR environment variables Note: If you are using Matlab2006a or below version, please edit the SETUP file and follow the instruction detailed in the SETUP file. Note the matlab2007b directory is created by the script get_matlab2007b . This is done to meet Matlab’s change in R2007b and later versions.

Action 3: Start MATLAB, by typing “matlab &”. If opening SETUP file, it is seen the environment variables for working directory (TUT_DIR) is set.

Action 4: In Matlab command window, input “open SimCouplerLib.mdl ” to open the library SimCouplerLib. (Note if you use the Matlab GUI to open the matlab/ SimCouplerLib.mdl ” the Matlab current Directory path will be changed to AMS-MATLAB/matlab. Reset Matlab current Directory path to AMS-MATLAB, from the Matlab GUI.) This library contains the coupler module and several examples. To open an example, double click on its blue symbol. You can insert the coupler module in any SIMULINK design by dragging and dropping from the AMS Designer – Simulink Cosimulation Library.

Figure 3: The Simulink Library for Co-Simulation

Note: Before you proceed with the tutorial steps, check your MATLAB release number (R13 or R14 or R2007b or R2008a). If you use MATLAB R13 open the SimCouplerLib_r13 by double clicking the yellow box. The coupling technology in both releases is equivalent, however, the MATLAB demo and the standard SIMULINK libraries are slightly different. Please note that the R14 designs are not backward compatible with R13.

Action 5: Double click on the first green box labeled Step 1 . The end-to-end design for a wireless LAN transmission system opens (see Figure 1). This design contains the main DSP algorithms of a wireless LAN 802.11a physical layer for the transmitter and the receiver chains. It generates a standard compliant 802.11a signal and implements the related post-processing algorithms.

Action 6: In the window displaying the LAN transmission system schematic, click Simulation – Start . A spectrum scope and a scatter diagram will come up. The minor deviations in the scatter diagram originated from the noisy channel. Look at the bit error rate (BER) display. In the testbench window, the bit error rate information appears at the output of the Error Rate Calculation block.. Observe that the bit error rate is zero

Action 7: You might want to double click on the AWGN block and increase the noise by changing the parameter signal to noise ratio SNR (dB) to 13 .

Action 8: In the testbench window, double-click the AWGN block. The Function Block Parameters form appears. In the SNR (dB) field, change the signal-to-noise ratio from 20 to 13

Start the simulation again. Click Simulation – Start to start the simulation again. The scatter diagram is now distorted and after some seconds bit errors do occur. The final plot should look like Figure 4. Now change the SNR back to 20 .

Figure 4: SIMULINK Library for Co-Simulation

The following actions will be used to set up the co-simulation step by step. There is a complete setup in Tutorial Step 2 which can be used as a reference.

Action 9: We want to include the analog transmitter RF-front end within this system testbench. Therefore, a coupler module is inserted between OFDM Transmitter and AWGN channel . Drag and drop the SimulinkCoupler block (the block that contains “cadence” located on top of the green boxes) into the testbench and place the block at the top right corner.

Action 10: Double click the SimulinkCoupler block to open the Function Block Parameters window. Set input pins to 3 and output pins to 2 . Even though the 3rd input pin is not necessary in this case, it illustrates how signals flow and how the coupler is created in DFII.

In addition, in order to make it look better, user can resize the SimulinkCoupler and fit the signal lines (see Figure 5).

Action 11: This SIMULINK testbench uses framed signals. In the Function Block Parameters window, change the parameter Frame mode to framed . Click OK to close the form and to update the SimulinkCoupler with the correct number of pins.

Action 12: In the testbench window, switch on the signal dimension display by selecting Format – Port/Signal Displays - Signal Dimensions to see details on the framed signals used. The other SimulinkCoupler parameters are described in later sections.

Action 13: The example uses complex valued signals. Before the signal is transmitted to AMS Designer it is necessary to split complex signals into the real and imaginary parts. SIMULINK provides a converter for this purpose. Select View – Simulink library to display the library browser.

Double click on Math Operations. The desired converters are located at the bottom right corner in this library.

Action 14: Drag-and-drop the Complex to Real-Imag block from the Library window to the testbench window and place it on the left side of the SimulinkCoupler block.

Action 15: Drag-and-drop the Real-Imag to Complex block from the Library window to the testbench window and place it on the right side of the SimulinkCoupler block.

Action 16: Rewire the testbench schematic to accomodate the new blocks.

Action 17: Since the analog/RF subsystem will eventually change the signal level, insert an ideal gain block at the output of the coupler block, to adapt the signal level to the properties of the digital base-band receiver. The gain block is in the Math Operations library. Switch the gain level to 0.04 by double clicking on the placed ‘Gain’ block and setting Gain to 0.04.

Action 18: Delete the wire between the OFDM Transmitter and the AWGN channel, by right clicking on the wire and choosing cut, and connecting the signals as shown in Figure 5 (or use the rectangular green Tutorial Step 2 button). To re-wire the design move the mouse pointer over the module pin. It changes to a cross. Press the left mouse button, move the cursor to the destination pin and release the button.

Action 19: The SIMULINK model is ready for co-simulation. It should look similar to Figure 5 below. All other information about frame size and sampling time is detected automatically within the SIMULINK model. Please note another Spectrum Scope is added to compare the signal before and after the SimulinkCoupler. To add it, user can copy and paste the existing scope block, click right button of mouse on it and choose Format—Flip Block to flip it, then connect it.

Figure 5: Testbench with Additional Modules for Co-Simulation

Action 20: To verify the stop time of the Simulink simulation, do the following: In the testbench window, choose Simulation - Configuration Parameters. The Configuration Parameters form appears. Set the stop time of the SIMULINK simulation to 1000e-6 by clicking Simulation – Configuration Parameters as shown in Figure 6.

Figure 6: Simulink Simulation Settings

All necessary modifications on the MATLAB side are complete. You can use your modified Simulink schematic, or you can use the Step 2 version later in this tutorial.

Modifying the Virtuoso Schematic

NOTE: If AMS-Matlab option (-amsmatlab ) is disabled by default, before every action you should first enable this in ADE, Simulation – Options – AMS Simulator – PLI section, by turning on “Dynamically load VPI libraries for AMS/MATLAB”.

Or a easier way is to add below line into your .cdsinit. envSetVal( "ams.elabOpts" "amsMatlab" `boolean t) Action 1: Start the IC design framework II by opening the Command Interpreter Window (CIW) by

entering virtuoso & at the prompt in the top AMS-MATLAB directory.

% virtuoso &

Action 2: In the command interpreter window (CIW), Click File – Open to open the schematic. In the Open File form, click AMSDcouple for Library Name, click tb_ieee_802_11a_demo_template for Cell Name, click config for View Name, click edit for Mode and click OK. (You can also click Browse and navigate to AMSDcouple/tb_ieee_802_11a_demo_template/config )

Figure 7: Open the Schematic Template with Virtuoso

The Schematic window contains all the blocks in the analog/RF transmitter chain.

• A driver module to scale the coupler output

• The RF transmitter model (see Figure 2)

• A simple line termination using resistors (see Figure 8) The only missing parts are

• A signal source for an 802.11a system

• The related post-processing algorithms These parts are provided by the MATLAB/Simulink design.

Figure 8: AMS Designer Schematic Template

Note : The AMSDcouple library includes additional examples like tb_sine, tb_sine100, tb_event_fixed, etc. All examples have corresponding designs in MATLAB/Simulink. You can work with these examples to explore co-simulation. The IC5141 USR4 release and later releases support two ways to create a coupler in the Schematic window.

• The Fixed Cell Coupler method (the recommended method) – Create the specific couplers that you need and save them in your library. You determine the number of coupler pins before you generate the coupler. This coupler is simple and works for all three flows. Use this method to create a coupler instance specifically for your design.

• The simulinkCoupler method – Use the simulinkCoupler found in the analogLib library. The simulinkCoupler is a Pcell coupler. You can change its pins at any time. The simulinkCoupler is flexible and can get verilogAMS code generated automatically in ADE. In addition, ADE also allows user to generate the verilogAMS module for simulinkCouple and modify it manually. These features will be described in a later section of this tutorial.

The steps of running co-simulation with simulinkCoupler and Fixed Cell Coupler in ADE are different. The following sections will walk through both methods. Note: The CouplerToSimulink coupler from the AMSDcouple library and used in the old release version of this tutorial is phased out. Since the IC5141 USR4 release on, only the Fixed Cell Coupler and the simulinkCoupler is supported and used in co-simulation.

Action 3: In the Schematic window, choose Launch –Mixed Signal Options – AMS. The AMS menu is added to the menu bar. Click on AMS – Simulink® Coupler Creation . The Fixed Cell Coupler Creation form opens (see Figure 9). In this form, you would input 2 for input pins

and 3 for output pins and then click Generate Fixed Coupler . However, this is not needed in this case, as a Fixed Coupler with 2 inputs and 3 outputs has already been created in the library and is ready to be used. Close the form.

Figure 9: Add a Coupler Module to the Schematic

Action 4: In the Schematic window, click Create – Instance and click Browse to select cell coupler_2_3_a from the AMSDcouple library. Click this instance and choose Edit – Properties – Object to examine all the parameters for this module (see Figure 10).

Figure 10: Object Properties for the Coupler Module

Action 5: Connect the coupler module with the other instances using Create – Wire (see Figure 11) or you can close this schematic and open tb_ieee_802_11a_demo which contains the coupler module already wired.

Figure 11: Wire the Coupler Module

Action 6: The schematic is complete and you can save it using File – Check and Save . The entire signal flow through both the MATLAB/Simulink and Cadence environments is shown in.

Figure 12: Signal Flow through the MATLAB/Simulink and Virtuoso Environments

Notice that each sink (coupler input pin) acts as signal source (output pin) in the other environment. The signal flows into the 3 input pins on the Simulink schematic, out the 3 output pins on the Virtuoso schematic, through the design in Virtuoso, into the 2 input pins on the Virtuoso schematic and out the 2 output pins on the Simulink schematic, and through the rest of the design on the Simulink schematic.

Action 7: In the Simulink window, close MATLAB/Simulink by clicking File – Exit MATLAB. You are ready to run the co-simulation in ADE.

Section 1: Run Co-Simulation in ADE with the Fixed Cell Coupler Action 1: In the Virtuoso Schematic window, choose Lauch – ADE L to invoke ADE L. The Simulation

window (ADE) opens.

Action 2: Look at the middle of the bar under the menus in the ADE Simulation window and make sure the simulator is set to ams(Spectre). The simulator is set in the .cdsinit file in the AMS-MATLAB directory.

Action 3: The ADE setup for co-simulation is quite simple. Click Analysis – Choose and in the Choosing Analyses form type 1m as Stop Time. Click OK.

Action 4: Choose Simulation – Options – AMSSimulator . In fact in this case the simulator should be pre-set. Then review the options and leave them as default.

Action 5: From the “Simulation > Netlister and Run Options”, select the OSS-based netlister with irun.

Action 6: In the Simulation window, choose Variables – Copy from Cellview to obtain the variable names from the schematic. There are two global design variables for the gain and compression point of the RF power amplifier. The compression point parameter is a measurement of the amplifier’s linearity/nonlinearity. The smaller the number the larger is the amplifier’s nonlinearity. By double clicking the variable names at the bottom left corner of the Simulation window. The Editing Design Variables form opens. Set the gain variable, GAIN_PA, to 35 and set the compression point variable, CP_PA, to 24.

Action 7: Start MATLAB before you start the AMS Designer simulation. Click Setup – Matlab/Simulink – Start , the Setup MATLAB form opens. Select before AMS starts for the value of Start MATLAB to ungrey the fields. When this value is chosen, MATLAB will start automatically when the simulation is run. The MATLAB start command field will contain matlab . Note in the MATLAB startup directory field is set as current working directory by default. In the MATLAB design name, type tutorial2r14. And in the AMS delay to allow MATLAB initialization field leave the default value of 10. In this case the AMS simulator will start after 10 seconds which allows 10 seconds for MATLAB to initialize. Sometimes you may extend the initialization field values to 30s for examples if 10s were too short.

Action 8: Finally, the form looks like Figure 13. Click OK. In the popped up Start MATLAB before AMS starts form, click Close.

Figure 13: The Start MATLAB Form You are ready to run cosimulation from ADE.

About Starting MATLAB/Simulink and AMS

In the Setup MATLAB form, “no” is the default choice for the “Start MATLAB” field. This choice is useful if, after filling out the form, you decide not to run Matlab and do not want to clear out your form fields. The “before AMS starts” choice means that you want MATLAB to start automatically before the AMS simulation starts. In order for co-simulation to start and run properly, the MATLAB/Simulink simulation must already be running when the AMS simulation starts. When you use the Setup MATLAB form and you use “before AMS starts” and “AMS delay to allow MATLAB initialization” to coordinate simulation start up times, the connection between the simulators is automatically set up. Use “now” to start MATLAB immediately. This is similar to the third flow that runs the AMS simulator and environment separate from the MATLAB/Simulink simulation.

Action 9: In the ADE Simulation window, set the simulation time to 1m (tran analysis), the same as it is in Simulink. Choose Simulation – Netlist and Run or click on the green traffic light button on the right side of the Simulation window. After a few seconds, MATLAB starts and Simulink design shows up. After 10 seconds from the time when MATLAB/Simulink started, AMS simulation launches and when ncsim starts, the connection is set up and co-simulation starts.

Note: Only simulink window for the design will open and no MATLAB command window. Besides, there will have the log file of MATALB and Ncsim displaying in the screen. The log files can also be viewed by choosing Simulation – Output Log

Action 10: After the co-simulation is done, review the MATLAB/Simulink output (see Figures 14 and 15). Bit errors do not occur with these settings, however, the input spectrum and output spectrum are different due to the non-ideal RF transmitter chain.

Action 11: To rerun the co-simulation, it needs no change for setup at all. After you modify the design you can simply choose Simulation – Netlist and Run or click on the green traffic light button on the right side of ADE window.

Figure 14: Simulation Results as Spectral Plots

Figure 15: Constellation Diagram PA_CP = 24

Action 12: In the ADE Simulation window, double-click on the CP_PA variable name and change the compression point value of the transmitter model (parameter CP_PA) from 24 to 18.

Action 13: In Simulink design window, click File – Exit Matlab to prepare the next part of tutorial.

Both MATLAB/Simulink and ADE Are Open

In case user wants to leverage the full functionalities of MATLAB, it is also possible to start MATLAB is ADE and then run the co-simulation by start 2 simulations separately. Now both MATLAB and ADE are open. This is the scenario if you click “now ” in Figure 13. If user chooses “now ” in action 7, then the use model will be the same as following.

Action 14: Click Setup – Matlab/Simulink – Start , Change from “before AMS starts ” to “now ”, note a button labelled Start shows up and the AMS delay to allow MATLAB initialization field is greyed out.

Action 15: Make sure all the inputs of other fields are unchanged from previous run. Click on Start button at the lower right corner

Action 16: It is seen MATLAB command window will open and as well we the Simulink design window. Then in the test bench window (see Figure 5) click Simulation – Start. It will be seen in the MATALB command window that Simulink simulation is waiting for 120s for Ncsim simulation to start.

Action 17: In the ADE Simulation window, Click Simulation – Netlist and Run (or click on the green traffic light button on the right side of ADE) to start the AMS simulation. After Nncsim starts, the connection will be setup and the co-simulation starts. Wait until the co-simulation finishes.

Action 18: Review the MATLAB output (see Figures 14, 16 and 17). Figure 16 and Figure 17 show the simulation results. The constellation diagram gets worse due to the larger amplifier nonlinearity. However, the overall system behavior is still reasonable. Some bit errors do occur during the simulation.

Figure 16: Constellation Diagram PA_CP = 18

Figure 17: BER Measurement PA_CP = 18

Action 19: To rerun the simulation, you need to start Simulink and ADE again separately.

Section 2: Run Co-Simulation in ADE with simulinkCo upler

The following steps introduce the flow using the simulinkCoupler block from the analogLib library and will introduce the auto-generation of verilogAMS module for simulinkCoupler.

Action 20: In the ADE Schematic window (see Figure 11), remove the coupler_2_3_a coupler block.

Action 21: Click Create – Instance , click Browse to select cell simulinkCoupler from the analogLib library. Set the number of input pins as 2 and the number of output pins as 3 and place the simulinkCoupler in the space created when you removed coupler_2_3_a . The schematic should look similar to Figure 11.

Action 22: The simulinkCoupler is a Pcell that has no fixed number for pins. This makes the simulinkCoupler block flexible since you can change the number of pins to fit different designs. Click Setup – MATLAB/Simulink – Create pcell coupler file , the Create Pcell Coupler File form opens. By default, “Auto-create pcell while netlisting” is checked and the other options are greyed out. This means user needs to do nothing and ADE will generate the verilogAMS module automatically. The other options will be mentioned later.

Action 23: Follow the steps in Action 16 through Action 18 to run the co-simulation. The results look similar to Figures 14, 16 and 17.

Action 24: In case user wants to view and modify the verilogAMS module for simulinkCoupler, open Create Pcell Coupler File form Click Setup – MATLAB/Simulink – Create pcell coupler file by uncheck “Auto-create pcell while netlisting”.

Action 25: In the the Create Pcell Coupler File form, click Select, follow the prompt at the left bottom of CIW window, “Select Simulink® Pcell coupler block”, click on coupler modules in the Schematic window. The form looks like Figure 18.

Figure 18: Use the SimulinkCoupler from AnalogLib

Action 26: After selecting the coupler module, click Generate Verilog-AMS to create the Pcell coupler module source file. Look for a message in the CIW, you will see “Generated Verilog-AMS file successfully”. To examine the Pcell source file, click Edit Verilog-AMS to review the source file. Click OK to exit.

Action 27: Follow the steps in Action 15 through Action 17 to run the co-simulation. The results look similar to Figures 14, 16 and 17.

Action 28: In CIW form, click File – Exit to close virtuoso.

Section 3: Run Co-Simulation in MATLAB/Simulink

Action 1: The runSimulation script was generated in the simulation directory while you were running Section 1 or 2 in this tutorial. From a UNIX terminal, use a text editor to open the runSimulation script ./simulation/tb_ieee_802_11a_demo_template/ams/conf ig/netlist/runSimulation and review the contents. It uses the irun command.

Action 2: In the MATLAB testbench window, move the cursor over the SimulinkCoupler module, double click on it and the Function Block Parameter window will appear. Check “Show advanced options” to display all the advanced options.

Action 3: Change the value of “Use AMS Designer run script” to Name/Host (default is no). The “AMS Designer run script” and “Hostname” fields are available. Note the default value is ./runSimuation which is just an example. You will change it to launch_runSim_irun. The launch_runSim_irun CSH script will change the directoy to “./simulation/tb_ieee_802_11a_demo_template/ams/con fig/netlist and it will call the runSimulation” in the “AMS Designer run script” field (Figure 19).

Note: The launch_runSim_irun script is the following: #!/bin/csh -f echo "Matlab Current directory path is:" pwd setenv RUN_DIR ./simulation/tb_ieee_802_11a_demo/am s/config/netlist cd $RUN_DIR echo "irun will start, from this directory:"

pwd echo "We launch runSimulation" runSimulation

Figure 19: Input Run script

Note: For “Use AMS Desinger run script”, there are 3 selections. They are no, Name/Host and Command to be executed “as is” . In this tutorial we will not use the 3rd selection. It is to provide a place that user can input commands and they will be excuted as is. For example, running MATLAB in Windows and AMSD in Linux, user can type below command: rsh 1921.168.5.5 /home/test/AMS-MATLAB/simulation/tb_ieee_802_11a_demo/ams/config/n etlist/runSimulation & To succeed your simulation, the Matlab Current Directory path needs to be set to the AMS-MATLAB subdirectory path.

Action 4: Click OK to exit the window.

Action 5: Click Simulation – Start to start the co-simulation.

Action 6: After a few seconds the co-simulation starts. During the pause, ncvlog and ncelab start. Note: If the simulation does not start, check if run script is valid and can run in command line

Action 7: Look at Matlab command window while waiting the cosimulation to start, search for the info as below. It is seen the launching command is printed for user’s reference. User can modify this an put in Command to be executed “as is” field according to his own needs.

Cosimulation Interface Launching the command: './launch_runSim_irun > AMSS imulink.log 2>&1 &' block 'tutorial2r14/SimulinkCoupler': Waiting for incoming connection on port 5023, timeo ut: 120 sec ... After the simulation finishes, output is similar to Figures 14, 16 and 17. The Ncsim log will be displayed in the editor after the simulation and also saved in run directory named as AMSSimulink.log

Summary

The three sections in this tutorial demonstrate step-by-step how to set up and run AMS-Simulink co-simulation.

• Run co-simulation following one of the two flows

• Characterize, optimize, and verify your design in one or both design environments

o MATLAB/Simulink

o Cadence Virtuoso/AMS Designer

• Rerun the simulation in the same sequence as before and notice the effects of your design changes. Note in ADE and Simulink flow user can rerun the simulation with one button click

• Repeat the sequence until the design meets specifications

• To restart the tutorial, type ./CLEAN in the command line./

• AMS/Simulink cosimulation supports multiple platforms: Linux, Solaris, HP, IBM and windows. Due to the widely usage, it is common to run cosimulation in Matlab in Windows. This is mentioned briefly in section 3 already. Please note for this usage, SETUP file may not work. User needs to add the path of coupler in IUS and working directory in Matlab manually. Below are examples that user needs to input into Matlab. User can change the path accordingly:

addpath('/grid/cadence/install/ius57/lnx86/tools/a ffirma_ams/etc/matlab'); addpath('/home/cadence/tutorial/AMS-MATLAB/matlab' ); addpath('/home/cadence/tutorial/AMS-MATLAB/matlab/ tutorial');

Learn More about the Co-Simulation Interface

The following predefined demos explain in more detail the main features of Simulink-AMS Designer co-simulation. For detailed step-by-step instructions on how to use the tools, see the previous sections.

Frame-Based and Unframed Signals

Simulink provides different testbenches for framed and unframed data.

• From virtuoso, open 'tb_sine' config.

• Switch on the AMS plug-in and invoke SimVision.

• Optionally select signals to display.

Unframed Coupling

— Open 'sine_tb.mdl' from the SIMULINK library.

— Review the parameters of the SIMULINK coupler module. It supports event driven and fixed rate synchronization.

— Start with event based simulation.

o The parameter Frame mode must be set to unframed.

o The parameter Frame size is greyed out for this mode.

o The coupler module sends data to AMS Designer after each change of its input signal.

o In SimVision you see the sine wave exactly as generated by the sources.

o The sampling time of all sine sources in SIMULINK is set to 1e-6.

— You can change the sampling time of one SIMULINK sine source and view the changes in synchronization.

— After finishing this simulation you can try fixed rate synchronization.

o Specify a Sample Time of 10e-6 to sample the signal at 100 kHz. The sampling theorem is satisfied since the highest sine frequency is 20 kHz.

— Start the SIMULINK simulation.

— Reinvoke AMS Designer/ncsim. Use Simulation – Reinvoke Simulator, no changes needed on the AMS Designer side.

— Start the simulation.

— The simulation runs faster.

— View the sampled signals in SimVision and SIMULINK.

— You can run this with different values of Sample Time, that is, reduce Sample Tme to 1e-6 for more accurate sampling.

Framed Coupling

Some telecommunication simulations work with a data stream driven simulation. Some DSP algorithms process a data frame instead of single samples. So SIMULINK provides framed signals. To increase the simulation performance, cosimulation also supports framed signals.

— Open sine_tb_frame.mdl from the SIMULINK library.

— Review the parameters of the SIMULINK coupler module.

o Specify the number of input and output ports and the socket port.

o Set the parameter Frame mode must to framed.

— The frame length is taken from the connected input signals in SIMULINK.

— Reinvoke the simulator if you have simulated the unframed example before.

— Run simulation. The signals are displayed in SIMULINK.

— Now change the frame size:

o Edit each of the three Buffer modules in SIMULINK, set frame size to 10.

o Re-invoke the AMS simulator and start the simulation.

o The result is the same. The simulation takes a bit more time.

— Try this for several frame sizes. Note that the frame length is currently limited to 10000.

Event Based and Fixed Rate Simulation

Fixed Rate synchronization might be useful if the model contains signals with different (high and low) sampling rates and the interface is only connected to a low sampling rate block. If the signals exchanged between AMS Designer and SIMULINK are at the lower rates, fixed rate synchronization with a dedicated Sample time can improve the simulation performance significantly. This is demonstrated in the following example:

— Open the SIMULINK testbench "event_fixed_tb".

— The model contains a sine wave generator which produces a sine of 2 kHz sampled at 10 us. The sine wave signal is transmitted to the AMS Designer.

— The pulse generator produces a high frequent pulse with a period of 100 ns. (100 times faster than the sampling rate of the sine wave.)

— Open the AMS Designer config "tb_event_fixed".

— AMS Designer adds the two signals from SIMULINK.

— First start the simulation in event based mode. Double click on the coupler module in the SIMULINK schematic to check the settings. The sampling time should be set to -1 to enable the event based mode. Run the simulation.

— In SimVision select Signal_1, Signal_2 and Sum to display.

— Start the AMS Designer simulation.

— The simulation takes about 30 seconds. The sine waves displayed in SIMULINK and SimVision. You can mark the computed data points.

— After finishing the run, go back to SIMULINK and change the sync mode in the Coupler module to fixed rate with a Sample time of 0.00001 (equal to the sampling rate of the sine).

— Run the SIMULINK simulation again.

— Go back to SimVision and re-invoke the simulator.

— Start the AMS Designer simulation. The simulation finishes after about 5 seconds. The high frequent pulse no longer influences data exchange between the simulators.

— You can resimulate this with different Sample times.

— In other examples where the sampling rate changes over time, the event based synchronization is probably the better choice. Decide carefully what synchronization scheme fits best with your design.

Note: If you look at the computed signal points in the SimVision waveform plot, you will see, that the values are not necessarily updated at equidistant points even if you choose fixed rate in the SIMULINK coupler. AMS Designer’s analog solver controls the timing of these data points and can introduce more simulation points if necessary between two synchronization points.

Using the Coupler Module in Loops

This testbench demonstrates how to use coupling in feedback loops. The testbench is very simple: SIMULINK generates two sine waves and transmits them to AMS Designer and AMS Designer feeds one of the signals back to SIMULINK. The second signal is unused. Simulink compares the feed-thru sine wave with the original signal. The coupler has additional input and output pins and there is another feedback loop inside AMS Designer. In SIMULINK, a constant of 0.1 is added to the coupler output and the signal is connected to the third coupler input. After each cycle the signal is increased by 0.1. You can see this in the SIMULINK or AMS Designer window. At the beginning of simulation, the signal is initialized to zero.

— Open the 'tb_sine_loop' config from the icfb.

— Switch on the AMS plug-in and invoke SimVision.

— Select the signal 'Loop' to display.

— Decide which example to use: unframed or framed.

Unframed Coupling

— Open 'loop_tb.mdl' from the SIMULINK library.

— Review the parameter of the SIMULINK block.

— Start the SIMULINK simulation first, then start the AMS Designer simulation.

— After each cycle, increase the signal by 0.1.

— A ramp is displayed in the plot windows.

— Notice how the two sine waves match.

— Switch the coupling block to fixed port rate and view the changes on the ramp and the two sine waves.

Framed Coupling

— Open 'loop_tb_frame.mdl' from the SIMULINK library.

— Reinvoke the AMS simulator.

— Start the SIMULINK simulation first, then start the AMS Designer simulation.

— The simulation result now looks somewhat difficult:

o The signal increases once for each frame.

o The signal values are equal within each frame. The signal has steps, depending on the frame size.

o The frame size in the feedback loop path equals the frame size of the sine waves (defined in the buffer blocks).

o Change the frame size and view the changes in the results. Note: Handle feedback loops in cosimulation very carefully. In this example you can see that the behavior of feedback signals can vary depending on different simulation settings. Review your design very carefully around possible loops and decide how to integrate the loops in the cosimulation. With the default settings,

SIMULINK displays a warning: Warning: Block diagram 'loop_tb' contains 1 algebra ic loop(s) . To see more details about the loops use the command line SIMULINK debugger by typing "sldebug loop_tb" in the MATLAB command window. To eliminate this message, set the Algebraic loop option in the Diagnostics page of the Simulation Parameters Form to "None".

Troubleshooting

The coupler module prints messages to both the MATLAB main window and to the AMS Designer/ncsim console. The UNIX version of the SIMULINK coupler block also writes messages to the logfile SimCoupler.log in the MATLAB run directory. These messages can help to detect the reason of errors.

Problem: SIMULINK shows error message like: "Illegal rate transition found involving block 'sine_tb_frame/SimCoupler' at input port 2. A rate transition block must be inserted between the two blocks." SIMULINK generates this error by default only for the multi-tasking solver mode of its fixed-step solver when signals with different sample rates are connected to the same block. In framed mode the cosimulation produces wrong results when signals with different sample rates are connected to the SIMULINK coupler module. It is recommended to turn on this error message for single-task mode also by setting the property Simulation – Configuration Parameters – Diagnostics – Sample Time – Single task rate transition to error. All models in the AMS Designer/Simulink Cosimulation Library that use framed signals have this option turned on.

Problem: SIMULINK shows an error message like: "Error reported by S-function 'SimCoupler' in block 'sine_tb_frame/SimCoupler': could not determi ne block sample rate, try using the fixed step solver" The SIMULINK coupler module with parameter Frame mode set to framed can only be used in models with fixed sample rates. The variable step solver can be used as long as the resulting sample rate at the coupler module is fixed. Turn on sample time coloring (Format – Sample time colors) to inspect the sample rates in your model. Black and gray indicate a variable sample time and are not allowed in framed mode. Also, different sample times are not allowed at the coupler module (see the previous Problem).

Problem: SimVision does not come up, NC elaboration failed Execute AMS – Design Prep and start elaboration/simulation again. Check for error messages in the output window or in the log files. If in ADE flow, Simvision should not show up unless it is specified to run in interactive mode.

Problem: The cosimulation cannot be established After Simulation – Run AMS Designer/ncsim terminates immediately and the AMS Designer/ncsim console closes. Go to the dedicated AMS run directory and review the ncsim.log file. Coupler module messages display at the end of this file: ncsim> run initializing couple module 'tb_sine.I6' ERROR: connecting to socket failed, sockfd=16, host=localhost, port=5023 errno=111: Connection refused ERROR: can't create new connection to 'localhost' at port 5023 (Master simulator not running?) The coupler module cannot connect to MATLAB. Different reasons are possible:

1. The SIMULINK simulation is not started or has stopped due to the timeout settings. Try again. Start the SIMULINK simulation before the AMS Designer/ncsim simulation. Wait for the MATLAB initialization phase to finish before starting AMS Designer. Do not wait longer than the timeout before starting AMS Designer.

2. The simulators use different socket ports. Check the settings in MATLAB and the Virtuoso Schematic. If there are differences, change the port number in SIMULINK or in the Virtuoso Schematic.

3. MATLAB does not run on the specified host. Check the parameter Hostname of the coupler module in the Virtuoso Schematic. By default it is set to localhost.

4. The socket port may be used by another service. Change to another port at both sides.

Problem: The simulation ends before the desired tim e. The co-simulation terminates if one of the simulators has reached its simulation end time. On the AMS Designer side this setting is configured in the ADE Choosing Analyses form or the Hierarchy Editor at the Tran Analysis page of the AMS simulator options. In SIMULINK use the Simulation – Simulation Parameters form to change the simulation end time.

Problem: When using framed signals the SIMULINK cou pler module reports the error "lookup ports failed". The maximum frame size is actually limited to 10000 for each input signal. If your application requires a larger frame size, contact Cadence for support. Always ensure that all connected signals have the same frame size.

Problem: Matlab complains Invalid MEX-file: Error in 'tutorial2r14/SimulinkCoupler': Initialization commands cannot be evaluated. MATLAB error message: Error while obtaining sizes from MEX S-function 'SimCoupler' in 'tutorial2r14/SimulinkCoupler'. MATLAB error message: Invalid MEX-file '/CDS/CDS/lnx86/IUS62_hot/tools/affirma_ams/etc/matlab/SimCoupler.mexglx': /CDS/CDS/lnx86/IUS62_hot/tools/affirma_ams/etc/matlab/SimCoupler.mexglx: symbol mxCreateDoubleMatrix, version libmx.INTERNAL not defined in file libmx.so with link time reference. Always ensure that you are using a Matlab version compatible with the SimCoupler version. Cadence provides in the IUS installation (ncroot`/tools/affirma_ams/etc/matlab/) multiple SimCoupler.mexglx' Matlab version. Using MATLABPATH setenv variable you provide to Matlab the right coupler path.

Problem: Matlab 2008a does not start from ADE. MATLAB 7.6 (R2008a) was built using glibc 2.3.6, and this causes the warning to be displayed on machines that run glibc 2.3.4 (RHEL 4.x is an example case where this can happen) ---------------------------------------------------------------------------- Warning: glibc 2.3.4 - Unsupported version glibc 2.3.6 - MATLAB built using this version ---------------------------------------------------------------------------- -> Your configuration APPEARS to be too OLD to run this MATLAB program! ---------------------------------------------------------------------------- For system requirements consult http://www.mathworks.com ... *************************************************************************** -> Best to quit by pressing <return> at the next prompt ... Do you still want to try to continue? (y/[n]) > y However, MATLAB 7.6 (R2008a) is expected to work with glibc 2.3.4 the same way it works with glibc 2.3.6 To avoid receiving the warning when you start MATLAB, replace the file $MATLABROOT/bin/util/oscheck.sh with a new one:

See Mathworks URL : http://www.mathworks.com/support/solutions/data/1-5YTXCE.html?solution=1-5YTXCE

Chapter 9 Using runams Command

Introduction

The runams command allows you to run AMS Designer from the command line or from a script using the same default values used by the AMS ADE with the OSS/irun flow. This command includes options for netlisting the design and running simulations with irun. OCEAN allows you to run AMS, doing the same thing you can in GUI mode, however, runams has a far simpler use model. With runams, you simply type “runams ” followed by a list of command line options that will perform some action on the other command line arguments such as netlist or simulate a specified lib:cell:view. The runams command is similar to the amsdesigner command that allows you to run AMS Designer from the command line or from a script using the same default values used by the HED Plugin AMS environment with the Cellview based three-step flow. The runams command is available in IC 5.1.41 ISR 135, IC 6.1.3 ISR 12, and later versions.

runams Command Syntax

Usage: runams [-help | -h | -version | -V | -W] | runams -lib <libName> -cell <cellName> -view <viewName> \ action_options [setup_options] [netlisting_ options] [simulation_options] Note:

runams does not read the .cdsinit file . Therefore, specify any custom SKILL netlisting procedures your design uses in a .simrc file, which will be loaded automatically during netlisting. Simulation related options can be added to the .cdsenv file and loaded by runams using the -cdsenv option.

For options that require a file path to be specified:

- If single quotes are used around <filePath>, then relative paths (using ~ or .) will be expanded, but an environment variable ($envvar) will not be expanded. In order to make the runSimulation file more portable, use single quotes around file paths so that the environment variables in the file paths are not expanded in the runSimulation file.

- If single quotes are not used around <filePath>, relative paths and environment variables will be expanded. A relative path is resolved with respect to the invocation directory.

Case Information

This tutorial example has two inverters, one with schematic view (INV_sch) and the other with verilogams view (INV_vams). The power level is set using the design variable lVDD. The period of the input pulse is set using the design variable Prd.

Setting up the Tutorial

Action 45: Ensure that the following software is in your system path:

• Either IC 5.1.41 ISR 138, IC 6.1.3 ISR 14, or a later version. • IUS 9.2 or later version.

Action 46: In a terminal window, copy the runams.tar.gz file to your directory, gunzip the file, untar the file and then change to the directory runams.

% cp runams.tar.gz <your work directory> % gtar –zxf runams.tar.gz % cd runams

% source SETUP

Using the runams Command

Example 1: Using runams with an ADE state file

If you have saved your AMS Designer settings in ADE to a state file, you can use the setup in the state file with runams . This allows you to quickly setup and run simulations using the runams command. Action 47: Open the run_state script file in a text editor.

This file contains the following options for running the runams command using an existing ADE state file:

runams -lib testLib -cell top -view config \ -netlist \ -simulate \ -rundir run1 \ -state artist_states:state_ams \ -log ./logs/run_state.log Where: action_options: -netlist -simulate

setup_options: -lib amsPLL -cell pll_160MHZ_sim -view config -run dir run1 -state artist_states:state_ams -log ./logs/sma rt_run.log -state option loads state files from a specific ADE state directory or a cellview state. -state <stateLoadDir:stateName[:simulatorName ]> To load a state file from an ADE state directory, specify the directory and state name. The path used to find the state file will be: <stateLoadDir>/<libName>/<cellName>/<simulatorName> /<stateName> . -state <stateViewName> To load an ADE cellview state, specify the name of the cellview state. The cellview state is found in the libName/cellName/stateViewName directory. Ensure that <stateViewName> is an ams state. Note: When you load state files to run runams , all signals on the top level, instead of what you have set in the state file, will be saved. For more information, see the runams Limitations section in this document.

Action 48: Run the run_state script. The following text will be displayed above the netlist log.

$ ./run_state <COPYRIGHT information>

Starting runams... Run date: Thu Jul 2 20:53:44 2009 Run time options used: -lib testLib -cell top -view config -netlist increm ental -simulate batch -rundir /grid/cic/nsdpe-tc/data/ruilin/AVUM/CDBA/AVUM/runams/run1 -state artist_states:state_ams -wavetool simvision -solver spectre -log ./logs/smart_run.log Current directory: '/grid/cic/nsdpe-tc/data/ruilin/AVUM/CDBA/AVUM/runams' Using run directory: '/grid/cic/nsdpe-tc/data/ruilin/AVUM/CDBA/AVUM/runams/run1' Running si to netlist testLib.top:config ...

Themessages above are from runams. It describes the runams options used, present working directory and run directory. All the messages that are displayed will be written to a log file named run_state.log because the runams command in the run_state file uses the -log ./logs/run_state.log option.

Action 49: Check the netlist and results directories. You will find that the netlist and psf directories are

the same as those created by ADE.

Action 50: Check the waveform. You can use SimVision in the IUS installation directory.

Example 2: Using runams with control files

You may want to modify some netlist or simulation options without creating a new state file using the ADE GUI, or want use a control file created by the ADE GUI or by hand. You can do this using runams options. Examples of such customization are given below. Action 51: Open the run_control script in a text editor and check the runams options and input files.

runams -lib testLib -cell top -view config \ -netlist \ -simulate \ -rundir run2 \ -analogcontrol ./setup/amsControl.scs \ -modelfile ${TUT_DIR}/models/spectre/gpdk09 0.scs'(NN)' \ -cdsglobals './setup/cds_globals.vams' \ -connectrules userDef:ConnRules_25V_full_fast:connectLib/ConnRule s_25V_full_fast.vams \ -tclinput ./setup/probe.tcl \ -log ./logs/run_control.log Where:

-analogcontrol ./setup/amsControl.scs: Specifies the analog control file to use. This file contains the Spectre, UltraSim or aps control statements, such as the tran, info, or options statements. In this example, the tran analysis time is set to errpreset=liberal.

-connectrules userDef:ConnRules_25V_full_fast:./connectLib/ConnRu les_25V_full_fast.vams :

Specifies the connect rule to use. For built-in connect rules, the syntax is: -connectrules [libName.]<ruleName>[:viewName] For user-defined connect rules, the syntax is: -connectrules userDef:<[ruleName][:fileName]>

-cdsglobals'./setup/cds_globals.vams':

Specifies a file that includes the cds_globals module definition. In this case the design variable is set to Prd = 400n, lVDD = 2.5 .

The cds_globals module declares design variables and global signals. The specified <fileName> will be sent to irun. Note that the cds_globals.vams file that is created during netlisting will not be sent to irun. The global signals and design variables can also be set using the -globalsignals and -desvar options.

-modelfile ${TUT_DIR}/models/spectre/gpdk090.scs'(N N)':

Specifies the analog model files and section name. If you have more than one model file to include, use a colon to separate the list of files with model section names enclosed in parentheses, such as -modelfile file1:file2’(NN)’ .

-tclinput ./setup/probe.tcl Specifies a TCL file to use. Note: The database directory in the database statement should be either absolute or relative to the created netlist directory. In this tutorial the database directory is set as ../psf.

Action 52: Run the run_control script and open the waveform. Note that the frequency changes to

half of the previous value and the output out1 changes to 2.5V .

Example 3: Using the -netlisteropts option

You can use the –netlisteropts option to specify options for the OSS-based AMS netlister. -netlisteropts <options>

The following netlister options can be set using the -netlisteropts option: amsPortConnectionByNameOrOrder= name | order Specifies how to print the port connection (default: name). useSpectreInfo Specifies the list of views that are to be netlisted as spectre. This is equivalent to the Netlist using Use Spectre CDF simInfo option on the Netlister Options form. Specify the netlister options as a colon-separated list of name-value pairs enclosed in single quotes, such as: -netlisteropts 'amsPortConnectionByNameOrOrder=name :useSpectreInfo=spectre veriloga spice' Action 53: Open the run_netlist script in a text editor and check the runams options. Note that this

script works with a different configuration named config_CB .

runams -lib testLib -cell top -view config_CB \ -netlist \ -rundir run3 \ -netlisteropts 'amsPortConnectionByNameOrOrder=name:useSpectreInfo =spectre veriloga spice' \ -log ./logs/run_netlist.log

Action 54: Run the run_netlist script. You will find the following messages from the screen and the

log file at ./logs/netlist.log .

INFO (179) : The following cells will be netlisted without using the spectre CDF simulation information, because they ar e bound to view symbol: *** Library - testLib Cell - inv *** *** Library - gpdk090 Cell - nmos2v *** *** Library - gpdk090 Cell - pmos2v *** *** Library - analogLib Cell - vsour ce *** To use the spectre CDF simulation information, do o ne of the following: - Open your configuration in Hierarchy Editor and r eplace "symbol" with "spectre" in the view list and stop list. - Choose Simulation->Options->Netlister and add "sy mbol" in the "Netlist using spectre CDF simInfo" field.

This message means that the symbol views in your design are treated as digital. However, in this design we expected symbol views to be treated as analog. So we need to follow the instructions in the INFO (179) message.

Action 55: First back up your netlist file.

cp ./run3/netlist/netlist.vams netlist_d

Action 56: Open the netlist_run script in a text editor and add symbol to useSpectreInfo as shown below:

-netlisteropts 'amsPortConnectionByNameOrOrder=name:useSpectreInfo =spectre veriloga spice symbol'

Action 57: Run the netlist_run script again. The INFO (179) message is not displayed this time.

Compare the two netlist files using the command:

vimdiff netlist_d run3/netlist/netlist.vams netlist_d : pmos2v M0 ( .S(cdsNet1), .G(A), .D(Y), .B(cdsNet1) ); nmos2v M1 ( .S(cdsNet0), .B(cdsNet0), .G(A), .D(Y) ); run3/netlist/netlist.vams: gpdk090_pmos2v #(.w("(150n)"), .l(280n), .as(72.6f) , .ad(72.6f), .ps(1.01u), .pd(1.01u), .m("(1)*(1)")) (* integer passed_mfactor = "m"; *) M0 (Y, A, cdsNet1, cdsNet1); gpdk090_nmos2v #(.w("(150n)"), .l(280n), .as(72.6f) , .ad(72.6f), .ps(1.01u), .pd(1.01u), .m("(1)*(1)")) (* integer passed_mfactor = "m"; *) M1 (Y, A, cdsNet0, cdsNet0); As you can see, after we set useSpectreInfo=spectre veriloga spice symbol in -netlisteropts option, the primitives with symbol view are treated as analog.

runams advanced applications

One of the most important advantages of runams is that users do not need to invoke the ADE GUI, which to a large extent enables automatic simulation of the GUI case. You need to:

Create a simple script, maybe just using csh or Perl to - call runams with different options/parameters - change the rundir for each run

Create a runObjFile to plot families of curves Plot the results using Viva.

The three examples below show such advanced applications.

Parametric analysis -- change design parameter Corners analysis -- changes model sections Verification -- changes the 'view' for different configs.

Example 4: Parametric analysis using runams

In this example, the design parameter, Prd is changed to five values to observe the different results. Action 58: Change directory to ./Advanced_app . Open the C-shell script RUN_param. Check the

comments for each part and have a brief understanding of what each part does.

# create runObjFile header …… # MAIN FUNCTION: create runams script & run simulat ion …… # run runams # write runObjFile …… # Check waves in Viva

Here in this example, values of Prd is written in param.list . The RUN_param script will take each parameter value from param.list and run runams with each value. At the same time runObjFile is created in run_dirs so that after simulation, you may do family plot of the waves from each run.

Action 59: Run the RUN_param script.

./RUN_param As you may see in the terminal, each step is carried on and runams is called five times to run netlisting and simulation. You may also check run_200n, run_250n, run_300n, run_350n, run_400n for option details. *********************************** * Parametric Analysis * *********************************** Removing run_dirs ... Done! creating runObjFile header ... Done! Parametric Analysis Begins! … … Running ... Parameter: 200n …… Done! Parameter: 200n Running ... Parameter: 250n …… Done! Parameter: 250n Running ... Parameter: 300n …… Done! Parameter: 300n Running ... Parameter: 350n …… Done! Parameter: 350n Running ... Parameter: 400n …… Done! Parameter: 400n Parametric Analysis Done! Viva is being invoked to show the result waves ...

Action 60: After the simulation Viva is invoked. Expand tran-tran->top , right-click net3 and plot it.

You’ll see the family plot of five waves. The frequency of vsource changes from 200n to 400n with a step of 50n .

Example 5: Corner analysis using runams

In this example, the model section is changed to five values (NN, SS, SF, FS, FF ) to observe the different results. Action 61: Open the C-shell script RUN_corner . This script does similar actions as the previous one.

This time model section is written in corner.list . The RUN_corner script will take each value from corner.list and run runams with each value. At the same time runObjFile is created in run_dirs so that after simulation, you may do family plot of the waves from each run.

Action 62: Run the RUN_corner script.

./RUN_corner As you may see in the terminal, each step is carried on and runams is called five times to run netlisting and simulation. You may also check run_NN, run_SS, run_SF, ./run_FS, ./run_FF to see the option details.

*********************************** * Corner Analysis * *********************************** Removing run_dirs ... Done! Corner Analysis Begins!

Parametric Analysis Begins! … … Running ... Model Section: NN …… Done! Model Section: NN Running ... Model Section: SS …… Done! Model Section: SS Running ... Model Section: SF …… Done! Model Section: SF Running ... Model Section: FS …… Done! Model Section: FS Running ... Model Section: FF …… Done! Model Section: FF Corner Analysis Done! Viva is being invoked to show the result waves ...

You’ll see the family plot of five waves. Zoom in at an edge, and you may find the different waves with different model sections.

Example 6: Verification using runams

When you verify the design function, you may want to try your case with serveral views for a cell or even several configs for the whole design. In this example, the three design configs are used for each run.

Action 64: Open the C-shell script RUN_verification . This script does similar actions as the previous one.

This time the design configurations in config.list . The RUN_verification script will take each value in config.list and run runams with each configuration. At the same time runObjFile is created in run_dirs so that after simulation, you may do family plot of the waves from each run.

In the three different configs, instance INV_vams uses three different views. config inst (testLib.top:schematic).INV_vams binding :veri logams config1 inst (testLib.top:schematic).INV_vams binding :veri logams1 config2 inst (testLib.top:schematic).INV_vams binding :veri loga

Action 65: Run the RUN_verification script.

./RUN_corner As you may see in the terminal, each step is carried on and runams is called three times to run netlisting and simulation. You may also check run_config, run_config1, run_config2 to see the option details.

*********************************** * Verification Flow * *********************************** Removing run_dirs ... Done! Verification Begins! Running ... Configuration: config …… Done! Configuration: config Running ... Configuration: config1 …… Done! Configuration: config1 Running ... Configuration: config2 …… Done! Configuration: config2 Verification Done! Viva is being invoked to show the result waves ...

You’ll see the family plot of three waves.

Summary

The runams command provides a convenient way to run AMS Designer from the command line or from a script, using the same default values used by AMS in ADE using the OSS+irun flow. This provides a simple way to run command line regressions using the same setup (state files) that was used in the ADE GUI.

runams Limitations

The runams command currently does not support the following options that are supported by the

amsdesigner command: -hier_info -saveconfig -savenetlistfiles -append_log -readmode -snapshot -liblist <libraryListSpecification> -viewlist <viewListSpecification> -cdsglobals overwriteedits | retainedits -inh_viewlist <lib> <cell> <view> {view} -sourcefile <library> <cell> <filePath> -verilogfile <library> <cell> <viewToUse> <filePath > -compile -elaborate -simulate tcl

Currently, you cannot specify particular signals to be saved by loading the state files. When you load state files to run runams, all signals on the top level will be saved. See CCR685803 for more information. Workaround: Add –tclinput <TCL_file> option to runams command. Set needed probe in the <TCL_file> . Probe settings from –tclinput has precedence.

Chapter 10 Designing with Text-On-Top and Using the Scope Navigator with AMS Designer

Beginning with the IC 5.1.41 USR5 release, you can create and simulate text-on-top designs using AMS Designer together with ADE. Using the new scope navigator and the Cadence hierarchy editor, you can select output signals from both text modules and schematics for plotting.

You can create a text-on-top design by importing a text module for the top-level design into the Virtuoso®

design environment and creating an associated config view so that you can load and simulate this design in the analog design environment (ADE). The estimated time to complete this tutorial is about 20 minutes.

Test Case Information

The PLL for this tutorial is a text-on-top design (Verilog-AMS). Beneath it is a mix of text modules and schematics. The key signals are up_n , down, vco_in , and fb . The directory/file structure for this test case is as follows: . |-- README # README fil e |-- SETUP # Environment setup fil e |-- PLL_top.vams # Text module (Verilog-AMS) for t op-level desig n |-- cds.lib # Defines librarie s |-- clean # Clean-up scrip t |-- hdl.var # Defines work library and view mappi ng |-- model # Directory containing model file s |-- artist_states # Saved states for AD E `-- PLL_lib # Design librar y

Setting up the Tutorial

Before running the tutorial, do the following: Action 1: Prepare the database and come into the directory TextOnTop .

% gunzip –c TextOnTop.tar.gz | tar xvf - % cd TextOnTop

Action 2: At the prompt, source the SETUP file as follows:

% source SETUP

This file sets the CDIR environment variable to the current directory. Action 3: Run the Cadence virtuoso workbench as follows:

% virtuoso &

The command interpreter window (CIW) appears. You are ready to begin.

Creating a Text-on-Top Design

You can create the top-level text module using any of the following methods:

Verilog In Note: See the Verilog In for Virtuoso Design Environment User Guide for more information.

In the schematic editor, choose Design – Create Cellview – From Cellview and use the Cellview From Cellview form that appears to specify the appropriate module type Note: See the Virtuoso Schematic Editor User Guide for more information.

In the command interpreter window (CIW) or the Library Manager, choose File – New Cellview to open a text editor window so that you can create the appropriate module type

There are several ways to create the text description for the top-level design. This tutorial demonstrates how to create a text-on-top design by creating a new text cellview of the appropriate type from the Library Manager. You can use this method whether you plan to netlist your design using the cellview-based netlister or the OSS-based netlister. To open the Library Manager, start in the command interpreter window and choose Tools – Library Manager. This method is what we will use for this tutorial.

To create the text-on-top design for this tutorial, do the following: Action 4: In the CIW, choose Tools – Library Manager.

The Library Manager appears.

Action 5: In the Library column, select PLL_lib.

Choose File – New – Cellview.

The Create New File form appears. In the Type drop-down combo box, select VerilogAMSText. The View Name will change to verilogams and the Tool will change to VerilogAMS-Editor.

Action 6: In the Cell Name field, type the name of the top-level cell (PLL_top ). Click OK.

An editing window appears and you can input the top-level text module description.

Action 7: Import the content of $CDIR/PLL_top.vams , replacing the skeleton content shown above.

For example, if you are using vi , you can type :r $CDIR/PLL_top.vams to import this content. Be sure to remove any left-over lines from the skeleton file.

Action 8: Save and exit the file. For example, if you are using vi , you can hold down the Shift key and

type ZZ or simply type :wq .

A prompt appears asking whether you want to create a symbol view.

Action 9: Click No.

PLL_top appears in the Cell column in the Library Manager window. The top cell view for this tutorial design consists of a Verilog-AMS description of a top-level PLL block (PLL_top.vams ): //Verilog-AMS HDL for "PLL_lib", "PLL_top" "verilog ams" `include "constants.vams" `include "disciplines.vams"

module PLL_top (in_ref,vco_in ); input in_ref ; output vco_in ; VCO1 (* integer library_binding = "PLL_lib"; *) I2 ( .VCO_out( fb ), .VCO_in( vco_in ) ); LF (* integer library_binding = "PLL_lib"; *) I1 ( .LF_out( vco_in ), .up_n( up_n ), .down( down ) ); PD (* integer library_binding = "PLL_lib"; *) I4 ( .up_n( up_n ), .down( down ), .fb( fb ), .res_n( res_n ), .ref( in_ref ) ); vsource #(.wave({0,0.0,20n,0,21n,5}), .type("pwl")) (* integer library_binding = "analogLib"; *) V1 ( res_n, cds_globals.\gnd! ); vsource #(.delay(100n), .type("pulse"), .period(200 n), .width(100n), .val0(0.0), .rise(1n), .val1(5), .fall(1n)) (* integer library_binding = "analogLib"; *) V0 ( in_ref, cds_globals.\gnd! ); vsource #(.type("dc"), .dc(5)) (* integer library_binding = "analogLib"; *) I82 ( cds_globals.\vdd! , cds_globals.\gnd! ); endmodule

Creating a config View

To create a config view of the PLL_top cell for this tutorial, do the following: Action 10: In the Library Manager, choose File – New – Cellview.

The Create New File form appears with all the information from the previous cellview we created (PLL_top, verilogams, VerilogAMS-Editor).

Action 11: In the Typel drop-down combo box, select config. Then View Name changes to config and

the default of Open with changes to Hierarch Editor

Action 12: Click OK. config appears in the View column in the Library Manager window. The New Configuration form appears.

Action 13: Choose the verilogams view appears in the View field.

Action 14: On the New Configuration form, click Use Template. The Use Template form appears. Action 15: From the drop-down combo box in the Name field, select AMS.

Action 16: Click OK.

The New Configuration form now looks like this:

Action 17: Click OK.

All of the design instances and their cell bindings appear in the Cadence hierarchy editor.

Action 18: Choose View – Update to check and save the new configuration. An Update prompt

appears.

Action 19: Click OK to save the new config view.

Setting Up the Design in ADE

To set up the design in ADE, do the following:

Action 20: In the CIW, choose Tools – ADE L – Simulation. The Virtuoso®

Analog Design Environment appears.

Action 21: Choose Setup – Design. The Choosing Design form appears.

Action 22: Select the following, then click OK:

� Library Name: PLL_lib � Cell Name: PLL_top � View Name: config � Open Mode: edit

After you click OK, the design information appears in the ADE window:

Simulator: ams(Spectre) appears on the low right coner of the window.

Action 23: Choose Session – Load State. The Loading State form appears.

In the State Name box, select ams_state.

Action 24: Click OK. State information, including analysis setup information (in the Analyses box),

appears in the ADE window:

Verifying Netlister and Run Options, Connect Rules and Model File

To verify the netlister and run option, the connect rules, and the model file for this tutorial example, do the following: Action 25: In ADE, choose Simulation – Netlister and Run Options. The Netlister And Run Options form

appears.

Here we use OSS-based netlister with irun flow.

Action 26: To verify the connect rules for this tutorial, choose Setup – Connect Rules. The Select Connect Rules form appears.

You can verify that the Built-in connect rule, ConnRules_5V_full from connectLib, appears in the List of Connect Rules Used in Simulation table. When you are done with this form, you can click Cancel to close it.

Action 27: To verify the model file for this tutorial, choose Setup – Model Libraries. The Model Library

Setup form appears.

You can verify that the model file for this example is $CDIR/models/basicMos.scs . When you are done with this form, you can click Cancel to close it.

Using the Scope Navigator to Select Output Signals

Action 28: To use the scope navigator in the Cadence hierarchy editor to select output signals from text modules, do the following: Choose Outputs – To Be plotted – Select From HED. The Cadence hierarchy editor appears.

Action 29: If the Table View appears in hierarchy editor, choose View – Tree. Action 30: Select I4 (PLL_lib PD verilog). This is a text module. The Select Net/Term to Save/Plot form

appears.

The Save or plot selection is net. The Choose net/term selection is ref. /I4/ref appears in the Enter net/term field.

Action 31: Click View.

The corresponding Verilog source file appears in a text window. You can review the module and close the text window when you are finished.

Action 32: On the Select Net/Term to Save/Plot form, click Apply. The path and net name appear in the

Outputs box in ADE.

Action 33: Return to the Cadence hierarchy editor and select (PLL_lib PLL_top verilogams). This is the

top-level design instance, which is a Verilog-AMS text module. Action 34: On the Select Net/Term to Save/Plot form, select fb in the Choose net/term drop-down

combo box.

/fb appears in the Enter net/term field.

Action 35: Click OK. The path and net name appear in the Outputs box in ADE.

Using the scope navigator, you can plot both voltage and current. To plot current, select term instead of net for Save or plot on the Select Net/Term to Save/Plot form.

Selecting Nets on a Schematic

To select nets on a schematic, do the following: Action 36: In ADE, choose Outputs – To Be plotted – Select On Schematic. All the cells in the design

appear on a Choose form.

Action 37: Select I1 ("PLL_lib" "LF" "schematic").

Action 38: Click OK. The schematic appears in a Schematic Editing window.

Action 39: On the schematic, select nets up_n, down, and LF_out. Action 40: Press Esc to exit signal-selection mode.

All five outputs now appear in the Outputs box in ADE:

Action 41: In ADE, choose Simulation – Netlist and Run.

Action 42: The simulation log file appears in a separate window. Wait a few minutes for the simulation to finish.

A Graph Window appears.

Action 43: To view results in strip plots, choose Graph – Split Current Strips.

Summary

Upon completing this tutorial, you have explored how to create and simulate a text-on-top design using AMS and ADE. You have used OSS-based netlister with irun flow. You have seen how to plot signals in text modules using the scope navigator.

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