Post on 08-Mar-2023
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 1
DEVICES AND COMMUNICATION
BUSES FOR DEVICES NETWORK–
Lesson-13: Timing And Counting
Devices, WDTs and Real Time
Clocks
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 2
1. Timer Devices
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 3
Timer
• A device, which counts the input at
regular interval (T) using clock pulses
at its input.
• The counts increment on each pulse
• Store in a register, called count register
• Output bits (in a count register or at the
output pins) for the present counts.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 4
Evaluation of Time
• The counts multiplied by the interval
T give the time.
• The (present counts initial counts)
T interval gives the time interval
between two instances when present
count bits are read and initial counts
were read or set.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 5
Timer
Has an input pin (or a control bit in
control register) for resetting it for all
count bits = 0s.
Has an output pin (or a status bit in
status register) for output when all
count bits = 0s after reaching the
maximum value, which also means
after timeout or overflow.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 6
Counter
• A device, which counts the input due to the events at irregular or regular intervals.
• The counts gives the number of input events or pulses since it was last read.
• Has a register to enable read of present counts
• Functions as timer when counting regular interval clock pulses
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 7
Counter
Has an input pin (or a control bit in
control register) for resetting it for all
count bits = 0s.
Has an output pin (or a status bit in
status register) for output when all
count bits = 0s after reaching the
maximum value, which also means
after timeout or overflow.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 8
2. Counting Devices
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 9
Timer or Counter Interrupt
When a timer or counter becomes 0x00
or 0x0000 after 0xFF or 0xFFFF
(maximum value), it can generate an
‘interrupt’, or an output ‘Time-Out’ or
set a status bit ‘TOV’
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 10
Timer cum Counting Device
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 11
Free running Counter (Blind running
Counter)
• A counting device may be a free running
(blind counting) device giving overflow
interrupts at fixed intervals
• A pre-scalar for the clock input pulses to fix
the intervals
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 12
Free Running Counter
It is useful
for action or initiating chain of actions,
processor interrupts at the preset instances
noting the instances of occurrences of the events
processor interrupts for requesting the processor to use the capturing of counts at the input instance
comparing of counts on the events for future actions
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 13
Free running Timer cum Blind Counting
Device
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 14
3. Free Running Counting Devices
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 15
Free running (blind counting) device Many
Applications Based on
comparing the count (instance) with the one preloaded in a compare register [an additional register for defining an instance for an action]
capturing counts (instance) in an additional register on an input event. [An addition input pin for sensing an event and saving the counts at the instance of event and taking action.]
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 16
Free running (Blind Counts) input OC-
enable pin (or a control bit in control
register)
• For enabling an output when all count bits at free running count = preloaded counts in the compare register.
• At that instance a status bit or output pin also sets in and an interrupt ‘OCINT’ of processor can occur for event of comparison equality.
• Generates alarm or processor interrupts at the preset times or after preset interval from another event
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 17
Free running (Blind Counts) input capture
-enable pin (or a control bit in control
register) for Instance of Event Capture
• A register for capturing the counts on
an instance of an input (0 to 1 or 1 to 0
or toggling) transition
A status bit can also sets in and
processor interrupt can occur for the
capture event
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 18
Free running (Blind Counts) Pre-scaling
• Prescalar can be programmed as p = 1, 2,
4, 8, 16, 32, .. by programming a prescaler
register.
•Prescalar divides the input pulses as per
the programmed value of p.
• Count interval = p T interval
• T = clock pulses period, clock
frequency = T 1
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 19
Free running (Blind Counts) Overflow
• It has an output pin (or a status bit in
status register) for output when all
count bits = 0s after reaching the
maximum value, which also means
after timeout or overflow
• Free running n-bit counter overflows
after p 2n T interval
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 20
4. Uses of Timer/Counter Related
Devices
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 21
Uses of a timer device
Real Time Clock Ticks (System Heart Beats). [Real time clock is a clock, which, once the system starts, does not stop and can't be reset and its count value can't be reloaded. Real time endlessly flows and never returns back!] Real Time Clock is set for ticks using prescaling bits (or rate set bits) in appropriate control registers.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 22
Uses of a timer device
Initiating an event after a preset delay
time. Delay is as per count value
loaded.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 23
Uses of a timer device
Initiating an event (or a pair of events
or a chain of events) after a
comparison(s) with between the pre-set
time(s) with counted value(s). [It is
similar to a preset alarm(s).].
A preset time is loaded in a Compare
Register. [It is similar to presetting an
alarm].
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 24
Uses of a timer device
Capturing the count value at the timer
on an event. The information of time
(instance of the event) is thus stored at
the capture register.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 25
Uses of a timer device
Finding the time interval between two
events. Counts are captured at each
event in capture register(s) and read.
The intervals are thus found out.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 26
Uses of a timer device
Wait for a message from a queue or
mailbox or semaphore for a preset time
when using RTOS. There is a A
predefined waiting period is done
before RTOS lets a task run.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 27
Uses of a timer device
Watchdog timer. It resets the system
after a defined time.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 28
Uses of a timer device
Baud or Bit Rate Control for serial
communication on a line or network.
Timer timeout interrupts define the
time of each baud
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 29
Uses of a timer device
Input pulse counting when using a
timer, which is ticked by giving non-
periodic inputs instead of the clock
inputs. The timer acts as a counter if, in
place of clock inputs, the inputs are
given to the timer for each instance to
be counted.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 30
Uses of a timer device
Scheduling of various tasks
A chain of software-timers interrupt
and RTOS uses these interrupts to
schedule the tasks.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 31
Uses of a timer device
Time slicing of various tasks. A multitasking or multi-programmed operating system presents the illusion that multiple tasks or programs are running simultaneously by switching between programs very rapidly, for example, after every 16.6 ms.
Process known as a context switch. [RTOS switches after preset time-delay from one running task to the next. task. Each task can therefore run in predefined slots of time]
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 32
Uses of a timer device
Time division multiplexing (TDM)
Timer device used for multiplexing the input from a number of channels.
Each channel input allotted a distinct and fixed-time slot to get a TDM output. [For example, multiple telephone calls are the inputs and TDM device generates the TDM output for launching it into the optical fiber.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 33
Timer States
Reset State (initial count = 0)
Overrun State (several counts received after
reaching the overflow state)
Overflow State (count received to make count =
0 after reaching the maximum count)
Present State (counting or idle or before start or
after overflow or overrun)
Initial Load State (initial count loaded)
Running (Active) or Stop (Blocked) state
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 34
Timer States
Finished (Done) state (stopped after a preset
time interval or timeout)
Service Routine Execution enable/disable State
(enabled after timeout or overflow)
Auto Re-Load enabled/disabled State (enabled
count = initial count after the timeout)
Load enabled/disabled State (reset count = initial
count after the timeout)
Reset enabled/disabled State (enabled resetting
of count = 0 by an input)
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 35
5. Software Timers (Interrupts
Generating Devices at Preset
Software Interuction defined
Intervals)
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 36
Software timer
A timer which executes a software after the counts increment by certain pre-defined value and interrupt from to a system and executes a set of software instructions (ISR)
The software timer which generates interrupt on overflow of count-value or on finishing value of the count variable and runs a set of instructions (ISR).
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 37
6. System Clock
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 38
System clock
• A hardware-timing device programmed to
tick at constant intervals T.
• An interrupt at each tick
• A chain of interrupts thus occur at periodic
intervals.
• T is as per a preset count value
• The interrupts are called system clock
interrupts, when used to control the schedules
and timings in the system
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 39
SWT and System clock
• System clock has fixed program to tick at
constant intervals T.
• SWTs have fixed but programmable to tick
at intervals T.
• An interrupt at each tick in both
• The interrupts called system clock and SWT
interrupts, respectively
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 40
7. Watch Dog Times
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 41
Watchdog timer
A timing device such that it is set for a preset time interval and an event must occur during that interval else the device will generate the timeout signal on failure to get that event in the watched time interval.
On that event, the watchdog timer is disabled for generation of timeout or reset
Timeout may result in processor starting a service routine or start from beginning
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 42
Example
• Assume that we anticipate that a set of tasks must finish in 100 ms interval.
• The watchdog timer is disabled and stopped by the program instruction in case the tasks finish within 100 ms interval.
• In case task does not finish (not disabled by a program instruction), watchdog timer generates interrupts after 100 ms and executes a routine, which is programmed to run because there is failure of finishing the task in anticipated interval.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 43
Watchdog timer application
• An application in mobile phone is that
display is off in case no GUI
interaction takes place within a
watched time interval.
• The interval is usually set at 15 s, 20 s,
25 s, 30 s in mobile phone.
• Mobile thus saves the power
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 44
Watchdog timer application
• An application in temperature controller
• If controller takes no action to switch off the current within preset watched time interval, the current switched off
• Warning signal raised as indication of controller failure
• Failure to switch off current may burst a boiler in which water is heated.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 45
Provisioning of watchdog timer
A software task can also be
programmed as a watchdog timer
Microcontroller may also provide for a
watchdog timer.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 46
8. Real Time Clock
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 47
Real Time Clock (RTC)
A clock based on the interrupts at
preset intervals
An interrupt service routine executes
on each timeout (overflow) of this
clock
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 48
Real Time Clock (RTC)
A timing device once started never
resets or never reloaded with another
value
. Once it is set, it is not modified later.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 49
RTC
Used in a system to save the time and
date.
Used in a system to initiate return of
control to the system (OS) after the set
system clock period
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 50
RTC Application
• Assume that a hardware timer of an RTC
for calendar is programmed to interrupt
after every 5.15 ms (=1 day period/ 224)
• Assume each tick (interrupt) a service
routine runs and updates at a memory
location. Within one day (86400 s) there
will be 224 ticks, the memory location will
reach 0x000000 after reaching the
maximum value 0xFFFFFF.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 51
RTC with 5.5 ms tick
• Within 256 days there will be 232 ticks,
the memory location will reach
0x00000000 after reaching the
maximum value 0xFFFFFFFF.
• A battery is used to protect the
memory for long period
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 52
RTC for implementing a software timer
A hardware 16-bit timer ticks from processor clock after 0.5 s. It will overflow and execute an overflow interrupt service routine after 215 s = 32.768 ms.
The interrupt service routine can generate a port bit output after every time it runs or can call a software routine or send a message for a task. If n = 30, the RTC initiated software will run every 30 32.768 ms, which is close to 1 s.
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 53
Unmask and reset to mask of real time
interrupt
RTI is set to unmask and reset to mask the real time interrupt locally.
If RTI and I bits permit the interrupt request for real time, the microcontroller fetches the lower and higher bytes of the interrupt servicing routine address from the addresses 0xFFF0 (higher byte) and 0xFFF1 (lower byte)
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 54
Summary
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 55
We learnt
• Timer
• Counter
• Free running counter or blind counting counter
• Out-compare register and actions on comparisons of counts preset and reached
• Input-capture register and actions on capture of counts reached
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 56
We learnt
• Timer applications
• States of a Timer
• Software timer
• Timer gets input on system timer
interrupts
• Software timers enable the system to
have more number of timing devices
from one hardware timer
•
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 57
We learnt
• A watchdog timer number of applications
• It is timing device such that it is set for a
preset time interval and an event must occur
during that interval and program instuction
must disable the watchdog timer else the
device will generate on the timeout signal
an interrupt for the failure to get that event
in the watched time interval
2015 Chapter-5 L11: "Embedded Systems - Architecture, Programming and Design",
Raj Kamal, Publs.: McGraw-Hill Education 58
We learnt
• A real time clock (RTC) provides the
system clock to generate the system
interrupts
• An interrupt service routine executes on
each tick (timeout or overflow) of this
clock.
• This timing device once started is generally
never reset or never reloaded to another
value