Microelectronics Reliability 51 (2011) 2173–2178

Contents lists available at ScienceDirect

Microelectronics Reliability

journal homepage: www.elsevier .com/locate /microrel

Organic inverter: Theoretical analysis using load matching technique

S. Omar a,1, S. Mandal b,2, A. Ashok a,1, A.R. Harish a,1, M. Katiyar b,⇑,2

a Department of Electrical Engineering, Indian Institute of Technology, Kanpur 208 016, Indiab Department of Materials and Metallurgical Engineering, Indian Institute of Technology, Kanpur 208 016, India

a r t i c l e i n f o a b s t r a c t

Article history:Received 11 November 2010Received in revised form 3 April 2011Accepted 18 May 2011Available online 25 June 2011

0026-2714/$ - see front matter � 2011 Elsevier Ltd. Adoi:10.1016/j.microrel.2011.05.014

⇑ Corresponding author.E-mail addresses: sidomar18@gmail.com (S. Om

Mandal), arjitiitk@gmail.com (A. Ashok), arh@iitk.ac.i(M. Katiyar).

URL: http://www.elsevier.com (M. Katiyar).1 This author is from Electrical Engg. background.2 This author is from Material Science background.

This paper reports the analysis of key parameters affecting voltage transfer characteristics of pseudo PMOSorganic inverters. Pentacene has been used as active material for PMOS Organic Thin Film transistor (OTFT).We have used two different inverter configurations for thorough analysis. Each configuration comprises ofan enhancement mode driver (VThreshold = �9.7 V) and a depletion mode load (VThreshold = 11.7 V). First con-figuration has its source and gate terminals shorted. While, second configuration differs with its drain andgate terminals shorted. In order to surmise the theoretical performance of the inverters, we have used loadmatching technique. After investigating various parameters such as inverting gain, noise margin values(immunity to noise error signals) and threshold voltage value, influencing the voltage inverting efficiencyof the two configurations mentioned above, it was found that an inverter with shorted source-gate loadconfiguration is better of the two due to privileges such as saturation mode operation of load, low drivercurrent with early saturation of enhancement mode driver, which facilitates full swing output voltageoperation. Second configuration with shorted drain-gate load, lacks saturation mode operation of loadand fails to deliver high voltage swing along with acceptable noise margin values and inverting gain.

� 2011 Elsevier Ltd. All rights reserved.

1. Introduction

Inverters, based on inorganic semiconductors, constitute a ro-bust foundation for large scale logic circuits. Therefore, shift to-wards flexible electronics relies on the established performanceof organic inverters. However, it is difficult to realize CMOS inver-ter block using organic semiconductors as opposed to conventionalsilicon technology. Low carrier mobility and high degradation rateof n-type organic semiconductors in ambient conditions are funda-mental challenges in realizing the organic CMOS [1]. Hence, organ-ic inverter design relies solely on p-type organic semiconductorsand their use is limited to some specific applications such as smartcards, electronic papers and large area display, which do not re-quire high switching rate [2,3]. Extensive research work is beingcarried out on organic materials and pentacene appears to be themost reliable p-type material for Organic Thin Film Transistor(OTFT) based circuits because of its high carrier mobility, highIon/Ioff ratio and stability in ambient conditions [4–7]. A maximumhole mobility of 2.4 cm2 V�1 s�1 in ambient conditions [4], compa-rable to the mobility of amorphous-Si, makes organic semiconduc-tors a strong contender, capable of replacing amorphous-Si based

ll rights reserved.

ar), smandal@iitk.ac.in (S.n (A.R. Harish), mk@iitk.ac.in

applications due to relatively easier and low cost processing of or-ganic circuits.

Next level of development is to incorporate organic invertersinto integrated circuits. High gain and noise margin values of in-verter render reliability to cascading applications and digital oper-ations in electronic circuits [8]. Organic inverters reported inliterature, exhibit high gain (2–25) and have potential of runningmulti-stage logic such as ring oscillators and memory blocks withsuitable margin values [9]. In that direction, to realize OTFT basedinverters, an enhancement mode (E-mode) OTFT (negative Vth) anda depletion mode (D-mode) OTFT (positive VTH) were fabricatedover different Si/SiO2 substrates (p-type doped substrate having220 nm SiO2 layer on it), depositing pentacene as a p-type activematerial. Using E-mode OTFT as driver and D-mode OTFT as load,two different load configurations: (i) shorted source-gate load(1st configuration) and (ii) shorted drain-gate load (2nd configura-tion), have been used to study and analyze the performance ofinverters. We have used load matching technique to estimate theVoltage Transfer Characteristics (VTC) of inverter. Informationregarding inverter gain, noise margin and voltage swing can beanticipated by careful observation of the load matching curveand thus it is easier to figure out and propose modifications atthe early stage of design.

2. Experimental details: materials and device fabrication

A high performance pseudo PMOS inverter requires anenhancement mode (negative threshold voltage) driver OTFT and

2174 S. Omar et al. / Microelectronics Reliability 51 (2011) 2173–2178

a depletion mode (positive threshold voltage) load OTFT [2,3].Enhancement mode device was fabricated over Si/SiO2 substrate(Silicon Quest International) followed by treatment with OTS(octadecyltrichlorosilane) solution for 24 h in order to ingratiatepentacene molecules, to be deposited with relatively smallergrains. OTS solution removes the water molecules from the SiO2

surface and thus reduces the interface trap density. It may be a rea-son for negative shift of threshold voltage [10]. Additionally, it re-duces the effective capacitance value of insulator and makes thethreshold value more negative. OTS mono-layer also improves de-vice’s Ion/Ioff ratio as it also acts as an insulator having Eg = 9.3 eVand suppresses off-state leakage current. SiO2 layer, already pres-ent on the substrate acts as a gate dielectric of thickness 220 nm(capacitance = 15 nF/cm2). On top of it, a smooth surface of50 nm thick pentacene was deposited at 70 �C substrate tempera-ture and 3 � 10�6 mbar pressure by vacuum deposition technique.Source and drain electrodes were deposited over pentacene layerin the thermal evaporator chamber, using gold as the source mate-rial. Pressure of the chamber was maintained at 5.5 � 10�6 mbarand substrate temperature was set to the room temperature.Deposited electrode thickness was 50 nm (Fig. 1a). Depletion modedevice was fabricated following the similar procedure, with a sin-gle difference that Si/SiO2 substrate was not treated with OTS solu-tion (Fig. 1b). The E-mode and D-mode transistors were fabricatedseparately and wire connected to make an inverter and not inte-grated in the same substrate.

3. Results and discussion

I–V characteristics of both the E-mode and D-mode OTFTs weredetermined using Keithley 2602 source meter. A threshold voltage(Vth) of the order of �9.7 V having mobility 0.11 cm2 V�1 s�1 andIon�off ratio 103, was observed for E-mode device (Fig. 2). Depletionmode device expectedly exhibited a positive threshold voltage of11.7 V with mobility 0.21 cm2 V�1 s�1 and Ion�off ratio 104 (Fig. 3).

Refitting of D-mode OTFT into load was performed by measur-ing its shorted drain-gate performance. It is evident from the curvethat resulted performance is similar to the diode I–V performance,which could be used as a voltage controlled resistor (Fig. 4). Devicesymmetry of OTFT, which is an important feature, can be used toobtain I–V characteristics of both the load configurations fromthe single measurement of either of the 1st and 2nd D-mode load.The only difference is that source and drain swap their position andthe plot of first device is mirrored about y-axis (ILoad) to obtain thesecond device performance. Therefore, I–V performance of onlyshorted drain-gate D-mode OTFT was measured (Fig. 4). It hascut-in voltage of approximately +11 V. Region of operation of loadplays vital role in deciding the performance of particular load con-figuration. We follow the thumb rule that current always flowsfrom source to drain in case of PMOS. For load OTFT of 1st config-

Fig. 1. Top gate structure of pentacene based OTFT (a) MOS structure of subst

uration (Fig. 5), region of operation will be positive half portion ofthe load I–V curve (Fig. 4). Saturation region operation can be ver-ified for PMOS by following equation:

VDS 6 VGS � Vth ð1Þ

On applying this condition to the load of 1st configuration weobtain the condition for saturation, Vsource P Vth, which can be ver-ified from circuit of Fig. 5. When Vsource exceeds Vth, load gets satu-rated and this is exactly what we see when applied voltage exceeds11 V (Vth of D-mode OTFT), it gets saturated.

Inverter performance can be calculated from load matchingtechnique by measuring individually the driver and the load I–Vcharacteristics and then by mapping driver I–V curve onto the loadI–V curve, which was obtained by shorting its drain-gate terminals[8,10], bound to a befitting equation set. For E-mode driver and D-mode shorted source-gate configuration (1st configuration), I–Vcharacteristics of both curves can be mapped by applying KirchoffCurrent Law (KCL) to the Fig. 5 circuit using following equation set:

ILoad ¼ �IDriver ð2ÞVDS Load ¼ VDS Driver þ VDD ð3Þ

Vout can be directly captured by observing the x-axis coordinate (VDS

Load) of the quiescent points of load plot with driver plot (Fig. 6a). Vin

can be obtained from following equation:

Vin ¼ VGS Driver þ VDD ð4Þ

Fig. 6b describes inverting behaviour of the design. Quiescentpoints of the curve incorporate Voltage Transfer Characteristics(VTC) of 1st configuration. Intersection point of load curve with dif-ferent driver curve branches, each plotted at a unique VGS Driver,gives Vout and subsequently, corresponding Vin can be calculatedfrom Eq. (4). By careful observation, we locate that quiescentpoints are concentrated only in two regions. First region, whichencompasses the points of low Vout value, is obtained for load oper-ating at linear region while driver in saturation region. Second re-gion, for high Vout values, is obtained for load in saturation regionwhile driver at linear region.

As mentioned above, MOS is a symmetric device and its sym-metry can be used to anticipate the performance of a mirror imageconfiguration. A shorted source-gate I–V curve can be tapped forpredicting the I–V performance of shorted drain-gate load for dif-ferent region of voltage operation (source and drain interchange,as voltage changes its sign) (Fig. 7). For 2nd configuration, negativehalf of load I–V curve of Fig. 4 will be considered as region of oper-ation. On applying Eq. (1) to the 2nd load device configuration, de-vice will only be saturated when Vth 6 0 which can not be obtainedfor D-mode OTFT and it always remains in linear region of opera-tion. Now, for the 2nd configuration, transformation equations,which can be derived by applying KCL to the circuit of Fig. 7, under-go following modifications:

rate treated with OTS solution (b) MOS structure without OTS treatment.

Fig. 2. (a) IDS–VDS characteristics and (b) transfer characteristics of enhancement mode pentacene PMOS.

Fig. 3. (a) IDS–VDS characteristics and (b) transfer characteristics of depletion mode pentacene PMOS.

−40 −30 −20 −10 0 10 20 30 40 50−6

−5

−4

−3

−2

−1

0

1x 10

−5

Load Voltage (Volts)

Load

Cur

rent

(Am

p)

Fig. 4. I–V characteristics of depletion mode shorted source-gate pentacene PMOS.

S. Omar et al. / Microelectronics Reliability 51 (2011) 2173–2178 2175

ILoad ¼ IDriver ð5Þ� VDS Load ¼ VDS Driver þ VDD ð6Þ

Fig. 8a and b elaborates the load matching curve and the VTC of thisinverter design. Quiescent points of load plot with driver plot giveVout, with respect to the x-axis of load matching curve and Vin canbe found out from Eq. (4). For this configuration, quiescent pointsare densified in two areas of operation. Region of low Vout points,which approaches to logic zero, outlines the load in linear modeand the driver operating in saturation mode. 2nd region of high Vout

values, which map to the logic one, corresponds to both the loadand the driver in linear mode.

Noise margin, switching voltage and gain around switchingvoltage are the pivotal elements in inverter’s performance. Defini-

tion of noise margin (NM) can be realized in cascaded feedbackloops i.e. ring oscillators or bistable feedback circuits. Followingequation set illustrates the basic definition of NM [11]:

Vout P VOH when Vin 6 VIL ð7ÞVout 6 VOL when Vin P VIH ð8Þ

In the above equation set, noise margin (NM) can also beviewed as maximum allowed error which can be endured by inver-ter for undistorted reliable output. If we assume two inverters con-nected back to back just like a bistable S-R latch, definition of NMcan easily be verified. If input, bound to Eq. (7) is applied to 1st in-verter in Fig. 9, its output is defined by same equation. Now, outputof the first inverter becomes input to the second inverter andinequality itself reverses its sign for the input and Vin P VOH. Vin

also satisfies Eq. (8) for the 2nd inverter. If VIH 6 VOH, we are inthe safe region and we can define margin of immunity as NMHigh =VOH � VIH. Now, propagating this condition to the 2nd inverter, forinput voltage greater than a certain threshold, Vout 6 VOL, but in thecircuit shown, it again becomes input to the 1st inverter and ifVOL 6 VIL, we can again define the margin as NMLow = VIL � VOL.MPC (Maximum Product Criteria) technique has been used hereto find out the value of noise margin (NM). VTCs for bistable circuitof Fig. 9 were plotted for both the proposed configurations on thesame axis and enclosed area was used to find out the maximumrectangle area while taking all possible combinations of datapoints. The vertical line of rectangular area obtained from MPCprocedure, is taken as NMH and horizontal line as NML. For 1st con-figuration, respective sides of rectangle, obtained from the proce-dure mentioned above were marked as NMH and NML. For 2ndconfiguration, due to nature of VTC curve it is not possible to definea rectangle and we could only locate a horizontal line and its max-imum value was treated as NML. For 1st configuration, saturationmode load and linear mode driver operation leads to high VOH va-lue and at low voltage linear mode operation of load and saturation

Fig. 5. E–D mode shorted source-gate inverter.

(a)

(b)

Fig. 6. (a) Load matching curve for E–D mode shorted source-gate inverter (b) VTCof inverter.

2176 S. Omar et al. / Microelectronics Reliability 51 (2011) 2173–2178

mode of driver leads to low VOL value thus improving both NMH

and NML. Linear mode operation of load of 2nd configuration re-sults in low voltage swing and low output voltage. Consequently,NMH(VOH � VIH) value becomes insignificant for the logic opera-tions. On careful inspection of the curve, it is evident that VOL alsoincreases due to concave nature of the curve. It degrades the NML

performance of the device. Performance can be marginally im-proved only by reducing ILoad, while keeping IDriver fixed. As a resultof it, NMH improves at the cost of NML. It also improves the gain ofthe inverter.

Robustness of inverter can be concluded by looking at itsswitching voltage. Switching voltage (VSwitch) is defined at a pointwhere the line Vout = Vin intersects the voltage transfer curve ofthe inverter. At full swing, VTC having symmetric switching volt-age is preferred. Symmetry of switching voltage can be observedby looking at the distribution of quiescent points in load matchingcurve. If a line, parallel to y-axis is drawn at the x = VDD/2 and dis-tribution of quiescent points, around the line is observed, closerwill be Vswitch to VDD/2, more symmetric is the distribution. Devia-tion from symmetry will shift the Vswitch to the region where max-imum points lie. Switching voltage can also be adjusted bychanging the size of driver or load OTFT in order to operate atasymmetric levels [12]. Designing a device with asymmetric Vswitch

may be helpful when noise level is high at either of the logic levelfor suppressing the noise. Symmetric distribution of quiescentpoints of 1st configuration leads to a symmetric VSwitch, while2nd configuration exhibits lower VSwitch value as most of the quies-cent points are distributed in the low Vout region.

Voltage gain (�@Vout/@Vin) at Vswitch also plays vital role in digitaloperations. Gain at Vswitch quantifies how fast the inverter isswitching from one voltage level to another with respect to volt-age. Load matching curve can also give an idea of the gain magni-tude, which is proportional to maximum horizontal separation oftwo consecutive quiescent points. It is evident from respective loadmatching curves that 1st configuration has larger separation be-tween two consecutive quiescent points and thus exhibits highergain. For multi-stage logic implementation we also require an in-verter with gain higher than unity. Higher gain causes the cascadedfeedback circuit to oscillate, if designed appropriately [12]. Theo-retically, a linear combination of all the three parameters, opti-mized individually, will lead to the best inverter design.Comparison between both the designs makes it clear that pseudoPMOS inverter based on shorted source-gate load is the appropri-ate choice for logic implementation and cascading.

From VTCs, obtained from the quiescent points of the loadmatching curve of Figs. 6 and 8, various quantities such as noisemargin, inverter gain and switching voltage can be derived. Table 1summarizes the performance of the two configurations. It is evi-dent from the table values that shorted source-gate configurationhas symmetric Vswitch value (applied voltage ranges from 0 to40 V), gain with magnitude greater than one and acceptable noisemargin values satisfying the constraints.

It is also important to note that effect of bias stress on inverterperformance may be different in two configurations. Two different

Fig. 7. E–D mode shorted drain-gate inverter.

(a)

(b)

Fig. 8. (a) Load matching curve for E–D mode shorted drain-gate inverter (b) VTC ofinverter.

Fig. 9. Inverter-1 and inverter-2 connected back to back for positive feedbackoperation.

Table 1Comparison of 1st configuration and 2nd configuration of E–D mode pseudo PMOSinverter.

Load Switchingvoltage

Gain atVswitch

NMH

(VOH � VIH) (V)NML

(VIL � VOL) (V)

Shorted source-gate(1st device)

22.8 �3.24 4.5 19.4

Shorted drain-gate(2nd device)

5 �0.2 ⁄⁄ 2.3

S. Omar et al. / Microelectronics Reliability 51 (2011) 2173–2178 2177

biasing effects have been reported in case of organic transistors.First effect is responsible for generally negative threshold voltage

shift due to gate biasing (negative VGS) and second effect attributesto positive threshold voltage shift due to drain biasing effect (neg-ative VDS) [13]. Hence measurement of gate bias stress and drainbias stress effect in our load/driver OTFTs will be important. Thebias effect can also be nullified by resizing the driver with compar-atively smaller channel width or modification in other parametersusing our theoretical tool.

4. Conclusion

In this paper two different E–D mode configurations of pseudoPMOS inverter were analyzed using load matching method and itwas found that the 1st configuration having a load with its sourceand gate terminals shorted, exhibits high noise margin and highgain, including full swing operation. Theoretical estimate usingload matching provides better insight for modification of parame-ters by readjustment of quiescent points in desired region and itcan be observed directly from the load matching curve. Perfor-mance can also be optimized by resizing the driver and the load.Obtained values are in acceptable range for implementing logic cir-cuit based applications.

Acknowledgement

This research was financially supported by Ministry of Commu-nication and Information Technology, Govt. of India.

References

[1] Dimitrakopoulos CD, Mascaro DJ. Organic thin- film transistors: a review ofrecent advances. IBM J Res Dev 2001;45(1):11–27.

[2] Lee CA, Jin SH, Jung KD, Lee JD, Park B-G. Full-swing pentacene organic inverterwith enhancement-mode driver and depletion-mode load. Solid-State Electron2006;50:1216–8.

2178 S. Omar et al. / Microelectronics Reliability 51 (2011) 2173–2178

[3] Koo JB, Suh KS, Kim SH. Organic inverter including surface-treated layer andmethod of manufacturing the same. US 2008/0135947 A1; 2008.

[4] Dimitrakopoulos CD, Malenfant PL. Organic thin film transistors for large areaelectronics. Adv Mater 2002;14(2):99–117.

[5] Reese C, Roberts M, Ling M, Bao Z. Organic thin film transistors. Adv Mater 7.[6] Koo JB, Ku CH, Lim JW, Kim SH. Novel organic inverters with dual-gate

pentacene thin-film transistor. Organic Electron 2007;8:552–8.[7] Matters M, de Leeuw D, Vissenberg M, Hart C, Herwig P, Geuns T, et al. Organic

eld-effect transistors and all-polymer integrated circuits. Optical Mater1997;12:189–97.

[8] de Leeuw D, Cantatore E. Organic electronics: materials, technology and circuitdesign developments enabling new applications. Mater Sci SemiconductorProcess 2008;11(5–6):199–204.

[9] Choi M-C, Kimb Y, Ha C-S. Polymers for flexible displays: from materialselection to device applications. Prog Polym Sci 2008;33:581–630.

[10] Mandal S, Singh R, Katiyar M. Processing and fabrication of advancedmaterials. XVII: Role of octadecyltrichlorosilane on the performance ofpentacene based organic thin film transistor, vol. 1. I.K. InternationalPublishing House Pvt. Ltd.; 2009.

[11] Hauser JR. Noise margin criteria for digital logic circuits. IEEE Trans Education1993;36(4):363–8.

[12] Rabaey JM, Chandrakasan A, Nikolic B. Digital integrated circuits. 2nded. Prentice Hall; 2008.

[13] Liu YR, YU JL, Lai PT, Wang ZX, Hana J, Liao R. Threshold-voltage instability ofpolymer thin-film transistor under gate-bias and drain-bias stresses. IEEEElectron Dev Solid State Circ 2008:1–4.