Design project #3
- Phase Locked Loops
Introduction
Phase locked loops
1. Output clock frequency : 500 MHz
2. Dividing ratio : 1
VCOCont2 generator
Initial condition
generator
VCO
Cont2 generator
Gain = 1
Initial condition generator
VCO
FFT
500MHz @ ??V
Check the control
voltage at 500MHz!
VCOControl voltage range 1 ~ 2.5V (Parametric sweep)
Low freq High freq
Average VCO gain :
(High freq-Low freq)/1.5
Average VCO gain
:100MHz/V ~ 150 MHz/V
Include 500MHz
Charge pump
Feedback amp
Charge pumpFeedback amp
Gain = 100
Charge pump
Feedback amp
Design parameter for
up & down current
: 1. TR size
2. nbias
Up current
Down current
DC sweep
Charge pumpUp current = 4~6mA
@ Control voltage for 500MHz VCO in Part I
Charge pumpDown current = 4~6mA
@ Control voltage for 500MHz VCO in Part I
Charge pumpMismatch current < 50uA @ your control voltage
Available range > 1.45V
50uA @ Low voltage
-50uA @ High voltage
Available range :
High voltage – Low voltage
Available range
Phase locked loops
PLL system
Closed loop transfer function
C2=C1/10
Natural frequency(f0)
=25MHz
Show your matlab
result!
Phase locked loops
Open loop transfer function of PLL system
Phase
margin
Phase margin >
50 deg
Phase locked loops
Closed loop transfer function of PLL system
Max. peakingMax. peaking < 2 dB
Simulink
Loop filter
transfer function
Don’t touch!
Simulink
Double clickDouble click
Simulink
Insert your charge
pump up current
Insert your charge
pump down current
Simulink
500e6 – (Average VCO gainⅹyour control voltage @ 500MHz)
Your average VCO gain
SimulinkDouble click
SimulinkSettling time
Locking point – 0.005 <Ripple < Locking point – 0.005
Ex) Locking point = 1.7V
Settling time = 55ns
Phase locked loops
Resistor limitation
R= 580~600Ω
If you can’t satisfy specifications, you should redesign your
VCO or charge pump!
Natural frequency(f0) =25MHz
Phase margin > 50 deg
Max. peaking < 2 dB
Low settling time