VSM‟S - VSMIT

VSM‟S Somashekar R. Kothiwale Institute of Technology, Nipani.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

HDL 17ECL58

Somashekar R. Kothiwale Institute of Technology,

Nipani.

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING

LAB MANUAL

SUB: HDL LABARATORY

SUB CODE: 17ECL58

SEMESTER: V

By: Prof Prashant Hebbale

Asst Prof, ECE Dept

VSMSRKIT, Nipani

SYLLABUS



HDL 17ECL58

Part–A: PROGRAMMING

1. Write Verilog code to realize all the logic gates

2. Write a Verilog program for the following combinational designs

a. 2 to 4 decoder

b. 8 to 3 (encoder without priority & with priority)

c. 8 to 1 multiplexer.

d. 4 bit binary to gray converter

e. Multiplexer, de-multiplexer, comparator.

3. Write a VHDL and Verilog code to describe the functions of a Full Adder using three

modeling styles.

4. Write a Verilog code to model 32 bit ALU using the schematic diagram shown below

ALU should use combinational logic to calculate an output based on the four bit

op-code input.

ALU should pass the result to the out bus when enable line in high, and tri-state

the out bus when the enable line is low.

ALU should decode the 4 bit op-code according to the example given below.

5. Develop the Verilog code for the following flip-flops, SR, D, JK and T.

6. Design a 4 bit binary, BCD counters (Synchronous reset and Asynchronous

reset) and “any sequence” counters, using Verilog code.

Part–B: INTERFACING (at least four of the following must be covered using

VHDL/Verilog)

1. Write HDL code to display messages on an alpha numeric LCD display.

2. Write HDL code to interface Hex key pad and display the key code on seven segment

display.

3. Write HDL code to control speed, direction of DC and Stepper motor.



HDL 17ECL58

4. Write HDL code to accept Analog signal, Temperature sensor and display the data on

LCD or Seven segment display.

5. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,)

using DAC - change the frequency.

6. Write HDL code to simulate Elevator operation.



HDL 17ECL58

TOOL PROCEDURE

It is one of most popular software tool used to synthesize VHDL code. This tool

Includes many steps. To make user feel comfortable with the tool the steps are

given below:-

1 Double click on Project navigator. (Assumed icon is present on desktop).

2 Select NEW PROJECT in FILE MENU.

Enter following details as per your convenience

Project name : sample

Project location : C:\example

Top level module : HDL

3 In NEW PROJECT dropdown Dialog box, Choose your appropriate

device specification. Example is given below:

Device family : Spartan2

Device : xc2s200

Package : TQ144

TOP Level Module : HDL

Synthesis Tool : XST

Simulation : Modelsim / others

Generate sim lang : VHDL

4 In source window right click on specification, select new source

Enter the following details

Entity: sample

Architecture : Behavioral

Enter the input and output port and modes.

This will create sample.VHDL source file. Click Next and finish the

initial Project preparation.

5 Double click on synthesis. If error occurs edit and correct VHDL code.

6 Double click on Lunch modelsim (or any equivalent simulator if you are

using) for functional simulation of your design.

7 Right click on sample.VHDL in source window, select new source

Select source : Implementation constraints file.



HDL 17ECL58

File name : sample

This will create sample. UCF constraints file.

8 Double click on Edit constraint (Text) in process window.

Edit and enter pin constraints with syntax:

NET “NETNAME” LOC = “PIN NAME”

9 Double click on Implement, which will carry out translate, mapping,

place and route of your design. Also generate program file by double

clicking on it, intern which will create .bit file.

10 Connect JTAG cable between your kit and parallel pot of your computer.

11 Double click on configure device and select mode in which you want to

configure your device. For ex: select slave serial mode in configuration

window and finish your configuration.

12 Right click on device and select „program‟. Verify your design giving

appropriate inputs and check for the output.

13 Also verify the actual working of the circuit using pattern generator &

logic analyzer.



HDL 17ECL58

1. VERILOG CODE FOR ALL BASIC GATES

module gates(A, B, NOTOUT, OROUT, ANDOUT,

NOROUT,NANDOUT,XOROUT,XNOROUT);

input A,B;

output NOTOUT;

output OROUT;

output ANDOUT;

output NOROUT;

output NANDOUT;

output XOROUT;

output XNOROUT;

assign NOTOUT= ~A;

assign OROUT=A|B;

assign ANDOUT=A&B;

assign NOROUT=~(A|B);

assign NANDOUT=~(A&B);

assign XOROUT=A^B;

assign XNOROUT=~(A^B);

endmodule

RESULT:

A B NOT

OUT OROUT

ANDOUT NOROUT

NAND

OUT XOROUT XONROUT

0 0 1 0 0 1 1 0 1

0 1 1 1 0 0 1 1 0

1 0 0 1 0 0 1 1 0

1 1 0 1 1 0 0 0 1



HDL 17ECL58

2. VERILOG CODE FOR 2 TO 4 DECODER

module DECODER (DIN,ENABLE,D_OUT);

input [1:0] DIN;

output [3:0] D_OUT;

reg [3:0] D_OUT;

always @(DIN,ENABLE)

begin

if (ENABLE==1‟ b 1)

D_OUT=4‟b0000;

else

begin

case (DIN)

2'b00: D_OUT = 4'b0001;

2'b01: D_OUT = 4'b0010;

2'b10:D_OUT = 4'b0100;

2'b11: D_OUT = 4'b1000;

default: D_OUT =4'bXXXX;

endcase

end

end

endmodule

RESULT:-

Enable Select Lines Outputs

ENAB

LE

DIN(

1)

DIN(

0)

D_OUT(

3)

D_OUT(

2)

D_OUT(

1)

D_OUT(

0)

1 X X 0 0 0 0

0 0 0 0 0 0 1

0 0 1 0 0 1 0

0 1 0 0 1 0 0

0 1 1 1 0 0 0



HDL 17ECL58

2.(B)(I)VERILOG CODE FOR 8TO 3 ENCODER (WITHOUT PRIORITY)

module ENCODER8_3(ENABLE, DIN, D_OUT);

input EN;

input [7:0] DIN;

output [2:0] D_OUT;

reg [2:0] D_OUT;

always @ (DIN,ENABLE)

begin

if(ENABLE==1| )

D_OUT=3‟b000;

else

begin

case (DIN)

8'b00000001: D_OUT = 3'b000;

8'b00000010: D_OUT = 3'b001;

8'b00000100: D_OUT = 3'b010;

8'b00001000: D_OUT = 3'b011;

8'b00010000: D_OUT = 3'b100;

8'b00100000: D_OUT = 3'b101;

8'b01000000: D_OUT = 3'b110;

8'b10000000: D_OUT = 3'b111;

default: D_OUT =3'bXXX;

endcase

end

endmodule

RESULT

INPUTS OUTPUTS

ENAB

LE

DIN(

0)

DIN(

1)

DIN(

2)

DIN(

3)

DIN(

4)

DIN(

5)

DIN(

6)

DIN(

7)

D_OU

T

(0)

D_OU

T

(1)

D_OU

T

(2)

1 X X X X X X X X 0 0 0

0 1 0 0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0 0 0 1

0 0 0 1 0 0 0 0 0 0 1 0

0 0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 0 1 1 1 1



HDL 17ECL58

2.(B)(II)VERILOG CODE FOR 8TO 3 ENCODER (WITH PRIORITY)

module ENCODER8_3(ENABLE, DIN, D_OUT);

input EN;

input [7:0] DIN;

output [2:0] D_OUT;

reg [2:0] D_OUT;

always @ (DIN,ENABLE)

begin

if(ENABLE==1| )

D_OUT=3‟b000;

else

begin

casex (DIN)

8'b00000001: D_OUT = 3'b000;

8'b0000001x: D_OUT = 3'b001;

8'b000001xx: D_OUT = 3'b010;

8'b00001xxx: D_OUT = 3'b011;

8'b0001xxxx: D_OUT = 3'b100;

8'b001xxxxx: D_OUT = 3'b101;

8'b01xxxxxx: D_OUT = 3'b110;

8'b1xxxxxxx: D_OUT = 3'b111;

default: D_OUT =3'bXXX;

endcase

end

endmodule

RESULT

INPUTS OUTPUTS

ENAB

LE

DIN(

0)

DIN(

1)

DIN(

2)

DIN(

3)

DIN(

4)

DIN(

5)

DIN(

6)

DIN(

7)

D_OU

T

(0)

D_OU

T

(1)

D_OU

T

(2)

1 X X X X X X X X 0 0 0

0 1 0 0 0 0 0 0 0 0 0 0

0 X 1 0 0 0 0 0 0 0 0 1

0 X X 1 0 0 0 0 0 0 1 0

0 X X X 1 0 0 0 0 0 1 1

0 X X X X 1 0 0 0 1 0 0

0 X X X X X 1 0 0 1 0 1

0 X X X X X X 1 0 1 1 0

0 X X XX X X X X 1 1 1 1



HDL 17ECL58

2. (C)VERILOG CODE FOR 8TO 1 MUX

module MUX8_1(A, SEL, D_OUT);

input [7:0] A;

input [2:0] SEL;

output D_OUT;

reg D_OUT;

always@ (A,SEL )

begin

case (SEL)

3'b000:D_OUT=A[0];

3'b001:D_OUT=A[1];

3'b010:D_OUT=A[2];

3'b011:D_OUT=A[3];

3'b100:D_OUT=A[4];

3'b101:D_OUT=A[5];

3'b110:D_OUT=A[6];

3'b111:D_OUT=A[7];

default: D_OUT =3'b000;

endcase

end

endmodule

RESULT:

INPUTS OUTPU

T

SEL[2

]

SEL[1

]

SEL[0

]

D_OUT

0 0 0 A[0]

0 0 1 A[1]

0 1 0 A[2]

0 1 1 A[3]

1 0 0 A[4]

1 0 1 A[5]

1 1 0 A[6]

1 1 1 A[7]



HDL 17ECL58

2. (D) VERILOG CODE FOR BINARY TO GRAY CONVERTER

module BINARY_GRAY(B, G);

input [3:0] B;

output [3:0] G;

assign G[3] = B[3];

assign G[2] = B[3] ^ B[2];

assign G[1] = B[2] ^ B[1];

assign G[0] = B[1] ^ B[0];

endmodule

G2 G1 G0

B1

B0

B1

B0

B1 B0

B3 B2 00 01 11 10 B3 B2 00 01 11 10 B3 B2 00 01 11 10

00 00 1 1 00 1 1

01 1 1 1 1 01 1 1 01 1 1

11 11 1 1 11 1 1

10 1 1 1 1 10 1 1 10 1 1

G3=B

3

G2 = B3 B2‟ + B3 B2‟

G2 = B3 B2

G1 = B2 B1‟ + B1 B2‟

G1 = B1 B2

G0 = B1‟B0 + B1

B0‟

G0 = B1 B0

RESULT:

Binary inputs Gray Outputs

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0



HDL 17ECL58

2.(E) (I) VERILOG CODE FOR 1:4 DEMUX

module DEMUX1_4(D_IN, SEL, D_OUT);

input D_IN;

input [1:0] SEL;

output [3:0] D_OUT;

reg[3:0] D_OUT;

always @(D_IN, SEL)

begin

case (SEL)

2b00:D_OUT[0]=D_IN;

2'b01:D_OUT[1]=D_IN;



default: D_OUT=3'b000;

endcase

end

endmodule

RESULT:-

SELECT INPU

T

OUTPUT

SEL[

1]

SEL[

0]

D_IN D_OUT[

3]

D_OUT[

2]

D_OUT[

1]

D_OUT[

0]

0 0 1 X X X 1

0 1 1 X X 1 X

1 0 1 X 1 X X

1 1 1 1 X X X



HDL 17ECL58

2 (E)(II). COMBINATIONAL VERILOG CODE FOR 4-BIT COMPARATOR

module COMPARATER(A, B, ALB,AGB,AEB);

input [3:0] A;

input [3:0] B;

output ALB;

output AGB;

output AEB;

reg ALB,AGB,AEB;

always @ (A,B)

begin

if (A<B)

ALB=1'b1;

else

ALB=1'b0;

if (A>B)

AGB=1'b1;

else

AGB=1'b0;

if (A==B)

AEB=1'b1;

else

AEB=1'b0;

end

endmodule

RESULT:

A B A=B A>B A<B

000

0

000

0

1 0 0

000

0

010

0

0 1 0

010

0

000

1

0 0 1



HDL 17ECL58

3.VERILOG CODE FOR THE IMPLEMENTATION OF HALF ADDER.

DATA FLOW STYLE

module HALFADDER(A, B, SUM, CARRY);

input A, B;

output SUM, CARRY;

assign SUM = A^B;

assign CARRY = A & B;

endmodule

BEHAVIORAL STYLE

module HALFADDER(AB, SUM, CARRY);

input[1:0] AB; RESULT

output SUM,CARRY;

reg SUM,CARRY;

always@(AB)

begin

case AB

2‟b00:begin SUM=1‟b0; CARRY=1‟b0;end




endcase

end

endmodule

STRUCTURAL STYLE

module HALFADDER(A, B, SUM, CARRY);

input A,B;

output SUM,CARRY;

XOR U1 ( SUM , A, B);

AND U2 (CARRY, A, B);

Endmodule

Inputs Outputs

A B Sum(S) Carry(C)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1



HDL 17ECL58

TRUTH TABLE

Inputs Outputs

A B C Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

SUM

BC

CARRY

BC

A 00 01 11 10 A 00 01 11 10

0 0 1 0 1 0 0 0 1 0

1 1 0 1 0 1 0 1 1 1

SUM=A‟B‟C+A‟BC‟+AB‟C‟

+ABC

SUM = A B C

CARRY = AB+BC+AC



HDL 17ECL58

3b.VERILOG CODE FOR THE IMPLEMENTATION OF FULL ADDER.

DATA FLOW STYLE

module FULLADDER(A, B, CIN, SUM, CARRY);

input A, B,CIN;

output SUM, CARRY;

assign SUM = A^B^CIN;

assign CARRY = (A & B)|(B & CIN)|(A & CIN);

endmodule

BEHAVIORAL STYLE

module FULLADDER(ABC, SUM, CARRY);

input[2:0] ABC;

output SUM,CARRY;

reg SUM,CARRY;

always@(ABC)

begin

case (ABC)





3‟b100:begin SUM=1‟b1; CARRY=1‟b0end




endcase

end

endmodule

STRUCTURAL STYLE

module FULLADDER(A, B, CIN, SUM, CARRY);

input A,B, CIN;

output SUM,CARRY;

wire Temp1, Temp2, Temp3;

HALFADDER HA1 (A, B, Temp1, Temp2);

HALFADDER HA2 (CIN, Temp1, SUM, Temp3);

assign CARRY=Temp3| Temp2;

endmodule



HDL 17ECL58

RESULT:-

Inputs Outputs

A B C Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1



HDL 17ECL58

4. VERILOG CODE FOR 8-BIT ALU MODEL.

module ALU(A, B, SEL,EN,Y);

input [31:0] A,B;

input EN;

input [2:0] SEL;

output [31:0] Y;

reg [31:0]Y;

always @(A, B , SEL)

begin

if (EN==1)

begin

case (SEL)

3'b000:Y=A+B;

3'b001:Y=A-B;

3'b010:Y=~A;

3'b011:Y=A&B;

3'b100:Y=A|B;

3'b101:Y=~(A&B);

3'b101:Y=~(A|B);

3'b111:Y=A^B;

endcase

end

else

begin

Y=31‟bZ;

end

end

endmodule



HDL 17ECL58

5(A). VERILOG CODE FOR SR F/F

module SR_FF(SR, CLK, RST, Q, QBAR);

input [1:0]SR;

input RST, CLK;

output Q,QBAR;

reg Q,QBAR;

always @ (posedge CLK)

begin

if (RST==1)

begin

Q=0;

QBAR=1;

end

else

begin

case (SR)

2'b00: begin Q=Q; QBAR=QBAR; end

2'b01: begin Q=0; QBAR=1; end


2'b11: begin Q=1'bX; QBAR=1'bX; end

endcase

end

end

endmodule

RESULT:

INPUTS OUTPUTS

RST S R Q QBA

R

1 X X 0 1

0 0 0 0 1

0 0 1 0 1

0 1 0 1 0

0 1 1 X X



HDL 17ECL58

5(B). VERILOG CODE FOR D-FLIPFLOP.

module D_FF(D, RESET, CLK, Q, QBAR);

input D;

input RESET;

input CLK;

output Q;

output QBAR;

reg Q,QBAR;

always@(posedge CLK)

begin

if (RESET==1)

begin

Q=0;

QBAR=1;

end

else

begin

Q=D;

QBAR=~D;

end

end

endmodule

RESULT:-

RESE

T

D Q QBA

R

1 X 0 1

0 0 0 1

0 1 1 0



HDL 17ECL58

5(C) . VERILOG CODE FOR JK-FLIPFLOP.

module JK_FF(J, K, CLK, RESET, Q, QBAR);

input [1:0]JK;

input CLK,RESET;

output Q, QBAR;

reg Q, QBAR;

reg [22:0] div;

reg clkdiv;


begin

div = div+1'b1;

clkdiv = div[22];

end

always @ (posedge clkdiv)

begin

if(RESET==1)

begin

Q=0;

QBAR=1;

end

else

begin

case (JK)

2'b00: begin Q=Q; QBAR=QBAR; end



2'b11: begin Q=~(Q); QBAR=~(QBAR); end

endcase

end

end

endmodule

RESULT:-

RESE

T J K Q QBAR

1 X X 0 1

0 0 0 0 1

0 0 1 0 1

0 1 0 1 0

0 1 1 1 0



HDL 17ECL58

5(D) . VERILOG CODE FOR T-FLIPFLOP.

module T_FF(T, CLK, RESET, Q, QBAR);

input T, CLK, RESET;

output Q, QBAR;

reg Q,QBAR;


begin

div = div+1'b1;

clkdiv = div[22];

end

always @ (posedge clkdiv)

begin

if (RESET==1)

begin

Q=0;

QBAR=1;

end

else

case T

1‟b0:begin Q=Q; QBAR=QBAR; end

1‟b1:begin Q=~(Q); QBAR=~(QBAR)S; end

endcase

end

endmodule

RESULT:

RESE

T T Q QBAR

1 X 0 1

0 0 Q QBAR

0 1 QBAR Q



HDL 17ECL58

6. Design a 4 bit binary, BCD counters (Synchronous reset and Asynchronous reset) and

“any sequence” counters, using Verilog code.

6).A).VERILOGCODE FOR SYNCHRONOUS UP COUNTER

Module sys_up (clk,q,qbar);

Input clk;

output [3:0]q,qbar;

Wire s0,s1

Supply1 vdd;

JK_FF jkff0(vdd,vdd,clk,q[0],qbar[0]);


Assign s1=s0q[0]&q[1];

JK_FF jkff2(s0,s0,clk,q[2],qbar[2]);

Assign s1=s0 & q[2];


endmodule

Module JK_FF(J,K,clk,q,qbar);

Input clk;

Input JK;

Output q,qbar;

Reg q,qbar;

Initial

Begin q=1‟b0;qbar=1‟b1;end



HDL 17ECL58

Always @(posedge clk)

Begin

Q=(J&(~q))|((~K)&q);

Qbar=((~q));

End

endmodule

RESULT:-

Clock Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1



HDL 17ECL58

6).B).VERILOGCODE FOR SYNCHRONOUS DOWN COUNTER

Module sys_down (clk,q,qbar);

Input clk;

Output [3:0]q,qbar;

Wire s0,s1

Supply1 vdd;



Assign s0=q[0]&qbar[1];


Assign s1=s0 & qbar[2];


endmodule


Input clk;

Input JK;

Output q,qbar;

Reg q,qbar;

Initial



Begin

Q=(J&(~q))|((~K)&q);



HDL 17ECL58

Qbar=~q;

End

Endmodule

RESULT:-

Clock Q3 Q2 Q1 Q0

15 1 1 1 1

14 1 1 1 0

13 1 1 0 1

12 1 1 0 0

11 1 0 1 1

10 1 0 1 0

9 1 0 0 1

8 1 0 0 0

7 0 1 1 1

6 0 1 1 0

5 0 1 0 1

4 0 1 0 0

3 0 0 1 1

2 0 0 1 0

1 0 0 0 1

0 0 0 0 0



HDL 17ECL58

VERILOG CODE FOR ASYNCHRONOUS COUNTER

6) C).VERILOG CODE FOR ASYNCHRONOUSUP COUNTER


Input clk;

Output [3:0]q,qbar;

Supply1 vdd;


JK_FF jkff1(vdd,vdd,q[0],Q[1],qbar[1]);

JK_FF jkff2(vdd,vdd,q[1],q[2],qbar[2]);

JK_FF jkff3(vdd,vdd,q[2],q[3],qbar[3]);

endmodule


Input clk;

Input JK;

Output q,qbar;

Reg q,qbar;

Initial



Begin

q=(J&(~q))|((~K)&q);

qbar=~q;

End



HDL 17ECL58

Endmodule

RESULT:-

Clock Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1



HDL 17ECL58

6) C).VERILOG CODE FOR ASYNCHRONOUS DOWN COUNTER


Input clk;

Output [3:0]q,qbar;

Supply1 vdd;


JK_FF jkff1(vdd,vdd,qbar[0],q[1],qbar[1]);



endmodule


Input clk;

Input JK;

Output q,qbar;

Reg q,qbar;

Initial



Begin

q=(J&(~q))|((~K)&q);

qbar=~q;

End

Endmodule



HDL 17ECL58

RESULT:-

Clock Q3 Q2 Q1 Q0

15 1 1 1 1

14 1 1 1 0

13 1 1 0 1

12 1 1 0 0

11 1 0 1 1

10 1 0 1 0

9 1 0 0 1

8 1 0 0 0

7 0 1 1 1

6 0 1 1 0

5 0 1 0 1

4 0 1 0 0

3 0 0 1 1

2 0 0 1 0

1 0 0 0 1

0 0 0 0 0



HDL 17ECL58

INTERFACING

1 Write HDL code to display messages on an alpha numeric LCD display.

VHDL CODE

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

USE WORK.LCD_GRAP.ALL;

ENTITY HEXKEY_LCD IS

PORT (

CLK: IN STD_LOGIC; -- 16 MHZ CLOCK

RESET: IN STD_LOGIC; -- MASTER RESET PIN

LCD_RW : OUT STD_LOGIC;

LCD_SELECT : OUT STD_LOGIC;

LCD_ENABLE : OUT STD_LOGIC;

ROW: IN STD_LOGIC_VECTOR(0 TO 3); -- THIS ARE THE ROW LINES

LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- GIVES REGISTERED

DATA OUTPUT

COL: INOUT STD_LOGIC_VECTOR(0 TO 3));

END HEXKEY_LCD;

ARCHITECTURE HEXKEY_BEH OF HEXKEY_LCD IS

TYPE KEYPAD_STATE_TYPE IS (WAIT_R_0, C3, C2, C1, C0, FOUND, SAMPLE,

WAIT_R_1); --

STATE NAMES

TYPE STATE_TYPE IS (INITIAL,DISPLAY,CLEAR,LOCATION,PUTCHAR);

SIGNAL STATE,NEXT_STATE: STATE_TYPE;

-- CLEAR SCREEN.

CONSTANT CLR: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000001";

-- DISPLAY ON, WITHOUT CURSOR.

CONSTANT DON: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00001100";

-- FUNCTION SET FOR 8-BIT DATA TRANSFER AND 2-LINE DISPLAY

CONSTANT SET: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00111000";

--FREQUENCY DIVIDER

CONSTANT BIG_DELAY: INTEGER :=16;

CONSTANT SMALL_DELAY: INTEGER :=2;

CONSTANT REG_SETUP: INTEGER :=1;

SIGNAL CS, NS: KEYPAD_STATE_TYPE; -- SIGNALS FOR CURRENT AND

NEXT STATES

SIGNAL DIV_REG: STD_LOGIC_VECTOR (16 DOWNTO 0); -- CLOCK DIVIDE

REGISTER

SIGNAL DCLK,DDCLK: STD_LOGIC; -- THIS HAS THE DIVIDED CLOCK.

SIGNAL COL_REG_VALUE: STD_LOGIC_VECTOR (0 TO 3);

SIGNAL R1: STD_LOGIC; -- ROW DETECTION SIGNAL

SIGNAL KEY_VALUE: STD_LOGIC_VECTOR (7 DOWNTO 0);



HDL 17ECL58

SIGNAL DATA: STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

R1 <= ROW(3) OR ROW(2) OR ROW(1) OR ROW(0);

---------------------------- BEGINING OF FSM1 (KEYPAD SCANNER) ---------------------

----------

SYNC_PROC: PROCESS (DCLK, RESET, KEY_VALUE) -- THIS IS THE

SYNCHRONOUS PART

BEGIN

IF (RESET = '0') THEN -- YOU MUST HAVE A RESET FOR FSM TO SYNTHESIZE

PROPERLY

CS <= WAIT_R_0;

ELSIF (DCLK'EVENT AND DCLK = '1') THEN

CS <= NS;

END IF;

END PROCESS;

COMB_PROC: PROCESS (CS, R1, COL_REG_VALUE) -- THIS IS THE

COMBINATIONAL PART

BEGIN

CASE CS IS

---------------------------------------------------------------------------------------------------

WHEN WAIT_R_0 => -- WAITS TILL A BUTTON IS PRESSED

COL <= "1111"; -- KEEP ALL COLUMNS ACTIVATED

IF R1 = '1' THEN -- A BUTTON WAS PRESSED. BUT WHICH ONE?

NS <= C3; -- LET'S FIND OUT

ELSE

NS <= WAIT_R_0;

END IF;

---------------------------------------------------------------------------------------------------

WHEN C3 => --

COL <= "0001"; -- ACTIVATE COLUMN 3

IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 3

NS <= C2; -- SO CHECK IF IT WAS IN COLUMN 2

ELSE NS <= FOUND; -- BUTTON WAS IN COLUMN 3

END IF;

---------------------------------------------------------------------------------------------------

WHEN C2 => --




ELSE

NS <= FOUND; -- BUTTON WAS IN COLUMN 2

END IF;

---------------------------------------------------------------------------------------------------

WHEN C1 => --



HDL 17ECL58




ELSE


END IF;

---------------------------------------------------------------------------------------------------

WHEN C0 => --


IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 0 ??

NS <= WAIT_R_0; -- SO THE BUTTON MUST HAVE BEEN DEPRESSED FAST

ELSE


END IF;

---------------------------------------------------------------------------------------------------

WHEN FOUND => --

COL <= COL_REG_VALUE;

IF R1 = '0' THEN -- THIS MEANS BUTTON IS DEPRESSED

NS <= WAIT_R_0; -- SO GO BACK TO INITIAL STATE

ELSE

NS <= SAMPLE; -- OTHERWISE WRITE THE KEY VALUE TO DATA REGISTER

END IF;

---------------------------------------------------------------------------------------------------

WHEN SAMPLE => -- THIS STATE WILL GENERATE A SIGNAL WITH ONE

CLOCK PERIOD FOR SAMPLING


NS <= WAIT_R_1; -- OTHERWISE WAIT TILL BUTTON IS PRESSED

---------------------------------------------------------------------------------------------------

WHEN WAIT_R_1 => --


IF R1 = '0' THEN -- THIS MEANS BUTTON WAS DEPRESSED


ELSE


END IF;

---------------------------------------------------------------------------------------------------

END CASE;

END PROCESS;

---------------------------------------------------------------------------------------------------

WRITE_DATA: PROCESS (DCLK, CS, KEY_VALUE) -- WRITE VALID DATA TO

REGISTER

BEGIN

IF DCLK'EVENT AND DCLK = '0' THEN -- ON THE FALLING EDGE

IF CS = FOUND THEN

DATA <= KEY_VALUE;



HDL 17ECL58

END IF;

END IF;

END PROCESS; -- WRITE_DATA

---------------------------------------------------------------------------------------------------

COL_REG: PROCESS (DCLK, CS, COL) -- THIS IS THE COLUMN VALUE

REGISTER

BEGIN

IF (DCLK'EVENT AND DCLK = '0') THEN -- REGISTER THE COL VALUE ON

THE FALLING EDGE

IF (CS = C3 OR CS = C2 OR CS = C1 OR CS = C0) THEN -- PROVIDED WE'RE IN

STATES C3 THRU C0 ONLY

COL_REG_VALUE <= COL; -- OTHERWISE THE COLUMN VALUE IS NOT

VALID

END IF;

END IF;

END PROCESS; -- COL_REG

---------------------------------------------------------------------------------------------------

DECODER: PROCESS(ROW, COL_REG_VALUE) -- DECODES BINARY VALUE

OF PRESSED KEY FROM ROW AND

COLUMN

VARIABLE CODE: STD_LOGIC_VECTOR (0 TO 7);

BEGIN

CODE := (ROW & COL_REG_VALUE);

CASE CODE IS

-- COL

-- ROW 0 0123

WHEN "00010001" => KEY_VALUE <= ZERO;--KEY 0

WHEN "00010010" => KEY_VALUE <= ONE;--KEY 1

WHEN "00010100" => KEY_VALUE <= TWO;--KEY 2

WHEN "00011000" => KEY_VALUE <= THREE;--KEY 3

-- ROW 1

WHEN "00100001" => KEY_VALUE <= FOUR;--KEY 4

WHEN "00100010" => KEY_VALUE <= FIVE;--KEY 5

WHEN "00100100" => KEY_VALUE <= SIX;--KEY 6

WHEN "00101000" => KEY_VALUE <= SEVEN;--KEY 7

-- ROW 2

WHEN "01000001" => KEY_VALUE <= EIGHT;--KEY 8

WHEN "01000010" => KEY_VALUE <= NINE;--KEY 9

WHEN "01000100" => KEY_VALUE <= A;--KEY A

WHEN "01001000" => KEY_VALUE <= B;--KEY B

-- ROW 3

WHEN "10000001" => KEY_VALUE <= C;--KEY C

WHEN "10000010" => KEY_VALUE <= D;--KEY D

WHEN "10000100" => KEY_VALUE <= E;--KEY E

WHEN "10001000" => KEY_VALUE <= F;--KEY F



HDL 17ECL58

WHEN OTHERS => KEY_VALUE <= SPACE; -- JUST IN CASE

END CASE;

END PROCESS; -- DECODER

---------------------------- END OF FSM1 (KEYPAD SCANNER) -----------------------------

----------

-- SELECT THE APPROPRIATE LINES FOR SETTING FREQUENCY

CLK_DIV: PROCESS (CLK, DIV_REG) -- CLOCK DIVIDER

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

DIV_REG <= DIV_REG + 1;

END IF;

END PROCESS;

DCLK <= DIV_REG(8);

DDCLK<=DIV_REG(10);

---------------------------- END OF CLOCK DIVIDER -------------------------------------------

------

LCD_RW<='0';

PROCESS (DDCLK,RESET)

VARIABLE COUNT: INTEGER RANGE 0 TO BIG_DELAY;

VARIABLE C1 : STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

IF RESET = '0' THEN

STATE<=INITIAL;

COUNT:=0;

LCD_ENABLE<='0';

LCD_SELECT<='0';

C1 := "01111111";

ELSIF DDCLK'EVENT AND DDCLK = '1' THEN

CASE STATE IS

WHEN INITIAL => -- TO SET THE FUNCTION

IF COUNT=REG_SETUP THEN

LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=SET;

LCD_SELECT<='0';

IF COUNT=SMALL_DELAY THEN

STATE<=DISPLAY;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;

WHEN DISPLAY => -- TO SET DISPLAY ON




HDL 17ECL58

LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=DON;

LCD_SELECT<='0';


STATE<=CLEAR;COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;

WHEN CLEAR => -- CLEAR THE SCREEN


LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=CLR;

LCD_SELECT<='0';

IF COUNT=BIG_DELAY THEN

STATE<=LOCATION;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;

WHEN LOCATION => -- CLEAR THE SCREEN


LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

IF COUNT=0 THEN

IF C1="10001111" THEN

C1:="11000000";

ELSIF C1="11001111" THEN

C1:="10000000";

ELSE

C1:=C1+'1';

END IF;

END IF;

LCD_DATA <= C1 ;

LCD_SELECT<='0';


STATE<=PUTCHAR;

COUNT:=0;



HDL 17ECL58

ELSE

COUNT:=COUNT+1;

END IF;

WHEN PUTCHAR=> -- DISPLAY THE CHARACTER ON THE LCD


LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

CASE C1 IS

WHEN "10000000" => LCD_DATA<= H ;--SIGLE LINE

WHEN "10000001" => LCD_DATA<= E ;--SIGLE LINE

WHEN "10000010" => LCD_DATA<= X ;--SIGLE LINE

WHEN "10000011" => LCD_DATA<= SPACE ;--SIGLE LINE


WHEN "10000101" => LCD_DATA<= K ;--SIGLE LINE


WHEN "10000111" => LCD_DATA<= Y ;--SIGLE LINE

WHEN "10001000" => LCD_DATA<= B ;

WHEN "10001001" => LCD_DATA<= O ;

WHEN "10001010" => LCD_DATA<= A ;

WHEN "10001011" => LCD_DATA<= R ;

WHEN "10001100" => LCD_DATA<= D ;

WHEN "10001101" => LCD_DATA<= SPACE ;


WHEN "10001111" => LCD_DATA<= SPACE;

WHEN "11000000" => LCD_DATA<= K ;--SIGLE LINE


WHEN "11000010" => LCD_DATA<= Y ;--SIGLE LINE

WHEN "11000011" => LCD_DATA<= P ;--SIGLE LINE

WHEN "11000100" => LCD_DATA<= R ;--SIGLE LINE


WHEN "11000110" => LCD_DATA<= S ;--SIGLE LINE


WHEN "11001000" => LCD_DATA<= E ;

WHEN "11001001" => LCD_DATA<= D ;


-- WHEN "11001011" => LCD_DATA<= RIGHT_ARROW ;


WHEN "11001101" => LCD_DATA<= DATA ;



WHEN OTHERS => NULL;

END CASE ;

LCD_SELECT<='1';



HDL 17ECL58


STATE<=LOCATION;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;

END CASE;

END IF;

END PROCESS;

END HEXKEY_BEH;

VERILOG CODE

MODULE SEVEN_VERILOG(

INPUT CLK,

OUTPUT REG [3:0] CNTR,

OUTPUT REG [7:0] SEVEN

);

REG [20:0]CLK_DIV;

REG CLK1;

REG [1:0] STATE;

ALWAYS@(POSEDGE CLK)

BEGIN

CLK_DIV= CLK_DIV+1;

CLK1=CLK_DIV[19];

END

ALWAYS @(POSEDGE CLK1)

STATE = STATE +1;

ALWAYS @(STATE)

BEGIN

CASE(STATE) // *GFEDCBA

2'B00: SEVEN=8'B01110110;

2'B01: SEVEN=8'B01111001;

2'B10: SEVEN=8'B00111000;

2'B11: SEVEN=8'B01110011;

DEFAULT: SEVEN=8'B01111111;

ENDCASE



HDL 17ECL58

END

ALWAYS@(STATE)

BEGIN

CASE(STATE)

2'B00: CNTR=4'B1110;

2'B01: CNTR=4'B1101;

2'B10: CNTR=4'B1011;

2'B11: CNTR=4'B0111;

DEFAULT: CNTR=4'B1111;

ENDCASE

END

ENDMODULE



HDL 17ECL58

2. Write HDL code to interface Hex key pad and display the key code on seven segment

display.

VHDL CODING

------------------------------------

--CODE FOR SIMULATING 16 KEYS USING

--KEYBOARD PROVIDED ON SPARTAN BOARD

------------------------------------

LIBRARY IEEE;


USE IEEE.STD_LOGIC_ARITH.ALL;


ENTITY KEY_40 IS

PORT ( SCAN_L : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

READ_L_IN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

CLK : IN STD_LOGIC;

DISP_CNT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

DISP : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));

END KEY_40;

ARCHITECTURE BEHAVIORAL OF KEY_40 IS

SIGNAL DISP1 : STD_LOGIC_VECTOR(6 DOWNTO 0);

SIGNAL SCAN_L_SIG : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL CLK_DIV : STD_LOGIC_VECTOR( 11 DOWNTO 0);

SIGNAL CLK_4K : STD_LOGIC;

SIGNAL CNT_2BIT : STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL READ_L : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

---------------------------

--CLOCK DIVISION TO 4KHZ

--------------------------

PROCESS(CLK)

BEGIN

IF CLK='1' AND CLK'EVENT THEN

CLK_DIV <= CLK_DIV + '1';

END IF;

END PROCESS;

---------------------------

CLK_4K <= CLK_DIV(11);

---------------------------

-- 2 BIT COUNTER

--------------------------

PROCESS(CLK_4K)

BEGIN

IF CLK_4K = '1' AND CLK_4K'EVENT THEN



HDL 17ECL58

CNT_2BIT <= CNT_2BIT + '1';

END IF;

END PROCESS;

--------------------------

-- SCANNING THE LINES

--------------------------

PROCESS(CNT_2BIT)

BEGIN

CASE CNT_2BIT IS

WHEN "00" => SCAN_L_SIG <= "0001";

WHEN "01" => SCAN_L_SIG <= "0010";

WHEN "10" => SCAN_L_SIG <= "0100";

WHEN "11" => SCAN_L_SIG <= "1000";


END CASE;

END PROCESS;

------------------------------

--READ_L <= NOT READ_L_IN;

--SCAN_L <= NOT SCAN_L_SIG;

READ_L <= READ_L_IN;

SCAN_L <= SCAN_L_SIG;

DISP_CNT <= "1110";

--READING THE LINES

-------------------------------

PROCESS(SCAN_L_SIG,READ_L)

BEGIN

CASE SCAN_L_SIG IS

WHEN "0001" => CASE READ_L IS

WHEN "0001" => DISP1 <= "1111110";

WHEN "0010" => DISP1 <= "0110011";

WHEN "0100" => DISP1 <= "1111111";

WHEN "1000" => DISP1 <= "1001110";

WHEN OTHERS=> DISP1 <= "0000000";

END CASE;


WHEN "0001" => DISP1 <= "0110000";

WHEN "0010" => DISP1 <= "1011011";

WHEN "0100" => DISP1 <= "1111011";

WHEN "1000" => DISP1 <= "0111101";


END CASE;


WHEN "0001" => DISP1 <= "1101101";

WHEN "0010" => DISP1 <= "1011111";

WHEN "0100" => DISP1 <= "1110111";



HDL 17ECL58

WHEN "1000" => DISP1 <= "1001111";


END CASE;


WHEN "0001" => DISP1 <= "1111001";

WHEN "0010" => DISP1 <= "1110000";

WHEN "0100" => DISP1 <= "0011111";

WHEN "1000" => DISP1 <= "1000111";


END CASE;

WHEN OTHERS=> NULL;

END CASE;

END PROCESS;

DISP<= DISP1;

END BEHAVIORAL;

VERILOG CODE

MODULE KEYPAD_VERILOG(

INPUT CLK,

INPUT [3:0] KEY_RET,

OUTPUT REG [3:0] KEY_SCAN,

OUTPUT REG [3:0] CNTR,

OUTPUT REG [7:0] SEVEN

);

REG [20:0]CLK_DIV;

REG CLK1;

REG [3:0] I;

INITIAL

BEGIN

KEY_SCAN =4'B1110;

SEVEN=8'B01111111;

CNTR=4'B1110;

END


BEGIN

CLK_DIV= CLK_DIV+1;

CLK1=CLK_DIV[15];

END

ALWAYS@(POSEDGE CLK1)

BEGIN



HDL 17ECL58

CASE({KEY_SCAN,KEY_RET})

8'B1110_1110: SEVEN=8'B00111111;

8'B1110_1101: SEVEN=8'B00000110;

8'B1110_1011: SEVEN=8'B01011011;

8'B1110_0111: SEVEN=8'B01001111;

8'B1101_1110: SEVEN=8'B01100110;

8'B1101_1101: SEVEN=8'B01101101;

8'B1101_1011: SEVEN=8'B01111101;

8'B1101_0111: SEVEN=8'B00000111;

8'B1011_1110: SEVEN=8'B01111111;

8'B1011_1101: SEVEN=8'B01100111;

8'B1011_1011: SEVEN=8'B01110111;

8'B1011_0111: SEVEN=8'B01111100;

8'B0111_1110: SEVEN=8'B00111001;

8'B0111_1101: SEVEN=8'B01011110;

8'B0111_1011: SEVEN=8'B01111001;

8'B0111_0111: SEVEN=8'B01110001;

ENDCASE

CNTR=4'B1110;

END

ALWAYS @(POSEDGE CLK1)

BEGIN

IF(KEY_SCAN==4'B1110)

KEY_SCAN=4'B1101;

ELSE IF(KEY_SCAN==4'B1101)

KEY_SCAN=4'B1011;


KEY_SCAN=4'B0111;


KEY_SCAN=4'B1110;

END

ENDMODULE



HDL 17ECL58

3 A. Write HDL code to control speed, direction of DC and Stepper motor.

VHDL CODE

LIBRARY IEEE;



LIBRARY UNISIM;

USE UNISIM.VCOMPONENTS.ALL;

ENTITY DCMOTOR IS

GENERIC(BITS : INTEGER := 8 ); -- NUMBER OF BITS USED FOR DUTY CYCLE.

-- ALSO DETERMINES PWM PERIOD.

PORT ( CLK: IN STD_LOGIC; -- 4 MHZ CLOCK

RESET,EN: IN STD_LOGIC; -- MASTER RESET PIN

PWM : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);

RLY: OUT STD_LOGIC;

ROW: IN STD_LOGIC_VECTOR(0 TO 3) ); -- THIS ARE THE ROW LINES

END DCMOTOR;

ARCHITECTURE DCMOTOR1 OF DCMOTOR IS

SIGNAL COUNTER : STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0):="11111110";


REGISTER

SIGNAL DCLK,DDCLK,DATAIN,TICK: STD_LOGIC; -- THIS HAS THE DIVIDED

CLOCK.

SIGNAL DUTY_CYCLE: INTEGER RANGE 0 TO 255;

SIGNAL ROW1 : STD_LOGIC_VECTOR(0 TO 3); -- THIS ARE THE ROW LINES

BEGIN



BEGIN



END IF;

END PROCESS;

DDCLK<=DIV_REG(12);


------

TICK <= ROW(0) AND ROW(1) AND ROW(2) AND ROW(3);

PROCESS(TICK)

BEGIN

IF FALLING_EDGE(TICK) THEN

CASE ROW IS

WHEN "1110" => DUTY_CYCLE <= 255 ; --MOTOR SPEED 1






HDL 17ECL58

WHEN OTHERS => DUTY_CYCLE <= 100;

END CASE;

END IF;

END PROCESS;

PROCESS(DDCLK, RESET)

BEGIN

IF RESET = '0' THEN

COUNTER <= (OTHERS => '0');

PWM<="01";

ELSIF (DDCLK'EVENT AND DDCLK = '1') THEN

COUNTER <= COUNTER + 1;

IF COUNTER >= DUTY_CYCLE THEN

PWM(1) <= '0';

ELSE

PWM(1) <= '1';

END IF; END IF;

END PROCESS;

-- RLY<='1'; --MOTOR DIRECTION CONTROL- CLOCK WISE

RLY<='0';--MOTOR DIRECTION CONTROL- COUNTER CLOCK WISE

END DCMOTOR1;



HDL 17ECL58

3 B. WRITE A VHDL CODE TO CONTROL SPEED, DIRECTION OF STEPPER

MOTOR.

VHDL CODE

LIBRARY IEEE;




ENTITY STEPPER IS

PORT ( DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

CLK,RESET : IN STD_LOGIC);

END STEPPER;

ARCHITECTURE BEHAVIORAL OF STEPPER IS

SIGNAL CLK_DIV : STD_LOGIC_VECTOR(20 DOWNTO 0);

SIGNAL CLK_INT: STD_LOGIC;

SIGNAL SHIFT_REG : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

PROCESS(CLK)

BEGIN

IF RISING_EDGE (CLK) THEN

CLK_DIV <= CLK_DIV + '1';

END IF;

END PROCESS;

CLK_INT <= CLK_DIV(16);

PROCESS(RESET,CLK_INT)

BEGIN

IF RESET='0' THEN

SHIFT_REG <= "0001";

ELSIF RISING_EDGE(CLK_INT) THEN

SHIFT_REG <= SHIFT_REG(0) & SHIFT_REG(3 DOWNTO 1);

END IF;

END PROCESS;

DOUT <= SHIFT_REG;

END BEHAVIORAL;



HDL 17ECL58

4. WRITE A VHDL CODE TO ACCEPT 8 CHANNEL ANALOG SIGNAL,

TEMPERATURE SENSORS AND DISPLAY THE DATA ON LCD PANEL OR

SEVEN SEGMENT DISPLAY.

VHDL CODING

LIBRARY IEEE;




LIBRARY UNISIM;

USE UNISIM.VCOMPONENTS.ALL;

ENTITY ADC_LCD IS


RESET: IN STD_LOGIC; -- MASTER RESET PIN

INTR: IN STD_LOGIC;

ADC_OUT: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

CS,RD,WR:OUT STD_LOGIC;




LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); -- GIVES REGISTERED

DATA OUTPUT

END ADC_LCD;

ARCHITECTURE ADC_BEH OF ADC_LCD IS



-- CLEAR SCREEN.






--FREQUENCY DIVIDER

SIGNAL COUNTER : STD_LOGIC_VECTOR(18 DOWNTO 0);

SIGNAL CLK_DIV :STD_LOGIC;




SIGNAL DIGITAL_DATA1,DATA1,DATA2: STD_LOGIC_VECTOR(7 DOWNTO

0);

SIGNAL DIGITAL_DATA : INTEGER RANGE 0 TO 255;

SIGNAL NTR :STD_LOGIC;

BEGIN



HDL 17ECL58

IBUF_INST : IBUF

-- EDIT THE FOLLOWING GENERIC TO SPECIFY THE I/O STANDARD FOR

THIS PORT.

GENERIC MAP (

IOSTANDARD => "LVCMOS25")

PORT MAP (

O => NTR, -- BUFFER OUTPUT

I => INTR -- BUFFER INPUT (CONNECT DIRECTLY TO TOP-LEVEL PORT));

PROCESS(CLK)

BEGIN

IF CLK='1' AND CLK'EVENT THEN

COUNTER<=COUNTER+'1';

END IF;

END PROCESS;

CLK_DIV<=COUNTER(7);

CS <='0';

WR <=NTR;

DIGITAL_DATA1 <= ADC_OUT ;

RD <='0';

DIGITAL_DATA<=CONV_INTEGER(DIGITAL_DATA1) ;

PROCESS(DIGITAL_DATA)

BEGIN

CASE (DIGITAL_DATA) IS

WHEN 0 TO 100 => DATA1 <= ONE ; DATA2 <= NINE ;

WHEN 101 TO 110 => DATA1 <= TWO ; DATA2 <= ZERO ;

WHEN 111 TO 120 => DATA1 <= TWO ; DATA2 <= ONE ;

WHEN 121 TO 130 => DATA1 <= TWO ; DATA2 <= TWO ;

WHEN 131 TO 140 => DATA1 <= TWO ; DATA2 <= THREE ;

WHEN 141 TO 150 => DATA1 <= TWO ; DATA2 <= FOUR ;

WHEN 151 TO 160 => DATA1 <= TWO ; DATA2 <= FIVE ;

WHEN 161 TO 170 => DATA1 <= TWO ; DATA2 <= SIX ;

WHEN 171 TO 180 => DATA1 <= TWO ; DATA2 <= SEVEN ;

WHEN 181 TO 190 => DATA1 <= TWO ; DATA2 <= EIGHT ;

WHEN 191 TO 200 => DATA1 <= TWO ; DATA2 <= NINE ;

WHEN 201 TO 205 => DATA1 <= THREE ; DATA2 <= ZERO ;

WHEN 206 TO 210 => DATA1 <= THREE ; DATA2 <= ONE ;

WHEN 211 TO 215 => DATA1 <= THREE ; DATA2 <= TWO ;

WHEN 216 TO 220 => DATA1 <= THREE ; DATA2 <= THREE ;

WHEN 221 TO 225 => DATA1 <= THREE ; DATA2 <= FOUR ;

WHEN 226 TO 230 => DATA1 <= THREE ; DATA2 <= FIVE ;

WHEN 231 TO 235 => DATA1 <= THREE ; DATA2 <= SIX ;

WHEN 236 TO 240 => DATA1 <= THREE ; DATA2 <= SEVEN ;

WHEN 241 TO 245 => DATA1 <= THREE ; DATA2 <= EIGHT ;

WHEN 246 TO 250 => DATA1 <= THREE ; DATA2 <= NINE ;

WHEN OTHERS => DATA1 <= FOUR ; DATA2 <= ZERO ;



HDL 17ECL58

END CASE;

END PROCESS;

LCD_RW<='0';

PROCESS (CLK_DIV,RESET)



BEGIN

IF RESET = '1' THEN

STATE<=INITIAL;

COUNT:=0;

LCD_ENABLE<='0';

LCD_SELECT<='0';

C1 := "01111111";

ELSIF CLK_DIV'EVENT AND CLK_DIV = '1' THEN

CASE STATE IS



LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=SET;

LCD_SELECT<='0';


STATE<=DISPLAY;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;



LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=DON;

LCD_SELECT<='0';


STATE<=CLEAR;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;





HDL 17ECL58

LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

LCD_DATA<=CLR;

LCD_SELECT<='0';


STATE<=LOCATION;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;



LCD_ENABLE<='1';

ELSE

LCD_ENABLE<='0';

END IF;

IF COUNT=0 THEN

IF C1="10001111" THEN

C1:="10000000";

ELSE

C1:=C1+'1';

END IF;

END IF;

LCD_DATA <= C1 ;

LCD_SELECT<='0';


STATE<=PUTCHAR;

COUNT:=0; ELSE

COUNT:=COUNT+1;

END IF;



LCD_ENABLE<='1';

ELSE LCD_ENABLE<='0';

END IF;

CASE C1 IS

WHEN "10000000" => LCD_DATA<= A ;

WHEN "10000001" => LCD_DATA<= D ;

WHEN "10000010" => LCD_DATA<= C ;


WHEN "10000100" => LCD_DATA<= V ;

WHEN "10000101" => LCD_DATA<= O ;

WHEN "10000110" => LCD_DATA<= L ;



HDL 17ECL58

WHEN "10000111" => LCD_DATA<= T ;

WHEN "10001000" => LCD_DATA<= A ;

WHEN "10001001" => LCD_DATA<= G ;

WHEN "10001010" => LCD_DATA<= E ;


WHEN "10001100" => LCD_DATA<= EQUAL ;

WHEN "10001101" => LCD_DATA<= DATA1 ;

WHEN "10001110" => LCD_DATA<= DOT ;

WHEN "10001111" => LCD_DATA<= DATA2;


















END CASE ;

LCD_SELECT<='1';


STATE<=LOCATION;

COUNT:=0;

ELSE

COUNT:=COUNT+1;

END IF;

END CASE;

END IF;

END PROCESS;

END ADC_BEH;



HDL 17ECL58

5 A . WRITE A VHDL CODE TO GENERATE SINE WAVEFORMS USING DAC

CHANGE THE FREQUENCY ANDAMPLITUDE.

VHDL CODE FOR SINE WAVE

LIBRARY IEEE;




ENTITY DIGITAL_SINE_WAVE IS

PORT ( CLK : IN STD_LOGIC;

RST : IN STD_LOGIC;

DAC_OUT : OUT STD_LOGIC_VECTOR(0 TO 7));

END DIGITAL_SINE_WAVE ;

ARCHITECTURE BEHAVIORAL OF DIGITAL_SINE_WAVE IS

SIGNAL I: INTEGER RANGE 0 TO 23;

TYPE LOOK_UP IS ARRAY(0 TO 23) OF STD_LOGIC_VECTOR(7 DOWNTO 0);

CONSTANTSINE_LOOKUP: LOOK_UP:

=(“01111111”,”10100000”,10111110”,”11011001”,”11101101”,

”11111001”,”11111110”,--0 TO 90

“11111001”,”11101101”,”11011001”,”10111110”,”10100000”,”01111111”,--TILL

180

“01011110”,”00111111”,”00100101”,”00010001”,”00000100”,”00000000”,--TILL

270

“00000100”,”00010001”,”00100101”,”00111111”,”01011110”);

SIGNAL TEMP : STD_LOGIC_VECTOR(2 DOWNTO 0):=”000”;

BEGIN

PROCESS(CLK)

BEGIN

IF RISING_EDGE(CLK) THEN

TEMP <= TEMP + '1' ;

END IF;

END PROCESS;

PROCESS(TEMP(2))

BEGIN

IF TEMP(2)= '1' AND TEMP(2)‟EVENT THEN

IF RST='1' THEN

DAC <= "00000000";

ELSE

I<I+1;

DAC<=SINE_LOOKUP(I);

IF I=23 THEN

I<=0;

END IF;

END IF;

END PROCESS;

END BEHAVIORAL;



HDL 17ECL58

5 B. WRITE A VHDL CODE TO GENERATE SQUARE WAVEFORMS USING

DAC CHANGE THE FREQUENCY AND AMPLITUDE.

VHDL CODE

LIBRARY IEEE;




ENTITY SQUARE_WAVE IS


RST : IN STD_LOGIC;


END SQUARE_WAVE;

ARCHITECTURE BEHAVIORAL OF SQUARE_WAVE IS

SIGNAL TEMP : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL COUNTER : STD_LOGIC_VECTOR(0 TO 7);

SIGNAL EN :STD_LOGIC;

BEGIN

PROCESS(CLK)

BEGIN



END IF;

END PROCESS;

PROCESS(TEMP(3))

BEGIN

IF RST='1' THEN

COUNTER <= "00000000";

ELSIF RISING_EDGE(TEMP(3)) THEN

IF COUNTER<255 AND EN='0' THEN

COUNTER <= COUNTER + 1 ;

EN<='0';

DAC_OUT <="00000000"; --DAC_OUT<=COUNTER;(FOR TRIANGULAR

WAVE)

ELSIF COUNTER=0 THEN

EN<='0';

ELSE

EN<='1';

COUNTER <= COUNTER-1;

DAC_OUT <="11111111"; --DAC_OUT<=COUNTER;(FOR TRIANGULAR

WAVE)

END IF;

END IF;

END PROCESS;

END BEHAVIORAL;



HDL 17ECL58

VERILOG CODE FOR SQUARE WAVE

MODULE SQR_WAVE(

INPUT CLK,

OUTPUT REG [7:0] DOUT

);

REG [7:0]TEMP = 8'B0;

REG [25:0]DIVCLK;

REG CLK1;


BEGIN

DIVCLK = DIVCLK+1;

CLK1 = DIVCLK[8];

END

ALWAYS@(POSEDGE CLK1)

BEGIN

TEMP = ~TEMP;

DOUT = TEMP;

END

ENDMODULE



HDL 17ECL58

5 C. WRITE A VHDL CODE TO GENERATE TRAINGULAR WAVEFORMS

USING DAC CHANGE THE FREQUENCY AND AMPLITUDE.

VHDL CODE

LIBRARY IEEE;




ENTITY TRIANGULAR_WAVE IS


RST : IN STD_LOGIC;


END TRIANGULAR_WAVE ;

ARCHITECTURE BEHAVIORAL OF TRIANGULAR_WAVE IS




BEGIN

PROCESS(CLK)

BEGIN



END IF;

END PROCESS;

PROCESS(TEMP(3))

BEGIN

IF RST='1' THEN

COUNTER <= "000000000";



IF COUNTER(0)='1' THEN

DAC_OUT <=COUNTER(1 TO 8);

ELSE

DAC_OUT <=NOT(COUNTER(1 TO 8));

END IF;

END IF;

END PROCESS; END BEHAVIORAL;



HDL 17ECL58

VERILOG CODE FOR TRIANGULAR

MODULE TRI_WAVE(

INPUT CLK,

OUTPUT REG [7:0] DACOUT

);

REG [7:0] TEMP=8'B00000000;

REG A=1;

ALWAYS@ (POSEDGE CLK)

BEGIN

IF ((TEMP==8'D0)|| (TEMP ==8'D255))

A=~A;

IF (A==1)

TEMP =TEMP+1;

IF(A==0)

TEMP = TEMP-1;

DACOUT =TEMP;

ENDMODULE



HDL 17ECL58

5 D. WRITE A VHDL CODE TO GENERATE RAMP WAVEFORMS USING

DAC CHANGE THE FREQUENCY AND AMPLITUDE.

VHDL CODE

LIBRARY IEEE;




ENTITY RAMP_WAVE IS


RST : IN STD_LOGIC;


END RAMP_WAVE;

ARCHITECTURE BEHAVIORAL OF RAMP_WAVE IS




BEGIN

PROCESS(CLK)

BEGIN



END IF;

END PROCESS;

PROCESS(TEMP(3))

BEGIN

IF RST='1' THEN

COUNTER <= "00000000";



END IF;

END PROCESS;

DAC_OUT <=COUNTER;

END BEHAVIORAL;



HDL 17ECL58

5 E. WRITE A VHDL CODE TO GENERATE SAWTOOTH WAVEFORMS

USING DAC CHANGE THE FREQUENCY AND AMPLITUDE.

VHDL CODE

LIBRARY IEEE;




ENTITY SWATOOTH_WAVE IS


RST : IN STD_LOGIC;


END SWATOOTH_WAVE;

ARCHITECTURE BEHAVIORAL OF SWATOOTH_WAVE IS




BEGIN

PROCESS(CLK)

BEGIN



END IF;

END PROCESS;

PROCESS(TEMP(3))

BEGIN

IF RST='1' THEN

COUNTER <= "00000000";



END IF;

END PROCESS;

DAC_OUT <=COUNTER;

END BEHAVIORAL;



HDL 17ECL58

VERILOG CODE FOR SAWTOOTH WAVE

MODULE SAW(

INPUT CLK,

OUTPUT REG [7:0] DACOUT

);

REG [7:0] COUNTER;

ALWAYS@ (POSEDGE CLK)

BEGIN

COUNTER = COUNTER +1;

DACOUT=COUNTER;

END

ENDMODULE



HDL 17ECL58

6. WRITE A VHDL CODE TO SIMULATE ELEVATOR OPERATIONS.

VHDL CODE

LIBRARY IEEE;




ENTITY ELEVATOR IS

GENERIC(BITS : INTEGER := 8 ); -- NUMBER OF BITS USED FOR DUTY CYCLE.

-- ALSO DETERMINES PWM PERIOD.


RESET,EN: IN STD_LOGIC; -- MASTER RESET PIN


PWM : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);



ROW: IN STD_LOGIC_VECTOR(0 TO 3); -- THIS ARE THE ROW LINES

LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- GIVES REGISTERED

DATA OUTPUT

COL: INOUT STD_LOGIC_VECTOR(0 TO 3));

END ELEVATOR;

ARCHITECTURE RTL OF ELEVATOR IS

SIGNAL COUNTER : STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0):="00000000";

TYPE KEYPAD_STATE_TYPE IS (WAIT_R_0, C3, C2, C1, C0, FOUND, SAMPLE,

WAIT_R_1);

-- STATE NAMES



-- CLEAR SCREEN.






--FREQUENCY DIVIDER




SIGNAL CS, NS: KEYPAD_STATE_TYPE; -- SIGNALS FOR CURRENT AND

NEXT STATES

SIGNAL DUTY_CYCLE,DUTY_CYCLE1 : STD_LOGIC_VECTOR(BITS - 1

DOWNTO 0);


REGISTER



HDL 17ECL58

SIGNAL DCLK,DDCLK: STD_LOGIC; -- THIS HAS THE DIVIDED CLOCK.

SIGNAL COL_REG_VALUE: STD_LOGIC_VECTOR (0 TO 3);

SIGNAL R1,CLK_D,START,STOP: STD_LOGIC; -- ROW DETECTION SIGNAL

SIGNAL KEY_VALUE1,FLOOR,KEY_VALUE: INTEGER RANGE 0 TO 15;

SIGNAL DATA,DATA1,FLOOR_NUM: STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL TEMP1,TEMP2,TEMP3,TEMP4: STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL TEMP5,TEMP6,TEMP7,TEMP8: STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

--CLK_OUT <= DCLK;

R1 <= ROW(3) OR ROW(2) OR ROW(1) OR ROW(0);

---------------------------- BEGINING OF FSM1 (KEYPAD SCANNER) ---------------------

----------

SYNC_PROC: PROCESS (DCLK, RESET, KEY_VALUE) -- THIS IS THE

SYNCHRONOUS PART

BEGIN

IF (RESET = '0') THEN -- YOU MUST HAVE A RESET FOR FSM TO SYNTHESIZE

PROPERLY

CS <= WAIT_R_0;

ELSIF (DCLK'EVENT AND DCLK = '1') THEN

CS <= NS;

END IF; END PROCESS;

COMB_PROC: PROCESS (CS, R1, COL_REG_VALUE) -- THIS IS THE

COMBINATIONAL PART

BEGIN

CASE CS IS

WHEN WAIT_R_0 => -- WAITS TILL A BUTTON IS PRESSED

COL <= "1111"; -- KEEP ALL COLUMNS ACTIVATED

IF R1 = '1' THEN -- A BUTTON WAS PRESSED. BUT WHICH ONE?

NS <= C3; -- LET'S FIND OUT

ELSE

NS <= WAIT_R_0;

END IF;

---------------------------------------------------------------------------------------------------

WHEN C3 => --




ELSE NS <= FOUND; -- BUTTON WAS IN COLUMN 3

END IF;

---------------------------------------------------------------------------------------------------

WHEN C2 => --




ELSE



HDL 17ECL58


END IF;

---------------------------------------------------------------------------------------------------

WHEN C1 => --




ELSE


END IF;

---------------------------------------------------------------------------------------------------

WHEN C0 => --


IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 0 ??

NS <= WAIT_R_0; -- SO THE BUTTON MUST HAVE BEEN DEPRESSED FAST

ELSE


END IF;

---------------------------------------------------------------------------------------------------

WHEN FOUND => --


IF R1 = '0' THEN -- THIS MEANS BUTTON IS DEPRESSED


ELSE

NS <= SAMPLE; -- OTHERWISE WRITE THE KEY VALUE TO DATA REGISTER

END IF;

---------------------------------------------------------------------------------------------------

WHEN SAMPLE => -- THIS STATE WILL GENERATE A SIGNAL WITH ONE

CLOCK PERIOD FOR SAMPLING



---------------------------------------------------------------------------------------------------

WHEN WAIT_R_1 => --


IF R1 = '0' THEN -- THIS MEANS BUTTON WAS DEPRESSED


ELSE


END IF;

---------------------------------------------------------------------------------------------------

END CASE;

END PROCESS;

---------------------------------------------------------------------------------------------------

WRITE_DATA: PROCESS (DCLK, CS, KEY_VALUE) -- WRITE VALID DATA TO

REGISTER



HDL 17ECL58

BEGIN

IF DCLK'EVENT AND DCLK = '0' THEN -- ON THE FALLING EDGE

IF CS = FOUND THEN

KEY_VALUE <= KEY_VALUE1;

END IF;

END IF;

END PROCESS; -- WRITE_DATA

---------------------------------------------------------------------------------------------------

COL_REG: PROCESS (DCLK, CS, COL) -- THIS IS THE COLUMN VALUE

REGISTER

BEGIN

IF (DCLK'EVENT AND DCLK = '0') THEN -- REGISTER THE COL VALUE ON

THE FALLING EDGE

IF (CS = C3 OR CS = C2 OR CS = C1 OR CS = C0) THEN -- PROVIDED WE'RE IN

STATES C3 THRU C0 ONLY

COL_REG_VALUE <= COL; -- OTHERWISE THE COLUMN VALUE IS NOT

VALID

END IF;

END IF;

END PROCESS; -- COL_REG

---------------------------------------------------------------------------------------------------

DECODER: PROCESS(ROW, COL_REG_VALUE) -- DECODES BINARY VALUE

OF PRESSED KEY FROM ROW AND

COLUMN

VARIABLE CODE: STD_LOGIC_VECTOR (0 TO 7);

BEGIN

CODE := (ROW & COL_REG_VALUE);

CASE CODE IS

-- COL

-- ROW 0 0123

WHEN "00010001" => KEY_VALUE1 <= 0;

WHEN "00010010" => KEY_VALUE1 <= 1;

WHEN "00010100" => KEY_VALUE1 <= 2;

WHEN "00011000" => KEY_VALUE1 <= 3;

-- ROW 1

WHEN "00100001" => KEY_VALUE1 <= 4;

WHEN "00100010" => KEY_VALUE1 <= 5;

WHEN "00100100" => KEY_VALUE1 <= 6;

WHEN "00101000" => KEY_VALUE1 <= 7;

-- ROW 2

WHEN "01000001" => KEY_VALUE1 <= 8;

WHEN "01000010" => KEY_VALUE1 <= 9;

WHEN "01000100" => KEY_VALUE1 <= 10;

WHEN "01001000" => KEY_VALUE1 <= 11;

-- ROW 3



HDL 17ECL58

WHEN "10000001" => KEY_VALUE1 <= 12;

WHEN "10000010" => KEY_VALUE1 <= 13;

WHEN "10000100" => KEY_VALUE1 <= 14;

WHEN "10001000" => KEY_VALUE1 <= 15;

WHEN OTHERS => KEY_VALUE1 <= 0;

END CASE;

END PROCESS; -- DECODER

---------------------------- END OF FSM1 (KEYPAD SCANNER) -----------------------------

----------



BEGIN



END IF;

END PROCESS;

DCLK <= DIV_REG(8);

DDCLK<=DIV_REG(10);

CLK_D<=DIV_REG(22);


------

LCD_RW<='0';

PROCESS (DDCLK,RESET)



BEGIN

IF RESET = '0' THEN

STATE<=INITIAL;

COUNT:=0;

LCD_ENABLE<='0';

LCD_SELECT<='0';

C1 := "01111111";

ELSIF DDCLK'EVENT AND DDCLK = '1' THEN

CASE STATE IS



LCD_ENABLE<='1';


END IF;

LCD_DATA<=SET;

LCD_SELECT<='0';


STATE<=DISPLAY;

COUNT:=0;

ELSE COUNT:=COUNT+1;



HDL 17ECL58

END IF;



LCD_ENABLE<='1';


END IF;

LCD_DATA<=DON;

LCD_SELECT<='0';


STATE<=CLEAR;

COUNT:=0;


END IF;



LCD_ENABLE<='1';


END IF;

LCD_DATA<=CLR;

LCD_SELECT<='0';


STATE<=LOCATION;

COUNT:=0;


END IF;



LCD_ENABLE<='1';


END IF;

IF COUNT=0 THEN

IF C1="10001111" THEN

C1:="11000000";

ELSIF C1="11001111" THEN

C1:="10000000";

ELSE C1:=C1+'1';

END IF;

END IF;

LCD_DATA <= C1;

LCD_SELECT<='0';


STATE<=PUTCHAR;

COUNT:=0;


END IF;



HDL 17ECL58



LCD_ENABLE<='1';


END IF;

CASE C1 IS

WHEN "10000000" => LCD_DATA<= F ;--SIGLE LINE

WHEN "10000001" => LCD_DATA<= L ;--SIGLE LINE

WHEN "10000010" => LCD_DATA<= O ;--SIGLE LINE

WHEN "10000011" => LCD_DATA<= O ;--SIGLE LINE

WHEN "10000100" => LCD_DATA<= R ;--SIGLE LINE


WHEN "10000110" => LCD_DATA<= N ;--SIGLE LINE

WHEN "10000111" => LCD_DATA<= U ;--SIGLE LINE

WHEN "10001000" => LCD_DATA<= M ;

WHEN "10001001" => LCD_DATA<= B ;

WHEN "10001010" => LCD_DATA<= E ;

WHEN "10001011" => LCD_DATA<= R ;


WHEN "10001101" => LCD_DATA<= EQUAL ;

WHEN "10001110" => LCD_DATA<= FLOOR_NUM ;



WHEN "11000001" => LCD_DATA<= T ;--SIGLE LINE

WHEN "11000010" => LCD_DATA<= A ;--SIGLE LINE

WHEN "11000011" => LCD_DATA<= T ;--SIGLE LINE

WHEN "11000100" => LCD_DATA<= U ;--SIGLE LINE



WHEN "11000111" => LCD_DATA<= TEMP1 ;--SIGLE LINE

WHEN "11001000" => LCD_DATA<= TEMP2 ;









END CASE ;

LCD_SELECT<='1';


STATE<=LOCATION;

COUNT:=0;




HDL 17ECL58

END IF; END CASE; END IF; END PROCESS;

PROCESS(CLK_D,RESET)

VARIABLE COU : STD_LOGIC_VECTOR(1 DOWNTO 0);

VARIABLE START,STOP: STD_LOGIC; -- ROW DETECTION SIGNAL

BEGIN

IF RESET='0' THEN

COU:="00";

TEMP1 <= L ;

TEMP2 <= I ;

TEMP3 <= F ;

TEMP4 <= T ;

TEMP5 <= I ;

TEMP6 <= D ;

TEMP7 <= L ;

TEMP8 <= E ;

FLOOR_NUM <= ZERO ;

ELSIF RISING_EDGE(CLK_D) THEN

CASE KEY_VALUE IS

WHEN 0 => FLOOR_NUM <= ZERO ;

FLOOR <=0;

WHEN 1 => FLOOR_NUM <= ONE ;

FLOOR <=1;

WHEN 2 => FLOOR_NUM <= TWO ;

FLOOR <=2;

WHEN 3 => FLOOR_NUM <= THREE ;

FLOOR <=3;

WHEN 4 =>

TEMP1 <= D ;

TEMP2 <= O ;

TEMP3 <= O ;

TEMP4 <= R ;

TEMP5 <= O ;

TEMP6 <= P ;

TEMP7 <= E ;

TEMP8 <= N ;

WHEN 5 =>

TEMP1 <= D ;

TEMP2 <= O ;

TEMP3 <= O ;

TEMP4 <= R ;

TEMP5 <= C ;

TEMP6 <= L ;

TEMP7 <= O ;

TEMP8 <= S ;

WHEN 6 =>



HDL 17ECL58

START:='1';

STOP:='0';

WHEN 7 =>

STOP:='1';

START:='0';

WHEN OTHERS =>

TEMP1 <= I ;

TEMP2 <= D ;

TEMP3 <= L ;

TEMP4 <= E ;

TEMP5 <= K ;

TEMP6 <= E ;

TEMP7 <= Y ;

TEMP8 <= SPACE ;

END CASE;

IF START='1' THEN

IF COU=FLOOR THEN

START := '0';

COU:=COU;

TEMP7 <= "001100" & COU ;

ELSIF COU<=FLOOR THEN

COU:=COU + '1';

TEMP1 <= U ;

TEMP2 <= P ;

TEMP3 <= SPACE ;

TEMP4 <= SPACE ;

TEMP5 <= SPACE ;

TEMP6 <= "01111110" ;

TEMP7 <= "001100" & COU ;

TEMP8 <= SPACE ;

ELSIF COU>=FLOOR THEN

COU:=COU-'1';

TEMP1 <= D ;

TEMP2 <= O ;

TEMP3 <= W ;

TEMP4 <= N ;

TEMP5 <= SPACE ;

TEMP6 <= "01111111" ;

TEMP7 <= "001100" & COU ;

TEMP8 <= SPACE ;

END IF; END IF; END IF;

END PROCESS;

END RTL;



HDL 17ECL58

EXTRA EXPERIMENT

4. WRITE A VHDL CODE TO CONTROL EXTERNAL LIGHTS USING

RELAYS.

VHDL CODE

LIBRARY IEEE;




ENTITY EXTLIGHT IS

PORT ( CNTRL1,CNTRL2 : IN STD_LOGIC;

LIGHT : OUT STD_LOGIC);

END EXTLIGHT;

ARCHITECTURE BEHAVIORAL OF EXTLIGHT IS

BEGIN

LIGHT<= CNTRL1 OR CNTRL2 ;

END BEHAVIORAL;

VERILOG CODE

VERILOG CODE FOR RELAY

MODULE REALY_VERILOG(

INPUT A,B,

OUTPUT Y );

ASSIGN Y = A | B;

ENDMODULE

VSM‟S - VSMIT

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