JNTU ONLINE EXAMINATIONS [Mid 2 - lica] - Webs

c.

rder low Pass Butterworth filter is [02M02]

JNTU ONLINE EXAMINATIONS [Mid 2 - lica]

1. The general form of biquadratic function is given by H(s)= _ _ _ _ _ _ _ _ _ [01D01]

a.

b.

c.

d.

2. In general, the change is _ _ _ _ _ _ _ _ _ for the nth order filter. [01D02]

a. 20n db/decade

b. 40n db/decade

c. 60n db/decade

d. 80n db/decade

3. Disadvantage of the active filter ,it requires _ _ _ _ _ _ _ _ _ _ _. [01M01]

a. AC supply

b. Square wave generator

c. DC supply

d. Triangular wave generator

4. Active filter having one extra filter comparing passive filters is [01M02]

a. LPF

b. HPF

c. All pass filter

d. BPF

5. Voltage transfer function H(s) of an active filter is given by [01M03]

a. H(s)=Vi(s)/Vo(s)

b. H(s)=Vo(s)/Vi(s)

c. H(s)=Vo(s)-Vi(s)

d. H(s)=Vo(s)* Vi(s)

6. What is the active filter advantage over the passive filter. [01S01]

a. reduced size and increased weight. b.

increased size and increased weight. c.

reduced size and reduced weight. d.

increased size and reduced weight

7. In large quantities , the cost of the integrated circuit can be much _ _ _ _ _ _ _ _ _ than its equivalent passive network.

[01S02]

a. lower

b. high

c. equal

d. constant

8. Due to flexibility in _ _ _ _ _ _ _ _ _ and _ _ _ _ _ _ _ _ adjustments, the active filters can be easily tuned. [01S03]

a. frequency, gain

b. gain, frequency

c. tuner, frequency

d. gain, output voltage

9. Following is called as passive filter [01S04]

a. butter worth LPF

b. chebyschev LPF

c. cauver LPF

d. RC component LPF

10. For large circuit design procedures active filter is _ _ _ _ _ _ _ _ than that of the passive filters. [01S05]

a. harder

b. simple

c. not applicable

d. similar

11. Band stop or elimination filter conditions for pass bands [02M01]

a. 0

b. 0

c. 0 f

d. 0 f

12. Simplified equation of V1

non inverting input of op-amp for first o

a.

b.

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d.

is [03M01]

d.

13. Gain of the first order Butterworth L.P.F [02M03]

a.

b.

c.

d.

14. ØPhase of the 1st order Butterworth L.P.F [02M04]

a.

b.

c.

d.

15. Gain magnitude value at f=fH

in L.P.F [02M05]

a. Af

b. 0.707Af

c. f

d. 0.077Af

16. Butterworth filter is preferred because [02S01]

a. flat pass band, ripple stop band

b. ripple pass band, ripple stop band

c. flat pass band, flat stop band

d. ripple pass band, flat stop band

17. Cauver filter is preferred because [02S02]





18. Chebyshev filter is preferred because [02S03]





19. High pass filter representation with stop band and pass band is [02S04]

a.

b.

c.

0

d. 0 f

20. Band pass filter condition for stop band is [02S05]

a. 0

b. 0

c. 0 f

d. 0 f

21. Calculate Rf value in the second order HPF [03D01]

a.

b.

c.

d.

22. Calculate Rf in the second order HPF if [03D02]

a.

b.

c.

d.

23. The voltage gain magnitude equation for first order HPF is

a.

b.



0Hz and f

L = 400Hz [04M02]

ance R

2. The new resistance value of R

2 in BPF

24. Calculate frequency scaling for the example, convert the 1KHz cut off frequency of the LPF, to a cut off frequency of

1.6KHz. [03M02]

a. 0.625 b. 1.6 c. 160 d. 62.5

25. Design a HPF at a cut off frequency of 1KHz with a pass band gain of 2. Assume C = 0.01μf. Calculate R [03M03]

a. 15.9MΩ

b. 15.9KΩ

c. 159KΩ

d. 1.59KΩ

26. The voltage gain magnitude equation of second order LPF is [03S01]

a.

b.

c.

d.

27. The high cut off frequeny of secomd order LPF is [03S02]

a.

b.

c.

d.

28. In the second order low pass filter α1

is [03S03]

a. 2.828

b. 1.414

c. 0.707

d. 3

29. In the second order low pass filter, through which component output is fed back to wards input (in filter circuit)

[03S04]

a. Inductor

b. R2

resistor

c. Capacitor

d. Rf resistor

30. In the second order high pass filter, through which component output is feedback towards the input (in filter circuit)

[03S05]

a. Inductor

b. R2

resistor

c. Capacitor

d. Rf resistor

31. Quality of Q ,in the narrow band Band Elimination filter [04D01]

a.

b. Q=1/(2(2-A)

c. Q=1/(3(3-A)

d.

32. Design a notch filter to eliminate 120Hz hum when C=0.33μF R= _ _ _ _ _ _ _ _ _ _ _ _ [04D02]

a. 3kohms

b. 5kohms

c. 6kohms

d. 4kohms

33. Calculate AF value in the narrow band pass filter at fc [04M01]

a.

b.

c.

d.

34. Calculate Q value of the first order band pass filter when f

H= 200

a. 0.559

b. 5.59

c. 55.9

d. 894

35. The new centre frequency can be achieved by changing the resist



[05M03]

[04M03]

a.

b.

c.

d.

36. The relation of quality factor [04S01]

a.

b.

c. Q = BW / fc

d.

37. Design first order wide band pass filter [04S02]

a. HPF O/P connected to I/P of LPF

b. LPF O/P connected to I/P of HPF

c. LPF O/P connected to I/P of LPF

d. HPF O/P connected to I/P of HPF

38. Cut off frequency of BPF & BEF is [04S03]

a.

b.

c.

d.

39. The voltage gain of first order BPF is [04S04]

a.

b.

c.

d.

40. In narrow band pass filter _ _ _ _ _ _ _ _ _ _ _ _ no. of feedback paths are [04S05]

a. 1

b. 2

c. 3

d. 4

41. The total voltage on the capacitor change from _ _ _ _ _ _ _ _ _ _ _ _ _ _ (between chargimg time) [05D01]

a.

b.

c.

d.

42. V

co available in IC form is _ _ _ _ _ _ _ _ _ _ _ NE/SE 566 [05D02]

a. fair child

b. motorola

c. signetic

d. intel

43. Voltage to frequency conversion factor in (566) [05M01]

a.

b.

c.

d.

44. The frequency of VCO (566) , fo = _ _ _ _ _ _ _ _ _ _ _ _ _ [05M02]

a.

b.

c.

d.

45. Calculate fo of the VCO (566) when

a. 26.17 KHz

b. 41.67 KHz

c. 8.33 KHz

d. 4.167 KHz

46. All pass filters are also called as [05S01]



a. Delay equalizers

b. BPF

c. BEF

d. Notch filter

47. For following filter signal input applied for the both inverting and non-inverting Inputs of op-amp [05S02]

a. BPF

b. BEF

c. All pass filter

d. Notch filter

48. The phase angle is given in All pas filter [05S03]

a.

b.

c.

d.

49. NE/SE 566 VCO is _ _ _ _ _ _ _ _ _ pin IC [05S04]

a. 4

b. 8

c. 16

d. 20

50. In , VC

(pin 5) having variable resistor R2

it acts as _ _ _ _ _ _ _ _ _ _ _ _ _application [05S05]

a. fixed frequency generator

b. variable frequency generator

c. variable frequency with control voltage

d. filter

51. The out put of timer is10W, if the amplitude of the trigger pulse: [06D01]

a. =1/3( Vcc )

b. =2/3(Vcc)

c. <2/3(Vcc)

d. >2/3(Vcc).

52. The load connected between pin 3 and +Vcc is called: [06D02]

a. normally off load

b. normally on load

c. abnormal load

d. sub normal load

53. Timing range of 555 timer is [06M01]

a. nano to micro seconds

b. micro to milli seconds

c. micro seconds to hours

d. above one hour.

54. The operating temperature range of 555 timer is:( in degree centigrade`s) [06M02]

a. -55 to 125

b. -10 to +25

c. +25 to +30

d. below25.

55. The out put of timer depends on this property of the external trigger pulse: [06M03]

a. width

b. frequency

c. phase

d. amplitude.

56. In 8 pin 555 Ic,pin 5is _ _ _ _ _ _ _ _ _ [06S01]

a. Threshold

b. Control voltage

c. Vcc

d. Discharge

57. In 8 pin 555 Ic,pin 7is _ _ _ _ _ _ _ _ _ [06S02]

a. Threshold

b. Control voltage

c. Vcc

d. Discharge

58. In 14 pin 555 Ic , pin 5is _ _ _ _ _ _ _ _ _ [06S03]

a. Threshold

b. Control voltage

c. Vcc

d. NC

59. The duty cycle of 555 timer _ _ _ _ _ _ _ _ _ _ _ _ _ _ [06S04]



squarewave [08D01]

a. is adjustable

b. not adjustable

c. adjustable under certain conditions

d. automatically varies with time

60. Ic 555 works with the following voltages(dc) [06S05]

a. +5v to +18v

b. +5v -0-(-5)v

c. 25v

d. -10v

61. In the monostable multivibrator R=100 kilo ohms, T=100msec. calculate the value _ _ _ _ _ _ _ _ _ _ _ _ _ of c. [07D01]

a. 0.9μ farad

b. 0.09 μ farad

c. 1.1 μ farad

d. 2μfarad

62. Capacitor charged on a monostable multi vibrator(Ic555) [07D02]

a. (1/3)Vcc

b. (1/2)Vcc

c. 2/3 Vcc

d. Vcc

63. The output of the timer is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ as long as the trigger input is low [07M01]

a. low

b. high

c. zero

d. unpredictable

64. The time during which the output of a monostable multi vibrator(555) remains high is given by [07M02]

a. RC

b. 1.5RC

c. 1.1RC

d. R/C

65. For the monostable multi vibrator,the pulse width is 10ms.Determine R if c=10μ farad [07M03]

a. 0.1kilo ohms

b. 1kilo ohms

c. 10 ohms

d. 10 kilo ohms

66. Application of negative pulse to the reset terminal [07S01]

a. enables the timer

b. changes the threshold level

c. reset the timer

d. no effect on trigger n threshold level

67. Threshold terminal [07S02]

a. monitors the voltage across c

b. monitors the output voltage

c. monitors the voltage at the discharge terminal

d. has no special role to play

68. The purpose of the transistor q connected to the discharge terminal is to [07S03]

a. maintain trigger level

b. maintain threshold level

c. discharge the external capacitor

d. charge the external capacitor

69. An external voltage applied to the control terminal [07S04]

a. changes the threshold level

b. no effect on the trigger and the threshold level

c. enables the timer

d. reset the timer

70. If the voltage at the trigger input is greater than 2/3 vcc, the output of the timer is [07S05]

a. low

b. high

c. zero

d. unpredectable

71. Astable MV (555 timer ) generates a frequency for unsymmetrical

a. 1.45/( )C

b. 1.45/( )C

c. 1.45/2 C

d. 1.45/2 C

72. Calculate the dutycycle when tlow=0.23ms,T=0.46ms [08D02]

a. 0.5



an Input signal is called _ _ _ _ _ _ _ _ _ _ _ [09M02]

a. 0.5 b. 0.25 c. 1 d. 2

b. 2 c. 1 d. 0.25

73. Calculate dutycycle for unsymmetrical square wave =3.6Kilo ohms =5.5 kilo ohms [08M01]

74. Calculate the frequency of astable MV for symmetrical squarewave f = _ _ _ _ _ _ _ _ _ when =7.25kilo

ohms,c=0.1microfarad [08M02]

a. 2KHZ b. 0.5 KHZ

c. 1KHZ

d. 1.5KHZ

75. Following is astable MV application [08M03]

a. FSK generator

b. Pulse width modulation

c. Missing pulse detector

d. Linear ramp generator

76. To use the monostable MV as a divide by 2 circuit ,the relation between the length of the timing cycle `tp`and the

timeperiod of the trigger input T is [08S01]

a. tp=T

b. tp>T

c. tp should be slightly greater than T

d. T should be slightly greater than tp

77. The time period of the monostable MV using 555 timer can be varied by the voltage applied to the _ _ _ _ _ _ _ _ _ _

terminal [08S02]

a. discharge

b. threshold

c. control

d. ground

78. Following is not the monostable MV application [08S03]

a. missing pulse detector

b. linear ramp generator

c. frequency divider

d. FSK generator

79. The timeperiod of the linear ramp generator is [08S04]

a. T= ( (2/3)Vcc Re (R1+R2)C)/(R1Vcc-Vbe(R1+R2))

b. T= ((2/3) VccReC)/( R1Vcc-Vbe(R1+R2))

c. T = ((2/3) Vcc Re(R1+R2)C)/ (R1 Vcc-Vbe)

d. T = ((1/3) VccRe(R1+R2)C)/(RVcc-Vbe)

80. Estimate dutycycle of astable MV when T= ton+toff [08S05]

a. RB*100/(RA+2RB)

b. RA*100/(RB+2RA)

c. 100/(RA+2RB)

d. RA*RB*100

81. The centre frequency of the PLL is determined by the free-running frequency of the Vco [09D01]

a. f0=1.2/RC

b. f0=1.2/4RC

c. f0=1.2/3RC

d. f0=1.2/2RC

82. Calculate free running frequency in PLL R1=10kohms C1=0.01μfarad [09D02]

a. 5khz

b. 3khz

c. 6khz

d. 10khz

83. IC _ _ _ _ _ _ _ _ _ _ PLL [09M01]

a. 566 b. 565 c. 1496 d. 1596

84. The range of frequencies over which the PLL can acquire lock with

a. lock range

b. capture range

c. pull intime

d. pulldown time



b. 3 fi

qual to 6,using PLL in frequency multiplier [10S01]

85. The total time taken by the PLL to establish lock is called _ _ _ _ _ _ _ [09M03]

a. lock range

b. capture range

c. pull intime

d. pull down time

86. In practical schmitt trigger , capacitor is preferred between pins [09S01]

a. 3 and 5

b. 5 and 1

c. 2 and 1

d. 6 and 8

87. It is basically an astable multivibrator circuit with variable control voltage is [09S02]

a. pulse width modulator

b. missing pulse detector

c. voltage control oscillator

d. linear ramp generator

88. The lock range of a PLL [09S03]

a. increase with increase in input voltage

b. decrease with decrease in supply voltage

c. increase with increase in supply voltage

d. voltage mirror

89. Wide supply voltage range _ _ _ _ _ _ _ of IC 566 [09S04]

a. 10v to 0v

b. 10v to 24 v

c. 0 to 5v

d. 5v to 12v

90. Following block is not present in PLL [09S05]

a. phase detector

b. amplifier

c. low pass filter

d. high pass filter

91. Calculate capture range frequency of the PLL when f2

=3.07khz ,f1= 2.93k hz [10D01]

a. fc= 6khz

b. fc= 72.83hz

c. fc= 1hz

d. fc= 0hz

92. Calculate the change in lock if supply voltages are changed as follows V=12v, -V = -12v ,fo= 3k hz [10D02]

a. +/- 2khz

b. +/- 3khz

c. +/- 1khz

d. +/- 0.5khz

93. To obtain o/p frequency to= _ _ _ _ _ _ a divide by 10 in frequency multiplier using PLL at fi =100Hz. [10G01]

a. 10Hz

b. 1KHz

c. 2KHz

d. 50KHz.

94. The _ _ _ _ _ means shifting the frequency of an oscillator by a small factor [10M01]

a. Frequency synthesizer

b. FM detector

c. Frequency Translation

d. Frequency multiplier

95. No of LPF blocks are present in frequency translation using PLL [10M02]

a. 3

b. 4

c. 2

d. 1

96. The modulated signal with _ _ _ _ _ _ _ phase shift And the un modulated carrier from output of PLL are fed to the

multiplier (in AM Detection) [10M03]

a. 900

b. 180 0

c. 60 0

d. 2700

97. To obtain o/p frequency to= _ _ _ _ _ _ ,a divide by N should be e

a. fi/3



a. Flexibility

5]

c. fi/6

d. 6 fi

98. Voltage control oscillator of LM 565 PLL center frequency [10S02]

a. 500KHz

b. 1000KHz

c. 100KHz

d. 200KHz

99. Vcc supply of LM565 PLL [10S03]

a. +/- 6V

b. +/- 3V

c. +/-2V

d. +/- 10V

100. When PLL is locked in on the we will have f = _ _ _ _ _ _ _ (M network,N factor) [10S04]

a. (M/N)f

b. (N/M)f

c. Nf

d. Mf

101. Weighted Resistor DAC makes use of _ _ _ _ _ _ voltage. [11D01]

a. -ve reference

b. +ve reference

c. 0 reference

d. Double

102. The full-scale range of a DAC is 16V. If the DAC is a 4-bit circuit, calculate the magnitude of the output voltage

represented by LSB [11D02]

a. 1.0V

b. 8.0V

c. 15V

d. 12V

103. In the digital domain a signal is represented as a series of numbers ( low/ high logic levels) [11M01]

a. Flexibility

b. Repeatability

c. Long-term storage

d. Cost

104. A program is much easier to update and customize than a hardware circuit. Thus a digital system offers [11M02]

a. Flexibility

b. Repeatability


d. Cost

105. In sampling theorem, Nyquist frequency is [11M03]

a. FS/3

b. FS/4

c. FS/2

d. FS

106. Both ADC and DAC are known as [11S01]

a. Message converters

b. Data converters

c. Flash converters

d. Memory converters

107. A/D conversion usually makes use of _ _ _ _ _ _ _ conversion [11S02]

a. A/D

b. D/A

c. A/A

d. D/D

108. The processing in which a number of analog signals, one at a time, are connected to common load is called [11S03]

a. Multiplexing

b. De-Multiplexing

c. Analog Multiplexing

d. Analog Detection

109. Noise can be reduced by transmitting as [11S04]

a. Analog signals

b. Digital signals

c. Semi-digital signals

d. Semi-analog signals

110. Digital system has what disadvantage compared to analog [11S0



_ _ _ _ _ _ _ _ _ _ mv/LSB [13D01] rror =+/- _ _ _ _ _ _ _ _ _ mv [13D02]

a. 12.5 b. 1.25 c. 125 d. 1.9

b. Repeatability


d. Cost

111. Let =10V, n=4 and resolution=0.5. Calculate R/ in the R-2R ladder DAC [12D01]

112. An 8-bit DAC has resolution of 20mV/LSB. Find V [12D02]

a. 6.1V

b. 5.1V

c. 4.1V

d. 3.1V

113. The resistance of R-2R ladder DAC with current output is [12M01]

a.

b.

c.

d.

114. In inverted R-2R ladder DAC where is [12M02]

a.

b.

c.

d.

115. In IC 1408 (16 pin) A1, A8 are _ _ _ _ _ _ _ _ _ _ _ pins? [12M03]

a. MSB,LSB

b. LSB,MSB

c. MSB,MSB

d. LSB,LSB

116. The least significant-bit voltage is given by VSB= _ _ _ _ _ _ _ _ _ in DAC [12S01]

a.

b.

c.

d.

117. The output voltage at full count is represented by VFS and is given by _ _ _ _ _ _ _ in DAC [12S02]

a.

b.

c.

d.

118. A 4-bit DAC has a hypothetical voltage of 8V. Calculate VLSB= _ _ _ _ _ _ _ _ per step [12S03]

a. 0.25V

b. 0.5V

c. 2V

d. 1V

119. Select the error not related to DAC [12S04]

a. Linearity error

b. Offset error

c. Gain error

d. Sum error

120. The resolution of R-2R ladder type DAC with voltage output is [12S05]

a.

b.

c.

d.

121. An 8 bit ADC out put all 1`s when =2.55v Find its resolution _ _

a. 10

b. 20

c. 1

d. 100

122. An 8 bit ADC out put all 1`s when =2.55v Find its Quantization e



version time is [14M01] M02]

a. 6

b. 4

c. 5

d. 3

123. Resolution in ADC [13M01]

a.

b.

c.

d.

124. Parallel comparator ADC is _ _ _ _ _ _ _ _ _ _ technique [13M02]

a. slowest

b. medium

c. constant

d. fastest

125. In a 3 bit ADC, the entire range of voltage should be divided In to _ _ _ _ _ _ _ _ _ _ intervals [13M03]

a. 7

b. 6

c. 8

d. 4

126. _ _ _ _ _ _ _ _ _ _ is also defined as the ratio of a change in value of input voltage Vi , needed to change the digital

output by 1 LSB .If the full scale input voltage required cause a digital output of all 1s is V [13S01]

a. resolution

b. quantization error

c. conversion time

d. settling time

127. Quantization error inADC [13S02]

a.

b.

c.

d.

128. Reference current of Ic 1408 [13S03]

a. 2mA

b. 4mA

c. 6mA

d. 10mA

129. One of the following is odd converter [13S04]

a. single slope

b. dual slope

c. R/2R ladder

d. successive approximation

130. The A/D conversion is a _ _ _ _ _ _ process where by an analog signal is converted into equivalent binary [13S05]

a. Resolution

b. Quantizing

c. Conversion time

d. Settling time

131. The reference voltage for a dual slope ADC is 100mV. If t1=50ms, find t

2 if the input voltage is 150mV [14D01]

a. 50ms

b. 60ms

c. 75ms

d. 150ms

132. If the conversion time of 8-bit flash ADC is 10μs, find the maximum frequency of a sinusoidal voltage than can be

digitized [14D02]

a. 62.17 Hz

b. 42.17 Hz

c. 32.17 Hz

d. 52.17 Hz

133. An 8-bit successive approximation ADC is driven by 1MHz. Its con

a. 8 μ sec

b. 7 μ sec

c. 9 μ sec

d. 6 μ sec

134. Conversion time of successive approximation ADC for n-bit is [14

a. TC=n*T



b. TC=T*(N+2)

c. TC=T*(N+1)

d. TC=T

135. Indirect ADC method is [14M03]

a. Counter type ADC

b. Tracking or Servo type ADC

c. Successive approximation ADC

d. Dual slope ADC

136. According to speed, dual slope ADC is _ _ _ _ _ _ _ [14S01]

a. Fastest

b. Fast

c. Medium

d. Slow

137. According to accuracy dual slope ADC is [14S02]

a. Less

b. Medium

c. More

d. Constant

138. According to accuracy flash type ADC is [14S03]

a. Less

b. Medium

c. More

d. Constant

139. Number of comparators preferred in 3 bit ADC is [14S04]

a. 8 b. 7 c. 6 d. 3

140. According to cost flash type ADC is [14S05]

a. Very costly

b. Medium

c. Constant

d. Less

141. 12 bit DAC operates between +5V. The reading when the input is 001001011100 is [15D01]

a. 1.479V

b. -1.479V

c. 3.521V

d. -3.521V

142. 12 bit CMOS DAC is [15D02]

a. AD7520

b. AD7523

c. AD7521

d. AD7533

143. Differential linearity of an ADC measures deviation from [15M01]

a. Ideal line

b. 1/2 LSB reference line

c. MSB

d. LSB

144. The basic step of a 10 bit DAC is 8.2mV and 0000000000 reads 0V then 0101101111 will read [15M02]

a. 2.092V

b. 2.902V

c. 3.092V

d. 3.902V

145. Examples of CMOS DAC are [15M03]

a. AD 561

b. AD 7520

c. AD754

d. DAC0806

146. The fastest ADC is [15S01]

a. CA330D

b. MOD 1020

c. ADC1103

d. ADC141

147. The successive approximation ADC of the following is [15S02]

a. CA3300D

b. MOD 1020



c. ADC 103

d. ADC 100

148. AD 574 is _ _ _ _ _ _ _ _ bit ADC [15S03]

a. 12

b. 10

c. 8

d. 4

149. The DMMS or DUMS basically employ [15S04]

a. Flash ADC

b. Successive approximation ADC

c. Dual slope integrating ADC

d. V/F ADC

150. The cheapest ADC is [15S05]

a. Flash type

b. Successive approximation type

c. Dual type

d. V/F type

151. A multiplier is an active network the output of which is proportional [16D01]

a. Z=k.(x/y)

b. Z=k.x +y

c. Z=k.x -y

d. Z=k.x.y

152. Linearity of multiplier equation [16D02]

a.

b.

c.

d.

153. The temperature stability is normally measured in terms of the temperature drift of the null offset term phi0, phi

0 units _

_ _ _ _ _ _ _ _ _ [16G01]

a. mV/0C

b. 0C/mV

c. ppm/ 0C

d. 0C/ppm

154. The process is which number of analog signals one at a time are counted at a time are counted at a common load is

called [16M01]

a. Multiplexing

b. De-multiplexing

c. Analogue multiplexing

d. Analogue detection

155. Four quadrant device accepts _ _ _ _ _ _ _ _ signal [16M02]

a. One bipolar

b. One polar

c. Two bipolar

d. Two polar

156. In quarter square multiplier, the multiplier uses _ _ _ _ _ _ _ _ _ _ to produce an output voltage given by [16M03]

a. Two square law devices

b. One square law devices

c. Three square law devices

d. Four square law devices

157. Multiplexing means _ _ _ _ _ _ _ _ _ _ [16S01]

a. One to many

b. Many to many

c. Many to one

d. One to many

158. A four quadrant multiplier can accept input voltage of _ _ _ _ _ _ _ [16S02]

a. Positive

b. Negative

c. Both polarities

d. constant

159. A one quadrant multiplier can operate with _ _ _ _ _ _ _ [16S03]

a. Only one polarity

b. Any two polarities

c. Constant

d. Two polarities



ltiplier [18D02]

a. 1 b. 2 c. 3 d. 4

160. _ _ _ _ _ _ _ _ is specified as the deviation of the actual output from that of the ideal [16S04]

a. Accuracy

b. Linearity

c. Offset terms

d. Bandwidth

161. Modulation for any percentage from 0 to 100 is possible in _ _ _ _ _ _ _ _ _ device. [17D01]

a. MC 1596

b. MC 1429

c. MC 1428

d. MC 1496

162. MC 1596 device can also be realized as a frequency _ _ _ _ _ _ _ [17D02]

a. doubler

b. constant

c. mono

d. scalar

163. Balanced modulator IC _ _ _ _ _ _ _ _ _ [17M01]

a. MC 1428

b. MC 1429

c. MC 1496

d. MC 2000

164. IC 1496 worked as also _ _ _ _ _ _ _ _ [17M02]

a. Product detector

b. FM demodulator

c. PLL

d. VCO

165. _ _ _ _ _ _ _ _ _ _ _ _ of the following IC worked as amplitude modulator [17M03]

a. MC 1428

b. MC 1429

c. MC 1496

d. MC 2000

166. The balanced modulator circuit is used to _ _ _ _ _ _ _ _ _ [17S01]

a. change

b. suppress

c. enhance

d. constant

167. A device having _ _ _ _ _ _ _ _ _ resistance can be used in the balanced modulator to generate AM equal. [17S02]

a. linear

b. non-linear

c. small

d. constant

168. MC 1496 in a balanced modulator circuit operating with _ _ _ _ _ _ supplies [17S03]

a. 12 to -8V

b. -12V to -8V

c. 12V to 8v

d. -12V to 8V

169. The suppression of these spurious sidebands is typically _ _ _ _ _ _ at carrier frequency of 500KHz in balanced

modulator [17S04]

a. 25db

b. 45 db

c. 55 db

d. 35 db

170. the MC 1496 in a balanced modulator circuit maximum modulating signal levels, the Recommended i/p signal levels are

_ _ _ _ _ _ _ _ _ rms, for the carrier _ _ _ _ _ _ rms [17S05]

a. 60 mv ,300 mv

b. 300mv , 60mv

c. 300mv, 300mv

d. 60mv, 60 mv

171. The squaring circuit can be used as _ _ _ _ _ _ _ using multiplier [18D01]

a. Frequency division

b. Frequency doublers

c. Frequency scaling

d. Frequency splitting

172. Dividers are at best _ _ _ _ _ _ _ _ _ _ quadrant devices using mu



jection ratio (FRR) [19S02]

173. MC 1595L is used as _ _ _ _ _ _ _ _ _ _ _ [18M01]

a. only multiplier

b. only divider

c. Multiplier and divider

d. sub tractor

174. Analog multiplier AD 534 is used _ _ _ _ _ _ _ _ oscillator [18M02]

a. RC

b. Wein bridge

c. Hay bridge

d. LC

175. Analog multiplier is used as _ _ _ _ _ _ _ _ _ [18M03]

a. Rectifier

b. diode

c. Transistor

d. JFET

176. Analog switch acts as a open switch when RDS is _ _ _ _ _ _ _ _ [18S01]

a. Zero

b. infinity

c. Finite

d. constant

177. Analog switch acts as a short circuit when _ _ _ _ _ _ _ _ [18S02]

a. R

b. R

c. R

d. constant

178. The switch is closed in JFET when V = _ _ _ _ _ _ [18S03]

a. Constant

b. infinity

c. Zero

d. more negative

179. The switch is open in JFET when V = _ _ _ _ _ _ _ [18S04]

a. Constant

b. infinity

c. Zero

d. more negative

180. A device is used as a divider _ _ _ _ _ _ _ [18S05]

a. RC 420

b. RC 42000

c. RC 650

d. RC 4200

181. Calculate the FRR when change Vi=5v and Vo=0.5mv [19D01]

a. 80db

b. 160db

c. 0db

d. 10db

182. The sample and hold circuit it is the deviation from zero of the o/p voltage when the input voltage is zero [19M01]

a. off set voltage

b. offset current

c. gain error

d. slew rate

183. Droop rate= _ _ _ _ _ _ [19M02]

a. iL

/cH

b. CH

/iL

c. CL

/iL

d. CL

/iH

184. Sample and hold circuits _ _ _ _ _ _ _ _ _ the crosstalk in the multiplexer [19S01]

a. increase

b. constant

c. reduces

d. zero

185. Feed through is usually expressed in terms of the feed through re

a.

b.

c.



d.

186. Acquisition time doesn't depend from the following factors? [19S03]

a. RC time constant

b. Maximum output current of op-amp

c. Slew rate of op-amp

d. Gain of op-amp

187. Due to _ _ _ _ _ _ _ _ _ it is difficult to compensate Aperture time by advance hold command [19S04]

a. a acquisition time

b. aperture time

c. aperture uncertainty

d. hold mode settling time(ts)

188. Calculate the change output Vo= _ _ _ _ _ _ _ _ When change Vi=5v and FRR=80db [20D01]

a. 5mv

b. 0.5mv

c. 50mv

d. 0.05mv

189. In general for monolithic S/H circuits aperture time(tap)and aperture Uncertainty(Δtap) are of the order of [20M01]

a. ns ; ps

b. ms ;ns

c. ps; ns

d. ns; ms

190. Because of propagation delays through the driver and switch Vo will keep tracking Vi some time after the inception of

the hold command. This is the _ _ _ _ _ _ [20S01]

a. acquisition time

b. aperture time

c. aperture uncertainty

d. hold mode settling time



JNTU ONLINE EXAMINATIONS [Mid 2 - lica] - Webs

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