Intro to Digital Design - UW Canvas

CSE369, Spring 2018L9: End Topics

Intro to Digital DesignEnd TopicsInstructor: Justin Hsia

EFAIL“Email is a plaintext communication medium. For people… who depend on the confidentiality of digital communication, this may not be enough. OpenPGP offers end-to-end encryption specifically for sensitive communication… S/MIME is an alternative standard for email end-to-end encryption that is typically used to secure corporate email communication.“The EFAIL attacks exploit vulnerabilities in the OpenPGP and S/MIME standards to reveal the plaintext of encrypted emails. In a nutshell, EFAIL abuses active content of HTML emails, for example externally loaded images or styles, to exfiltrate plaintext through requested URLs.”• https://efail.de/


Administrivia

Lab 8 – Project Reports due Friday, June 1 @ 5pm Project check‐ins this week during demos Demos can be scheduled outside of the lab hours by making a private Piazza post

Quiz 3 is next week: Tuesday, May 29 @ 10:30am 35 minutes, worth 14% of your course grade Topics: Timing, Routing Elements, Computational Building Blocks, Verilog Past Quiz 3 (+ solutions) on website: Files Quizzes

• Note: Your Quiz 3 will look a little different – focus on problem solving 2


Transfer of Data

Two modes of communication Parallel: all bits transferred at the same time Serial: one bit transferred at a time

Shift registers can be used for serial transfer:

In general, shift registers can allow for either or both modes (S for serial, P for parallel) at input and output Examples: SISO, SIPO, PISO

3

Computer Printer

In OutShift Reg

CLK

In OutShift Reg

CLK


Shift Register w/Parallel Load

Note: To avoid extra input, use D0 input as “shift in”

4

Load Shift Action

0 0 Q = old Q

0 1 Shift (left)

1 X Parallel load

D QDffCLK

0123

D QDffCLK

0123

D QDffCLK

0123

D QDffCLK

0123


Conversion between Parallel & Serial

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Cycle Shift Load Q0 Q1 Q2 Q3 Shift Load Q0 Q1 Q2 Q30 X X X X X X X X123456

Computer Printer

4‐bitShiftReg

D3D2D1D0

Q3Q2Q1Q0

Shift CLK Load

4‐bitShiftReg

D3D2D1D0

Q3Q2Q1Q0

Shift CLK Load


Shifter in Verilog

6

module leftshifter #(parameter WIDTH=8)(s_out, p_out, shift, load, d_in, clk);

output reg s_out; // serial outoutput reg [WIDTH-1:0] p_out; // parallel outinput [WIDTH-1:0] d_in; // data in (shift in d0)input shift, load, clk;

always @(posedge clk) beginif (load)p_out <= d_in;

else if (shift)p_out <= {p_out[WIDTH-2:0], d_in[0]};

end

assign s_out = p_out[WIDTH-1];

endmodule


Outline

Computer Components (Cont.) Memory/RAM Datapath teaser

FPGAs Course Wrap‐up

7


Storage Element: Idealized Memory

Memory (idealized) One input bus: DataIn One output bus: DataOut In reality, often combined

Memory access: Read: WriteEnable = 0, data at Address placed on DataOut Write: WriteEnable = 1, DataIn written to Address

For addresses, need Address input to be ‐bits wide

Clock (CLK) is a factor ONLY during write operation

8

CLK

DataInNx8 RAM

WriteEnable

8 8DataOut

Address


8x4 RAM

000

001

010

011

100

101

110

111

3-bitDEMUX

In

S2 S1 S0A2A1A0

In3 In2 In1 In0

Out3 Out2 Out1 Out0

WriteEnable


RAM Cell

Requirements: Store one bit of data Change data based on input when row is selected

Just a controlled register! No need to Reset Use RowSelect as Enable

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D Q

En

Input

RowSelect


Verilog Memories

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module memory16x8 (data_out, data_in, addr, write, clk);

output reg [7:0] data_out;input [7:0] data_in;input [3:0] addr;input write, clk;

reg [7:0] mem [15:0]; // two-dimensional array!

assign data_out = mem[addr];

always @(posedge clk)if (write)mem[addr] <= data_in;

endmodule


Datapath Teaser

Instructions of the form: operation src, dst Signals in red are set by Control based on operation This is inaccurate/incomplete but gives you a vague idea of connecting parts

12

64

ALUctr

CLK

busW

RegWr

64

64busA

64

busB

4 4

RW RA RB

srcdst

dst

Extender 64immediate

ALUSrcExtOp

MemtoReg

CLK

Data In

64

MemWrRegFile

0

1

ALU

0

1DataMemory

WrEn Addr

4 condition flags

next_rip InstrFetchUnitCLK


Outline



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RAMRAMRAMRAMRAM

RAMRAMRAMRAMRAM

RAMRAM

Logic cells imbedded in a general routing structure

Logic cells usually contain:

6‐input Boolean function calculator

Flip‐flop (1‐bit memory)

•

•

All features electronically (re)programmable

Field Programmable Gate Arrays (FPGAs)

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Using an FPGA

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// Verilog code for 2-inputmultiplexer

module AOI (F, A, B, C, D);output F;input A, B, C, D;

assign F = ~((A & B) | (C &D));endmodule

module MUX2 (V, SEL, I, J); //2:1 multiplexer

output V;input SEL, I, J;wire SELB, VB;

not G1 (SELB, SEL);AOI G2 (VB, I, SEL, SELB, J);not G3 (V, VB);

endmodule







endmodule







endmodule







endmodule

Verilog

FPGACADTools

0010101000101001010010010010011000101010001010110001010100101001010100010110001001010101010011110010010100001010100101010010010000101010101001010100101000101011010100101001010010100101001

Bitstream

Simulation


FPGA Combinational Logic

16

Create arbitrary combinational binary function F(A,B,C) using MUXes Creates a Lookup Table (LUT)

S2S1S0

0

7

123456

8:1MUX


FPGA Programming

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0010101000101001010010010010011000101010001010110001010100101001010100010110001001010101010011110010010100001010100101010010010000101010101001010100101000101011010100101001010010100101001

Bitstream

P = 1 memory cell (stores 1 bit of info)

PPPP

P P

S2S1S0

0

7

123456

8:1MUX

PPPP

P


FPGA Sequential Logic

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How do we put DFF’s onto LUT outputs only when we need them?

Creates an Logic Cell (or Logic Element)

D flipflopD Q

Clk

3‐inputLUT

A B C


Cyclone V Adaptive Logic Modules

19

https://www.altera.com/content/dam/altera‐www/global/en_US/pdfs/literature/hb/cyclone‐v/cv_5v2.pdf


Generic FPGA Logic Layout

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http://www.chipdesignmag.com/print.php?articleId=434?issueId=16


Example Programmed Gate Array

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0001

𝒇𝟏

0100

𝒇𝟐

0111

𝒇

𝒇

𝒙𝟐

𝒙𝟏

𝒙𝟑

· · ·

· · · Brown & VranesicFigure B.39

Not connected

Connected


FPGA CAD

22

CAD = “Computer‐Aided Design”

1) Tech Mapping: Convert Verilog to LUTs2) Placement: Assign LUTs to specific locations3) Routing: Wire inputs to outputs4) Bitstream Generation: Convert mapping to bits







endmodule







endmodule







endmodule







endmodule

Verilog

FPGACADTools

0010101000101001010010010010011000101010001010110001010100101001010100010110001001010101010011110010010100001010100101010010010000101010101001010100101000101011010100101001010010100101001

Bitstream


Gate Array vs. SoC

SoC = “System on a Chip”

23


DE1‐SoC Board

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DE1‐SoC Board

25


FPGAs vs. CPUs

Individual CPUs designed to handle sequential instruction execution Design and layout determined by architecture Computations “limited” to instruction set Powerful, but also requires things like OS

FPGAs Programmable, so specially‐designed logic for application

• But can be difficult to specify certain applications

Good for parallelizing computations• Can perform separate computations if separated via routing

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Outline



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Course Wrap‐Up

Combinational Logic Karnaugh Maps

Sequential Logic Timing Considerations

Finite State Machines Routing Elements Multiplexor, Encoder, Decoder, Demultiplexor

Computational Building Blocks Adders, Registers, Shift Registers, Counters

Verilog

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Digital Workhorses

Multiplexors Logic – can implement arbitrary logic as LUTs Routing – select between many simultaneous computations

Flip‐flops Store information registers, shift registers, counters, FSMs, RAM cells Synchronization of system

• Delay element – “holds up” information

Deal with metastability

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Takeaways

You can do a lot without actually digging into the hardware details! Verilog is programmatic way to generate design hardware High‐level view is sufficient for system design in many cases

… but the hardware details are important Timing especially – synchronization, metastability Bits are always present – resets, unexpected situations Design affects speed, power, size

A CPU is not required for many applications

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Takeaways

You now know how to design and implement fairly complex digital designs! Could breadboard + wire packages DE1‐SoC ($250): http://www.terasic.com.tw/cgi‐bin/page/archive.pl?Language=English&No=836

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Final Words

Please fill out course evaluation! Will be released next week online Let us know how to improve this class

Future classes EE 205/215 – details of electronics CSE 371 – digital design considerations (communication, robustness, power consumption) CSE 469 – computer architecture (CPU design)

Hope you had fun this quarter!

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Intro to Digital Design - UW Canvas

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