Impact of Organic Substrate Warp on C4 Non-Wets

IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 1, NO. 12, DECEMBER 2011 1947

Impact of Organic Substrate Warp on C4 Non-WetsVijay D. Khanna, Member, IEEE, and Sri M. Sri-Jayantha, Member, IEEE

Abstract— Balancing the level of substrate warp at reflow withother sources contributing to C4 non-wets is an important prob-lem. To address this, a methodology to predict the probability ofnon-wets during the chip attach process of an organic packagehas been developed. A technique for quantifying the convex orconcave warp of a substrate in the form of a shape inversion (SI)plot is introduced. Geometrical factors that influence non-wets,such as C4 height, solder pad relative location, collapsed solderheight etc., are described and their individual contributions to thenon-wet conditions are computed. Combining these contributionsonto the SI plot allows for a graphical representation of the non-wet probability. The technique is applied to a product substrateand the results are compared with the actual yield observedduring chip assembly.

Index Terms— C4, non-wet, reflow, substrate, warp.

I. INTRODUCTION

FLIP CHIP organic assemblies dominate microproces-sor and application-specific integrated circuit packages,

because they provide the high density and low impedanceI/Os demanded by these devices. The chips use an area arrayof C4 (controlled collapse chip connection) joints that aresoldered onto a matching set of solder pads on a substrate.High performance chips can incorporate more than 10 000 C4swith this number constantly increasing. The size and pitch ofthe C4s thus continue to decrease with time.

The substrate requirements have to match the increase indensity and the reduction of C4 pitch. This need, along withthe desire for lower packaging cost, has led to the adoptionof organic substrates in place of ceramics. The evolution of,and advantages and challenges facing organic substrates havebeen well documented [1], [2].

The use of resin, glass fiber and copper in the fabrication oforganic substrates creates several challenges. An obvious oneis the mismatch of thermal expansion between the chip and thesubstrate. A more complicated problem is that of managingthe native warp of the substrate. This warp must not onlysatisfy JEDEC specifications for flatness at room temperaturebut also meet the criterion of high C4 yield. The high volumeelectronics industry imposes stringent requirements on yield.Even a 1% yield loss is considered to be uneconomical.

A systematic method to predict substrate warp is a first steptoward minimizing yield loss [3]. However, arbitrary attempts

Manuscript received October 27, 2010; revised March 1, 2011; acceptedMarch 4, 2011. Date of publication August 4, 2011; date of current versionDecember 21, 2011. Recommended for publication by Associate EditorE. D. Perfecto upon evaluation of reviewers’ comments.

The authors are with the IBM Thomas J. Watson Research Center, YorktownHeights, NY 10598 USA (e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2011.2134103

to reduce warp can be counter productive because the otherfactors contributing to C4 non-wets can become dominant.Balancing the level of warp with these other factors thereforebecomes prudent.

A. C4 Non-Wet Problem

The warp in the flip chip area (FCA) makes it difficult forthe solder on the substrate pads and the C4s on the chip tocome into contact during reflow. This non-wetting condition(C4 non-wets) results in a loss of electrical connectivity andrenders the electronic package defective.

The factors affecting non-wets are many. Warp is obviouslya major contributor but is not the only one. This paperdiscusses the various factors and computes their relative impor-tance. A dimensional analysis determines the range of warpsthat will result in zero non-wets.

II. QUANTIFYING SUBSTRATE WARP

The warp of the substrates and its temperature dependencewas measured using a commercially available digital imagecorrelation (DIC) system [4]. This system employs a pair of2M pixel digital cameras to take stereo pictures of the objectbeing measured and uses image correlation to compute its sizeand shape. The accuracy of the system is reported as a smallfraction of a pixel.

In these measurements the substrates were heated in aconvection oven and the pictures were taken through a glasswindow. The oven was ramped at a rate of 3 °C/min toachieve quasi-equilibrium heating of the substrate and therebyeliminate effects due to temperature differentials. The systemwas routinely able to achieve a 1–2 μm repeatability in themeasurements at room temperature (with a slight decrease inaccuracy at higher temperatures). Ten images were recordedat each temperature so that averaging would eliminate theseDIC measurement errors.

Preliminary measurements on a few samples of the samesubstrate showed that the spread in the data was enough tonecessitate measuring a minimum sample size to reduce thisas a source of error. As a matter of convenience the sample sizewas chosen as 12. The samples were chosen at random fromthe available set of substrates with no consideration for panelor panel position. (Note that multiple substrates are made ina single panel and are then singulated at the final step in amanner similar to how chips are made on a silicon wafer.)

A typical result of the DIC is shown in Fig. 1. This is a con-tour map of the 3-D shape of the substrate at the temperatureof interest (25 °C in this case). Such a map gives much detailedinformation on the shape, but is not conducive to quantifyingand comparing warp behavior between substrates. To help in

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1948 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 1, NO. 12, DECEMBER 2011

Section 0

Stage: 0Temp � 24.3 °C

Section 1

Absolute Warp Contour[μm]

25.6

20.0

15.0

10.0

5.0

0.0

−5.0

−10.0

−16.2

Fig. 1. DIC results-contour plot of the absolute warp of a substrate. Twosection profiles are defined along the diagonals to help quantify the warp.

0 10 20 30 40 50 60Diagonal (mm)

−150

−100

−50

0

50

100

150

Z (μ

m)

0102030405060708

09101112MeanM + 3SDM − 3SD

Absolute Warp @ 25 °CSection 0 Normalized

Chip side

BGA side

Fig. 2. Section 0 profiles at 25 °C for the 12 samples with mean and ±3sigma lines. Note the large spread in the data.

quantifying the warp, it was decided to use section profilesalong the diagonals as is shown in the figure.

The Section 0 profiles for all 12 samples are shown inFig. 2 for 25 °C. Each profile has been normalized (zeroshifted) so that the center of the profile is at zero. This aids invisualizing the spread in the data, which is fairly significant—varying from ∼+75 μm (concave) to ∼−60 μm (convex).Normalizing also aids in quantifying the warp by a singlenumber as will be shown later. The mean (M) and sigma(SD) of the profiles are computed and are superimposed onthe plot. The mean line shows the nominal behavior of thefull population while the M±3SD red lines show the range(+175 to −100 μm) in which 99.6% of the population can beexpected to lie.

Similar calculations are performed for all the temperaturesand results in a family of means and standard deviations(sigmas). The means are plotted in Fig. 3. One can observethat, as the temperature is raised, the substrate bends down-ward (becomes more convex when seen from above) as isshown by the red arrow on the right. This behavior is expected,since the top build-up layers in the substrate are known tohave mostly copper traces with a larger percentage of resinand, thus, a higher coefficients of thermal expansion (CTE)compared to the lower build-up layers that typically have solid

−30 −20 −10 0 10 20 30Diagonal (mm)

−20

−10

0

10

20

30

40

Zon

XY

Z (

μm

)

RT75 C100 C125 C150 C175 C200 C225 C25 CD

Absolute Warp MeanSection 0 Normalized

FCA

CD = cool-down

Fig. 3. Section 0 means for each temperature are plotted and show theincrease in convexity with rising temperature.

−30 −20 −10 0 10 20 30Diagonal (mm)

0

10

20

30

40

50

Std

Dev

(μ

m)

RT75 C100 C125 C150 C175 C200 C225 C25 CD

Absolute Warp Std DevSection 0 Normalized

Fig. 4. Section 0 sigmas for each temperature are plotted and show anindependence from temperature.

w2

Mean = (w1+w

2+w

3+w

4) / 4

Center is kept at zeroFCA

Averaged Profile

w4

w1

w3

Fig. 5. Mean warp is defined as the average of the warps at the four cornersof the FCA.

copper ground or power planes and a lower CTE. The FCA ishighlighted since this is the region of interest when consideringthe impact of the substrate on C4 non-wets.

Similarly the family of standard deviation curves has beenplotted in Fig. 4 and shows that the sigmas (variability)are virtually independent of temperature. This implies thatthe change in warp with temperature (thermal warp) has amuch smaller variability than absolute warp. This can beexplained by the thermal warp being mostly dependent onthe design of the build-up layers while the absolute warpis strongly influenced by manufacturing process variations.Finally, in a manner similar to Figs. 2–4, the set of curves forSection 1 can be computed and plotted. A similar behavior isobserved.

KHANNA AND JAYANTHA: IMPACT OF ORGANIC SUBSTRATE WARP ON C4 NON-WETS 1949

0 50 100 150 200 250

Temperature (°C)

−20

−15

−10

−5

0

5

10

15

Mea

n W

arp

(μm

)

Mean Warp = Average (warp at 4 corners)

-ve = convex

Region of interest

for C4 non-wets

SIT

Mean Warp

FCA

Mean Absolute Warp versus Temp

−ve = convex

SIT

Region of interestfor C4 non-wets

+ve = concave

Slope = thermal warp

Fig. 6. Shape inversion (SI) plot for the warp behavior of the FCA.

At Reflow

Silicon Chip

C4

Substrate

GapGap

SS

Coined solderCoined solder

Melted solderMelted solder

h

Wetting occurs only when Gap < h + S

Fig. 7. Schematic of a C4 situated over its solder pad on the FCA

It soon becomes apparent, however, that such a set of plotsdo not permit an easy comparison of warp behavior from onedesign to another. Hence as a means for easy visualization andcomparison of warp, a definition of the “SI” plot is introduced.This is a plot of the mean warp as a function of temperature.The mean warp is defined as the average of the warp at thefour corners of the FCA. This is illustrated in Fig. 5.

This approximation for warp works best when the FCAshape is symmetric, i.e., convex or concave, and fails toaccurately represent the warp when the shapes are complexsuch as “saddle” (the two corners on one diagonal are up,while the other two corners are down). However, in the FCAit has been observed that the warp is predominantly symmetricso that the mean warp is expected to be an accurate measure.

The “SI” plot is shown in Fig. 6. Here one can see in asingle glance the warp of the substrate at room temperature,the warp at reflow (region of interest for C4 non-wets) andthe temperature at which the warp is zero. Since the centerof the substrate is kept at zero, a positive mean indicates thatthe corners are higher than the center and thus the FCA isconcave. Similarly a negative mean indicates that the FCA is

convex. The slope of the plot is a measure of the change inwarp with temperature, i.e., the thermal warp.

The temperature, at which the substrate goes from concaveto convex, i.e., through an SI, has been labeled as the SItemperature (SIT). One would expect the SIT to be close to thecure temperature of the resin in the substrate but unfortunatelythis is not so. The SIT for different substrate designs has beenobserved to be distributed over a range of temperatures.

III. GEOMETRIC FACTORS EFFECTING C4 NON-WETS

There are primarily two sets of factors that have an effect onthe wetting of C4s during reflow. One set are geometrical innature and control whether the C4s come into contact withthe solder on the substrate pads. The others are chemistrybased and act to hinder the wetting between the C4 and soldereven when they are in contact. This paper focuses on thegeometrical factors and discusses their relative importance forwetting.

First it is essential to define the spatial conditions that willallow wetting to occur. Fig. 7 shows a schematic of a C4located over its mating pad on the substrate. For the solder towet the C4 the ‘Gap’ between the chip and substrate has tobe less than the sum of the C4 height ‘h’ plus the height ‘S’of the solder once it is melted.1 This ‘Gap’ depends on theminimum gap between the chip and substrate as defined bythe points of initial contact. Superimposed on this minimumgap are the variations caused by non-flatness and misalignmentdue to the factors described ahead.

There are primarily five geometrical factors that influencethe wetting of C4s. These can be listed as follows.

1) Substrate warp at reflow—impacts the ‘Gap.’2) CTE radial offset—impacts the ‘Gap.’3) Pancaking of Pb-free C4s—impacts ‘h.’4) C4 height variation—impacts ‘h.’5) Minimum solder height on pads—impacts ‘S.’

1The solder pads on the substrate are coined to provide a flattened surfaceto aid with chip placement prior to reflow. When the solder melts it balls-upand rises to the height ‘S’ above the top of the solder mask surface.


Substrate

Chip

Substrate

Chip

Warp

Substrate

Warp

Chip

Warp

Concave Warp

Convex Warp − case 1

Convex Warp − case 2

Gap = Warp

Gap = Warp

Gap = Warp

Fig. 8. Alignment scenarios for a chip placed on a warped substrate.

The chip is assumed to be perfectly flat and so that variablehas been not included in this list.

A. Substrate Warp

The influence of substrate warp is highlighted in Fig. 8(where only the FCA region is shown). A chip is placed ontop of the substrate with three possible alignment scenarios. Inthe top schematic, a substrate with a concave warp is shownwith the chip resting on the C4s at its corners. (In actuality thechip will rest on the three highest points with a gap at one ofthe corners.) The remaining two schematics show the case ofconvex warp where the chip rests on the highest point near thecenter of the FCA. Case 1 shows where the chip remains leveland gives a clearance that it is equal on all sides. In case 2the chip is shown tilted over to one side.

From these schematics it becomes apparent that the impacton the ‘Gap’ is equal to the substrate warp for the top twoscenarios, but is nearly 2 × warp for case 2 when the chip istilted over.

B. CTE Radial Offset

The solder pads on the substrate are generally designed tomatch the pattern of the C4s at room temperature. However,the chip and substrate have a significant difference in their lat-eral or in-plane CTE. When heated to reflow temperatures, thedifferential expansion between the two creates a misalignmentbetween the C4s and the pads. This is zero at the center ofthe chip and increases with distance from the center. This isillustrated in Fig. 9. The amount of misalignment �x for a�T rise in temperature is given by

�x = DN P × �CT E × �T (1 − C)

where DNP is the distance from neutral point (center of chip),�CTE the difference in CTE (∼15 ppm) and C the degree ofcompensation, 0–1.

Substrate

Chip

C4

Solder

h

S

Gap

Aligned at roomtemperature

Heat

Substrate

�x

Misaligned at reflowtemperature

Thermal Expansion

Fig. 9. Misalignment at reflow, caused by the CTE mismatch between thechip and substrate.

h

S

RcR

c = (r

1+r

2) − �(r

1+r

2)2 − �x2

where �x = DNP ×ΔCTE × ΔT (1−C)

C = degree of compensation, 0 to 1

Chip

Substrate

Solder

r1

r2

�xC4 Rc

Rc

Fig. 10. Computation of Rc , the amount of clearance between the C4 andsolder, caused by the misalignment.

A consequence of this misalignment is that a clearance iscreated between the C4 and solder that impacts the ‘Gap.’

Correcting for this CTE misalignment has been discussedin a number of publications. Since the substrate expands morethan the silicon chip, it has been suggested [5] to make thepad pattern smaller than the C4 pattern at room temperature.This is expected to reduce the �x at reflow conditions. Theamount by which the pad pattern is made smaller is a measureof compensation. The factor C is introduced to accommodatethese different degrees of compensation. For no compensation,C = 0, the two patterns match at room temperature and �x isa maximum at reflow. For full compensation, C = 1, the padpattern is made sufficiently small so that �x = 0 is obtainedat reflow.

The effect of the misalignment can be quantified by com-puting the distance the chip would have to be lowered to bringthe C4 back into contact with the solder. This computation isshown in Fig. 10.

In this figure, the amount the chip has to be lowered tore-establish contact is given by Rc and can be computed as

Rc = (r1 + r2) −√

(r1 + r2)2 − �x2

where r1 and r2 are the radii of the C4 and solder, respectively.The clearance is dependent not only on DNP but also on

the size of the C4s and solder pad. This is shown in Fig. 11where Rc has been plotted as a function of DNP for three(r1 + r2) values. It can be seen that the clearance increases asthe square of the DNP (i.e., the size of the chip). For the newergeneration of large chips, the factor Rc approaches 20 μm andis becoming comparable to the height of the solder ‘S’ anda good portion of the C4 height ‘h.’ In addition, as the size


Chip Size

19×1925×25

�CTE = 15 ppm

Equivalent gap change Rc due to CTE mismatch

DNP (mm)0

0

10

20

30

40

50

60R

1 + R

2

80 μm

100 μm

120 μm

5 10 15 20 25

Equ

ival

ent G

ap: R

c (μ

m)

�T = 200 °C

Fig. 11. Variation of Rc as a function of DNP and the size of the C4 andsolder.

Substrate

Gap1Gap2

Substrate

SubstrateWarp

Concave WarpChip

Gap at center is reduced by Rc

for No CTE compensation.

Substrate

Chip

Warp

Convex Warp - best case

Gap1Gap2

Gap2 = Gap1 + Rc

Gaps at corners are increased byR

c for No CTE compensation.

SubstrateWarp

Convex Warp -worst case Chip

Gap +2 R

c

Gap at open end is increasedby 2 R

c

Fig. 12. Impact of Rc on the gap between the C4s and solder pads situatedat the points of non-contact.

of the C4s becomes smaller (smaller r1 + r2) with increase intheir density, the clearance only becomes worse.

It turns out that Rc does not always have a negative impacton wetting. It depends on the alignment scenarios as defined inFig. 8. This is illustrated in Fig. 12 where the three scenariosare shown with the left half representing the case of nocompensation with C = 0 while the right half shows full com-pensation with C = 1. In the case of concave warp, because

High-Pb C4s withPbSn solder

Pb-free C4 withPb-free solder

C4 pancakes (flattens) by ‘p’

h − ph

Chip

C4

Substrate

Chip

C4

Substrate

Fig. 13. Behavior of the C4s at the points of initial contact during reflow.This determines the minimum gap between the chip and the substrate.

0 500 1000 1500 2000 2500 3000

Number of Chips

0

5

10

15

20

25

30

Cop

lana

rity

(μ

m)

Coplanarity Mean

C4 Coplanarity

Fig. 14. Coplanarity of the C4s of a chip-a measure of the difference inheight between the tallest and shortest of the C4s.

the misalignment occurs at the points of contact, i.e., thechip corners, Rc allows the chip and substrate to come closertogether, thus reducing the effective gap at the center. In thecase of the convex warps, the chip cannot move relative to thesubstrate due to contact at the chip center, and so the effectivegap is increased by Rc at the periphery (and by 2 Rc forcase 2).

C. C4 Pancaking

As mentioned earlier, the minimum gap between the chipand substrate is defined by what happens during reflow at theinitial points of contact. This is illustrated in Fig. 13 whereboth the possibilities of high-Pb and Pb-free C4s are shown.

In the case of high-Pb C4s, the solder on the substrate padsis usually a low melt. During reflow this solder melts but theC4s do not, so they sink through the solder to come to reston the substrate pad. The minimum gap between the chip andsubstrate becomes equal to the height ‘h’ of the C4.

In the case of Pb-free C4s, the pad solder is also Pb-freeand so both undergo melting during reflow. Since the C4s aremolten, the surface tension of all the molten C4s tends to pullthe chip and substrate closer together and thereby flatten theC4s. This is referred to as pancaking. Due to this effect, theminimum gap between the chip and substrate is ‘h− p,’ where‘p’ is the amount of flattening. This parameter has not beenwell quantified, but is estimated to be in the order of 20 μmfor a 100 μm C4 size.


Chip

Warp

Substrate

δ

Concave Warp

Gapmin

= (h + δ) − p

Gapmax

= (Gapmin

+ Warp − Rc) < (h − δ) + S

min

Fig. 15. Chip on a concave FCA showing the five factors combined to givethe worst case scenario for C4 wetting.

D. C4 Height Variation

Since the minimum gap between the chip and substrate isdependent on ‘h,’ any variation in this parameter will alsohave an effect on the gap. Fig. 14 shows a plot of the C4coplanarity data from a large sample (>3000) of a chip madeat IBM Microelectronics. The coplanarity is a measure of thedifference in height between the shortest C4 and the tallest(this assumes no overall tilt in the mean C4 height across thechip). All of these chips have passed production specifications.It can be seen that the coplanarity varies from an average of6.5 μm to a maximum of over 25 μm. In this sample nearly7% have a coplanarity above 10 μm. The coplanarity specifi-cation is 30 μm, thus the worst case variation can be that high.

E. Minimum Solder Height

In the specifications for the manufacturing of the substratesis an entry for the mean height of the solder deposited on theFCA pads and its allowable tolerance. This height is definedas the height of the solder prior to coining. It is the height thatthe solder will achieve once it becomes molten during reflow.It is carefully chosen so that there is enough solder to ensurewetting during reflow, but not enough to allow bridging orshorts between C4s. The height of the solder is typically ofthe order of 30 μm.

IV. COMBINING THE EFFECTS OF THE FIVE FACTORS

Fig. 15 shows a schematic of a chip on a concave warpFCA where all the above factors have been combined to givethe worst case conditions for C4 wetting. In this figure, thefactor ‘δ’ is used as the variation in C4 height, i.e., ‘h ± δ.’The chip coplanarity is thus equal to 2δ.

The worst case scenario occurs when the C4s at the pointsof initial contact (minimum gap) are the tallest, thereby givingthe largest gap at the points of non-contact. Simultaneously theC4s located at this maximum gap have to be the shortest andbe paired with a minimum in solder height. To achieve 100%C4 wetting, this worse case scenario must satisfy the spatialcriterion discussed earlier.

In Fig. 15, the minimum gap is taken as ‘(h + δ) − p’to account for pancaking. The maximum gap is equal to thisminimum gap plus the substrate warp, but is reduced by the

Substrate

Chip

Warp

Substrate

Chip

Warp ~2×W

arp

2δ

2δ

Convex Warp – case 2

Gapmax

= (Gapmin

+ 2Warp + 2Rc) < (h − δ) + S

min

Gapmin

= (h + δ) − p

Gapmin

= (h + δ) − p

Gapmax

= (Gapmin

+ Warp + Rc) < (h − δ) + S

min

Convex Warp – case 1

Fig. 16. Chip on a convex FCA showing the five factors combined in theworst case scenario for C4 wetting.

Rc correction for CTE misalignment (as shown in Fig. 12).Combining Gapmax with the spatial criterion one obtains

Warpconcave < Smin + Rc + p − 2δ.

As long as the concave warp is less than this value 100%C4 to solder wetting can be expected. In a manner similar tothis one can derive the conditions necessary for the convexwarp cases

Warpconvex-1 < Smin − Rc + p − 2δ . . . case 1

Warpconvex-2 <(Smin + p − 2δ)

2− Rc . . . case 2.

The schematics for the convex warps are shown in Fig. 16.Here Gapmax is increased by Rc instead of being reduced.

In deriving these three equations only the absolute sense ofthe warp is considered. The results are therefore only valid forwarp values ≥ zero. If a negative result is obtained that onlyindicates that wetting is not possible for the values chosenfor the 5 factors, even if the substrate is perfectly flat. Thenegative result has no quantitative meaning.

These three relationships define a zone of mean warpswithin which 100% wetting can be achieved. For the chip-substrate system that was studied for this paper, the nominalvalues for the factors are taken as:

1) solder height, Smin ∼27 μm;2) pancaking, p ∼20 μm (not well characterized);3) CTE effect, Rc ∼ 10 μm (19 mm square chip);4) C4 height delta, δ ∼ 10 μm (coplanarity of 20 μm).

When entered into the three equations, the limits are

Warpconcave < 37 μm

Warpconvex-1 < 17 μm

Warpconvex-2 < 4 μm.


0 50 100 150 200 250−20

−15

−10

−5

0

5

10

15Mean Warp

Mean + SD

Mean − SD

Zer

o no

n-w

ets

34.1%

34.1%

13.6%

2.1%

Concave Non-Wets

Convex Non-Wets

Convex-case 1 17

Convex-case 2

4

Concave

37

Non WetProbability

13.6%

37

FCA Mean Absolute Warp versus Temp

Temperature (°C)

Mea

n W

arp

(μm

)

Fig. 17. Enhanced SI plot where the normal distribution curve for warp probability and the zone for 100% wetting has been superimposed. The probabilityof non-wets is given by the part of the distribution curve outside the non-wet zone.

The ideal way to visualize this zone is to superimpose it overthe SI plot. This is shown in Fig. 17. The SI plot is enhancedwith the ± 1SD (sigma) lines which are then used to positionthe normal distribution curve for warp probability at the reflowtemperature. Finally the zone of 100% C4 wetting is plottedadjacent to the normal curve. The concave warp limit is drawnas positive and the convex warp limits as negative to maintainthe sign convention adopted for the SI plot. If the substratewarp lies outside this zone, i.e., above the concave or belowthe convex limits then non-wetting can be expected there.

V. DISCUSSION

From Fig. 17 it is possible to conclude that about 15%of the substrates will have a non-wet problem. This assumesthat the non-wets are primarily due to convex-case 1 scenarios(see Fig. 16). If the chip alignments were more like case 2,then the incidence of non-wets could shoot up to in excessof 60%.

There is one saving possibility—that case 2 may actuallybe self-healing. When the C4s and solder melt together at thepoints of initial contact (on the left in the bottom schematic ofFig. 16), the joining could progress sequentially to the right—just like a zipper being closed. The warp curvature would haveto be below a critical value so that as the nth C4 joined with itspad, the (n + 1)th C4 would come into contact with the solderon its mating pad. This would continue until the zipper effectcompleted fully across the chip (100% wetting) or ended at aregion of local high curvature (the next C4 did not come intocontact with its pad).

The SI plot indicates that the severity of the effect on non-wets increases from concave to convex-case 1 to convex-case 2as indicated by the decreasing limits.

The ideal mean warp is at the middle of this 100% wettingzone

Ideal Mean Warp = (Warpconcave − Warpconvex-case 1)

2= Rc

which is 10 μm concave for this system.A small concave warp has been accepted as being advan-

tageous for C4 wetting for quite some time. It is importantto realize that this is true only for non-CTE compensatedsubstrates, where Rc > 0. For fully compensated substrates(Rc = 0) the limits for concave and convex-case 1 warps arethe same. The ideal mean warp for such a substrate wouldthen be zero.

The ideal mean warp gives the lowest non-wet probabilityfor any given spread in the warp. Furthermore if one couldnarrow the standard deviation, one could possibly obtain zeronon-wets. Unfortunately the control of the mean and sigmaof the warp is beyond present manufacturing capabilities. Aparametric study of a large number of substrates is underwayto discover the influence of design, material and fabricationvariables on the mean and sigma. The aim of the study is tofind ways to control the substrate warp to achieve high yields.The authors plan to publish this paper soon.

Substrate warp has been singled out as the source of theproblem whenever non-wets are observed. This paper showsthat even if one had a perfectly flat substrate it is possible toobtain non-wets due to the other factors involved being at anextreme (but still within specifications). For example considera system which has a substrate with a zero warp, has high-Pb C4s, has 100% CTE compensation, has a minimum solderheight of 25 μm and has a large coplanarity of 30 μm. Thethree limits for the zone would all be < 0 indicating one couldnever achieve 100% wetting.


−8 −6 −4 −2 0 2 4 6 8

−10−5

05

10

−4

−2

0

2

4

6

8

10

12

14

16

zm

zchip

x

y

C4-gap

Plane representinga chip at reflow

Fig. 18. Expanded view of the chip-attach area of the substrate as measured by the DIC. Superimposed is a plane that represents the chip which has high-PbC4s that do not melt.

It is now also possible to make some observations on therelative contribution of each factor.

1) Substrate warp is obviously the largest player in the non-wet problem but it is not the only player. The ability totune the mean and sigma of the warp is the ultimategoal.

2) Large minimum solder height is beneficial for all warps.It should be as large as possible without risking bridgingbetween the C4s. Since bridging occurs where the soldervolume is a maximum, it is desirable to make the largestsolders smaller and smallest solders larger, i.e., thesigma in solder heights should be made low as possible.

3) The use of Pb-free C4s is beneficial because pancakingincreases the limits for all warps.

4) CTE compensation may have the smallest impact of thefactors but should be used wherever possible since it iseasy to incorporate with a minor mask change. It willbecome more important as the chips become larger.

The impact of these factors only gets worse as increases indensity creates a need for larger number of smaller C4s placedcloser together with smaller substrate pads and less solder onthese pads.

A. Comparison of Analysis Prediction with Actual Results

The 15% result of the analysis turned out to be conservativewhen compared to a 10% actual fallout observed in theassembly line. This substrate was in its development stagesand an error in its build-up layers had induced the excessconvex warp at reflow. Typical non-wet losses should havebeen <1%.

The conservative (larger) prediction of the analysis wasalso observed when conducted on other substrate designs. Onepossible reason for this could be that the analysis is based onan insufficient number of factors. It may become necessary to

include the warp of the chip (particularly for the larger chipsof today) and the thermal gradient effects of very high heatingrates during the actual reflow process.

More important is that the analysis presently computes theonset of 100% C4 wetting by only considering the probabilitydistribution of the substrate warp and by considering the worsecase scenario. In actuality the other variables included in theanalysis have a probability distribution of their own whichneed to be considered. Also in a majority of cases the tallestor shortest C4s will not occur at the extreme corners of thechip or at its center. The worst case scenario may be artificiallyconservative.

At a minimum it will be necessary to conduct a multivariateprobability analysis to improve the model and compute a moreaccurate zone for complete C4 wetting.

B. Multivariate Probability Analysis Approach

Probability theory states that if the variables under consid-eration are independent and normally distributed then the sum‘Z ’ of two such variables ‘X’ and ‘Y ’ is normal and given by

λz = λx + λy

andρ2

z = ρ2x + ρ2

y

where λ is the mean and ρ is the standard deviation.Along with the substrate warp there are at least two other

variables that are independent and have a distribution of theirown. They are the height of the C4s ‘h ± δ’ and the heightof the solder on the substrate pads ‘S.’ Both of these havedistributions that are readily available as explained ahead. Forthe purpose of the analysis these variables will need to beassumed as normally distributed.

During the manufacture of the chips the height of each C4 ismeasured using a high speed optical metrology tool that uses


0 2 4 6 8 10 12 14 16 180

200

400

600

800

1000

1200

1400

1600

Gap 6-sigma = 18 μm

Total # of C4s = 8405# >10 μm gap = ~1000 (12%)

Fig. 19. Histogram of the gap between the C4s and the substrate. It has aslight tail toward its high end.

the data to compute the coplanarity of the C4s to compareagainst the specs. These data can easily be manipulated toprovide the mean and sigma of the C4 heights. Similarlyduring the manufacture of the substrates, a similar tool is usedto measure the height of the solder on the pads prior to coining.This is used to determine the minimum height of the solderto compare with the specs. These data can easily provide themean and sigma of the solder heights.

The remaining two variables—‘Rc’ and ‘p’ are dependentvariables that are computed from other factors. In Fig. 10‘Rc’ is shown to be computed from geometric factors. Dueto tolerances in the C4 and pad positions and in the soldervolumes, there will be a variability in �x and (r1+ r2) that willresult in a distribution for ‘Rc.’ Similarly ‘p’ the pancakingfactor depends on the balance of the surface tension forcesbetween the elongated and flattened molten C4s that havejoined with their mating pads. This will be highly dependenton the substrate warp and to some extent on the total volumeof the solder (C4+pad) at each joint. The inclusion of thesedependent variables makes the analysis significantly morecomplex.

Additional complexity arises from the fact that the C4sand solder melt and solidify over a range of temperatures—from the melting point to solidification with undercooling.During this period the substrate undergoes continuous changesin shape due to its thermal sensitivity (slope of SI plot) andwarp relaxation. This in turn causes changes in the amountof pancaking because of its high dependence on the substrateshape. Under this complex scenario it is entirely feasible thatwetting can even occur during the cool down cycle, while theC4s and/or solder are still molten.

The authors are working on developing this complete analy-sis and hope to present it in the future.

VI. FINE TUNING FOR ZERO NON-WETS

If the actual C4 height distribution is known for each chipand the solder height for each substrate then with the additionof the measured warp of each substrate (at reflow tempera-tures), enough information may be available to compute the

actual non-wet occurrence for the specific pairing of a chipwith a substrate.

The ability to pair a specific chip to a substrate could helpfurther reduce non-wet occurrence or even allow one to loosentolerances. That is because an out of tolerance chip whenpaired with an appropriate substrate warp could still give zeronon-wets.

The procedure to achieve this is shown in Fig. 18. TheFCA warp for the substrate, as obtained from the DIC, ismanipulated mathematically to compute the gaps between allof the C4s and their mating pads. The chip is assumed flat andis represented by a plane above the substrate. The boundaryconditions that define the equilibrium position of this planerelative to the substrate depends upon whether the C4s arehigh lead (do not melt) or Pb-free (melt).

In the case of the C4s not melting, the chip will adjust itselfso that it comes in contact with the substrate at three points.An optimization algorithm that minimizes the height of thecenter of gravity of the chip was used to identify its finalresting position. At the contact points the C4s sink throughthe molten solder on the pads and come to rest against thepads themselves. The gaps between the chip and substrate areequal to the height of these three specific C4s.

In the case of the C4s melting, the analysis has to take intoaccount that a certain set of the C4s will wet their mating padsand that the surface tension forces acting at these points willforce the plane to orient in a particular way. This analysis isfairly tedious but achievable.

Once the orientation of the plane has been determined it isfairly straightforward to compute the gaps between the chipand the substrate at the remaining C4s. A histogram of thegaps for the substrate of Fig. 18 is shown in Fig. 19. Thismay be approximated as a normal distribution even thoughthere is a slight tail toward its high end.

Once the gaps have been computed then it is just a matter ofmatching these with the C4 and solder heights at each locationto determine if there will be any non-wets between the specificchip and substrate.

VII. CONCLUSION

A graphical technique to analyze and predict the proba-bility of obtaining C4 non-wets during chip attach has beenpresented. The analysis introduces the geometrical factorsthat impact non-wets and computes the relative contributionof each. The optimal mean warp needed for minimal non-wetting is shown to depend upon whether the substrate is CTEcompensated or not and ranges from zero to slightly concave.The largest contributors to non-wets, besides warp, are shownto be the solder volume and variation in C4 height. The useof Pb-free C4s is shown to be beneficial and CTE-inducedmisalignments to be minor but increasing with chip size.

The analysis is overly conservative and predicts a greaterprobability of C4 non-wets than are actually obtained duringmanufacturing. This indicates a need for refining the techniqueby considering more geometrical factors and for the inclusionof multivariate probabilities. The procedure needed to achievethis is described along with a discussion of matching specificchips with substrates to further reduce C4 non-wets.


ACKNOWLEDGMENT

The authors appreciate for the helpful comments given bytheir colleagues—D. Russell, B. Bernier, and D. Powell, allfrom IBM, Yorktown Heights, NY.

REFERENCES

[1] E. D. Blackshear, M. Cases, E. Klink, S. R. Engle, R. S. Malfatt, D.N. de Araujo, S. Oggioni, L. D. LaCroix, J. A. Wakil, N. H. Pham,G. G. Hougham, and D. J. Russell, “The evolution of build-up packagetechnology and its design challenges,” IBM J. Res. Develop., vol. 49,no. 4.5, pp. 641–661, Jul. 2005.

[2] P. Borgesen, “Flip chip on organic substrates,” in Proc. SMTA, San Jose,CA, 1999, pp. 1–9.

[3] L. Valdevit, V. Khanna, A. Sharma, S. Sri-Jayantha, D. Questad, and K.Sikka, “Organic substrates for flip-chip design: A thermo-mechanicalmodel that accounts for heterogeneity and anisotropy,” Microelectron.Rel., vol. 48, no. 2, pp. 245–260, Feb. 2008.

[4] Aramis 3-D Deformation Analysis System. GOM Optical MeasuringTechniques, Germany [Online]. Available: http://www.gom.com/

[5] T. C. Chai, X. Zhang, H. Y. Li, V. N. Sekhar, W. Y. Hnin, M. L. Thew,O. K. Navas, J. Lau, R. Murthy, S. Balakumar, Y. M. Tan, C. K. Cheng,S. L. Liew, D. Z. Chi, and W. H. Zhu, “Impact of packaging design onreliability of large die Cu/low-κ (BD) interconnect,” in Proc. Electron.Comp. Technol. Conf., 2008, pp. 38–45.

Vijay D. Khanna (M’89) received the Ph.D. degreein mechanical engineering from the University ofTexas, Austin, in 1984.

He joined the IBM Thomas J. Watson ResearchCenter, Yorktown Heights, NY, and for 25 yearshas worked on numerous projects involving thedevelopment, prototyping, and characterization ofcomplex mechanical systems. For the past five years,he has worked in the area of electronic packaging,specifically on the characterization and modeling ofwarp in organic laminates.

Sri M. Sri-Jayantha (M’89) received the Ph.D.degree in mechanical and aerospace engineeringfrom Princeton University, Princeton, NJ, in 1983.

He joined the IBM Thomas J. Watson ResearchCenter, Yorktown Heights, NY, in 1983, as aResearch Staff Member, and currently manages agroup associated with micro-electronic system mod-eling and simulation. He holds more than 75 U.S.patents, and has reviewed and published severalpapers in IEEE transactions.

Dr. Sri-Jayantha received several OutstandingTechnical Achievement and Innovation Awards.

Impact of Organic Substrate Warp on C4 Non-Wets

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