Hope Foundation's International Institute of Information Technology

Hinjawadi, Pune - 411057 Department of Information Technology

Objective Question Bank

Subject: Digital Electronics & Logic Design SE IT

Unit-II – Combinational Logic Design

Q.1 An n variable K map can have (Mark 1) A) N2 cells B) 2n cells C) nn cells D) n2ncells

Q.2 Each term in the standard SOP form is called a (Mark 1) A) Minterm B) Maxterm C) Don’t care condition D) Literal

Q.3 Each term in the standard POS form is called a (Mark 1) A) Minterm B) Maxterm C) Don’t care condition D) Literal

Q.4 The main criteria in the design of digital circuit is reduction of (Mark 1) A) Cost B) Size C) Weight D) Volume

Q.5 The binary number designation of the rows and columns of the K map are in A) Binary code (Mark 1) B) BCD code C) Excess-3 code D) Gray code

Q.6 An 8 square eliminates (Mark 1) A) 2 Variables B) 3 Variables C) 4 Variables D) 8 Variables

Q.7 An 8 Square is called (Mark 1) A) A pair B) A quad C) An octet D) A cube

Q.8 Any variable appearing in the final expression is called a (Mark 1) A) Literal B) A real variable C) Final variable

D) Variable Q.9 The total no of 1s present in a term is called the (Mark 1)

A) Index B) Weight C) Logic level D) Term number

Q.10 Combining of adjacent squares on a k map containing 1s (or 0s)for the purpose of simplification of a SOP (POS)equation is called (Mark 1)

A) Looping B) Squaring C) Charting D) Forming

Q.11 The code used for labeling the cells of a k map is (Mark 1) A) 8-4-2-1 binary B) Hexadecimal C) Gray D) Octal

Q.12 The number of cells in a 6 variable k map is (Mark 1) A) 6 B) 12 C) 36 D) 64

Q.13 In simplification of a Boolean expression of n variables, a group of 2m adjacent 1s leads to a term with (Mark 1)

A) M-1 less than total number of variables B) M+1 less than total number of variables C) N+M literals D) N-M literals

Q.14 The number of adjacent cells each cell in an n variable k map can have is A) n-1 (Mark 1) B) n C) n+1 D) 2n

Q.15 A 16 square eliminates (Mark 1) A) 2 variables B) 3 variables C) 4 variables D) 8 variables

Q.16 In k map simplification ,a group of 4 adjacent 1s leads to a term with A) One literal less than the total number of variables (Mark 1) B) Two literal less than the total number of variables C) Three literal less than the total number of variables D) Four literal less than the total number of variables

Q.17 Minimization of logical expression while designing digital system helps in reducing (Mark 1)

A) Cost B) Space requirement C) Power requirements D) All of above

Q.18 The NANA _NAND realization is equivalent to (Mark 1)

A) AND- NOT realization B) AND –OR realization C) OR-AND realization D) NOT-OR realization

Q.19 The NOR-NOR realization is equivalent to (Mark 1) A) AND- OR realization B) NOT-AND realization C) OR-NOT realization D) OR-AND realization

Q.20 For the design of a combinational logic circuit with 4 outputs using only NAND gates, The no. of K maps required for the simplification process is (Mark 1)

A) 0 B) 1 C) 2 D) 4

Q.21 The gates required to build a half adder are (Mark 1) A) EX-OR gate and NOR gate B) EX-OR gate and OR gate C) EX-OR gate and AND gate D) Four NAND gates.

Q.22 For three variable combinational circuit ∑m= (1,4,7)= ______. (Mark 1) A) ∑M (0,2,3,5,6) B) π M(0,2,3,5,6) C) ∑m(0,2,3,5,6) D) πm (0,2,3,5,6)

Q.23 IC 74LS153 is a ______. (Mark 1) A) 4:1 mux B) 8:1 mux C) 16:1 mux D) Dual 4:1 mux

Q.24 ____ is a 4 bit comparator IC (Mark 1) A) 7400 B) 7413 C) 7485 D) 7483

Q.25 A DEMUX has _____. (Mark 1) A) One data input and a number of selection inputs, and they have

several outputs. B) One input and one output. C) Several inputs and several outputs. D) Several inputs and one output.

Q.26 ……… Are used for converting one type of number system in to the other form A) Decoder (Mark 1) B) logic gate C) half adder D) Full adder

Q.27 A 4:1 Demux has _________ input and __________ outputs. (Mark 1) A) 1,4 B) 4,1 C) 2,4

D) 4,2 Q.28 The device shown here is most likely a ________. (Mark 2)

A) comparator B) Multiplexer C) Demultiplexer D) Parity generator

Q.29 How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? A) 1 (Mark 1) B) 2 C) 4 D) 8

Q.30 For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be LOW. (Mark 2)

What is the status of the Y output?

A) LOW B) HIGH C) Don’t care D) Cannot be determined

Q.31 How many data select lines are required for selecting eight inputs? A) 1 (Mark 1) B) 2 C) 3 D) 4

Q.32 How many 1-of-16 decoders are required for decoding a 7-bit binary number?

A) 5 (Mark 1) B) 6 C) 7 D) 8

Q.33 How many 3-line-to-8-line decoders are required for a 1-of-32 decoder

A) 1 (Mark 1) B) 2 C) 4 D) 8

Q.34 For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the input is HIGH. What is the status of the outputs? (Mark 2)

A) All are HIGH. B) All are LOW. C) All but Y0'are LOW. D) All but Y0'are HIGH.

Q.35 The device shown here is most likely a ________. (Mark 1)

A) Comparator B) Multiplexer C) Demultiplexer D) Parity generator

Q.36 How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line encoder, have? (Mark 1)

A) 3 B) 4 C) 5 D) 6

Q.37 For a 1:32 Demultiplexer number of select lines is (Mark 1) A) 2 B) 4 C) 5 D) 32

Q.38 Demux is also used for (Mark 1)

A) Data selector B) Data distributer C) Both of above D) None of above

Q.39 IC74138 is used as (Mark 1) A) 1:8 demux B) 3 to 8 line decoder C) Both of the above D) None of the above

Q.40 Outputs of the IC 74138 is (Mark 1) A) Inverted B) Non inverted C) Tristate D) None

Q.41 Which of the following DEMUX is most suitable for implementing full adder? A) 1:8 (Mark 1) B) 1:32 C) 1:64 D) 1:2

Q.42 DEMUX is___________________ circuit (Mark 1) A) Combinational B) Sequential C) Memory Element D) All of that above

Q.43 How many 2 inputs NAND gates and 2 inputs OR gates are required for efficient implementation of full subtractor (Mark 1)

A) 4 NAND, 2 OR B) 3 NAND, 2 OR C) 2 NAND, 3 OR D) 3 NAND, 3 OR

Q.44 f(a,b,c,d)=sum m(1,3,6,9,12,14)this function can be implemented using following demux? (Mark 1)

A) 1:8 B) 1:16 C) 1:32 D) 1:64

Q.45 One application of a digital multiplexer is to facilitate: (Mark 1) A) Data generation B) Serial-to-parallel conversion C) Parity checking D) Data selector

Q.46 Most Demultiplexer facilitates which type of conversion? (Mark 1) A) Decimal-to-hexadecimal B) Single input, multiple outputs C) Ac to dc D) Odd parity to even parity

Q.47 How many inputs will a decimal-to-BCD encoder have? (Mark 1)

A) 4 B) 8 C) 10 D) 16

Q.48 What is the function of an enable input on a multiplexer chip? (Mark 1) A) To apply Vcc B) To connect ground C) To active the entire chip D) To active one half of the chip

Q.49 Which digital system translates coded characters into a more useful form? A) Encoder (Mark 1) B) Display C) Counter D) Decoder

Q.50 Which statement below best describes the function of a decoder? (Mark 1) A) Decoder will convert a decimal number into the proper binary equivalent. B) A decoder will convert a binary number into a specific output

representing a particular character or digit. C) Decoders are used to prevent improper operation of digital systems. D) Decoders are special ICs that are used to make it possible for one brand of

computer to talk to another. Q.51 Parallel adders are (Mark 1)

A) Combinational logic circuit B) Sequential logic circuit C) Both of the above D) None of these

Q.52 In which of the following adder circuits is the carry ripple delay eliminated? (Mark 1)

A) Half adder B) Full adder C) Parallel adder D) Carry look ahead adder

Q.53 To secure a higher speed of addition, which of the following is the preferred solution? (Mark 1)

A) Serial adder B) Parallel adder C) Adder with a look ahead carry D) Full adder

Q.54 A parallel adder in which the carry out of each full adder is the carry in to the next significant digit adder is called (Mark 1)

A) Ripple carry adder B) Look ahead carry adder C) Serial carry adder D) Parallel carry adder

Q.55 The adder preferred for applications where circuit minimization is more important than speed is (Mark 1)

A) Parallel adder B) Serial adder C) Full adder D) Half adder

Q.56 Which of following is not a combinational circuit (Mark 1) A) 4-to-1 multiplexer B) 3 : 8 decoder C) D flip flop D) Comparator

Q.57 Which of following is a combinational circuit (Mark 1) A) Shift register B) Decoder C) Counter D) Ring counter

Q.58 In BCD addition ,0110 is required to be added to the sum for getting the correct result, if (Mark 1)

A) The sum of 2 BCD numbers is not a valid BCD number B) The sum of 2 BCD numbers is not a valid BCD number or a carry is

produced C) A carry is produced D) None of the above is true

Q.59 BCD subtraction is performed by using (Mark 1) A) 1’s complement representation B) 2’s complement representation C) 5’s complement representation D) 9’s complement representation

Q.60 One of the following generations of IC contained hundreds of transistors on each chip. (Mark 1)

A) MSI B) SSI C) LSI D) VLSI

Q.61 One of the following generations of IC contained tens of thousands of transistors. (Mark 1)

A) MSI B) SSI C) LSI D) VLSI

Q.62 Relation between no of output(n) and select lines (m) in DEMUX is A) n=2^m (Mark 1) B) m=2^n C) n=2^(m-1) D) n=(2^m)-1

Q.63 The 8-input XOR circuit shown has an output of Y = 1. Which input combination

below (ordered A – H) is correct? (Mark 2)

A) 10111100 B) 10111000 C) 11100111 D) 00011101

Q.64 The Boolean SOP expression obtained from the truth table below is ________.

(Mark 2)

A)

B)

C) D) None of these

Q.65 The expression Y= AB+BC+AC is in ______ form. (Mark 1)

A) SOP B) POS C) Standard SOP D) Standard POS.

Q.66 Solve the network in the figure given below for X. (Mark 2)

A) A + BC + D B) ((A + B) C) + D C) D (A + B + C) D) (AC + BC) D

Q.67 What type of logic circuit is represented by the figure shown below?

(Mark 1)

A) XOR B) XNOR C) NAND D) NOR

Q.68 Mapping the SOP expression , we get ________. (Mark 2)

A) (A) B) (B) C) (C) D) (D)

Q.69 What is the correct output of the adder in the given figure, with the outputs in the order: (Mark 2)

A) 10111 B) 11101 C) 01101 D) 10011

Q.70 One way to make a four-bit adder perform subtraction is by: (Mark 1) A) Inverting the output. B) Inverting the carry-in and B inputs. C) Inverting the B inputs. D) Grounding the B inputs and carry-in.

Q.71 The simplified form of a logic function is (Mark 1)

A)

B)

C)

D)

Q.72 The reduced form of the Boolean expression of is

A) (Mark 1)

B)

C)

D)

Q.73 =Z then is equal to (Mark 1)

A)

B) C) 0 D) 1

Q.74 If then is equal to (Mark 1)

A)

B)

C)

D)

Q.75 Logical expression in the SOP form is most suitable for designing logic circuit using only (Mark 1)

A) NOR Gates B) NAND gates C) AND gates D) EX_NOR gates

Q.76 Logical expression in the POS form is most suitable for designing logic circuit

using only (Mark 1) A) NOR Gates B) NAND gates C) AND gates D) EX_NOR gates

Q.77 The addition of 3 bits is performed by using a _______ adder (Mark 1)

A) Half B) Full C) Flip-Flop D) Register

Q.78 In half adder the addition is limited to ______ bits (Mark 1)

A) 2 B) 3 C) 4 D) 5

Q.79 The addition of two bits is performed by using a ___ adder (Mark 1) A) Half B) Full C) Parallel D) Serial

Q.80 The result of binary addition 1 + 1 + 1is __________ (Mark 1) A) Carry 0, sum 0 B) carry 0, sum 1 C) carry 1, sum 0 D) carry 1, sum 1

Q.81 The result of binary addition 1 + 1 is __________ (Mark 1)

A) Carry 0, sum 0 B) carry 0, sum 1 C) carry 1, sum 0 D) carry 1, sum 1

Q.82 In four variable K-map, a group of eight adjacent ones leads to a term with

________ (Mark 1) A) 1 variable B) 2 variable C) 3 variable D) 0 variable

Q.83 Which of the following circuits comes under the class of combinational logic circuits? (Mark 1)

1. Full-adder 2. Full-subtractor 3. Half-adder 4. J-K flip-flop 5. Counter Select the correct answer from the codes given below:

A) 1 only B) 3 and 4 C) 4 and 5 D) 1, 2 and 3

Q.84 Consider the following digital circuits : (Mark 1) 1. Multiplexers

2. Read Only Memories

3. D - latch

4. Circuit as shown

Which of these come under the class of combinational of circuits ?

A) 1 and 2 B) 3 and 4 C) 1, 2 and 3 D) 1,2,3 and 4

Q.85 The _________ is a decimal to BCD encoder. (Mark 1)

A) IC 74153 B) IC 74138 C) IC 74147 D) IC 7483

Q.86 The _____ is a dual 4 : 1 multiplexer (Mark 1) A) IC 74153 B) IC 74138 C) IC 74147 D) IC 7483

Q.87 The IC 7483 is a _____ (Mark 1) A) BCD adder B) Comparator C) Multiplexer D) Demultiplexer

Q.88 A digital multiplexer can be used for which of the following? (Mark 1)

1. Decoder 2. Many-to-one switch 3. Implementation of combinational 4. For code conversion Select the correct answer using the code given below :

A) 1,3 and 4 B) 2,3, and 4 C) 1 and 2 only D) 2 and 3 only

Q.89 When two 16-input multiplexes drive a 2-input MUX, what is the result?

A) 2-input MUX (Mark 1) B) 4-input MUX C) 16-input MUX D) 32-input MUX

Q.90 Which of the following statements are correct related to multiplexer? (Mark 1)

1. Selects one of the several inputs and transmits it to a single output 2. Routes the data from a single input to one of many output 3. Can be used to convert parallel data into serial data.

4. Is a combinational circuit

A) 2,3 and 4 B) 1,3 and 4 C) 1,2 and 3 D) 2,4 and 3

Q.91 Two 16:1 and one 2:1 multiplexes can be connected to form a _________ A) 16:1 multiplexes (Mark 1) B) 32:1 multiplexes C) 64:1 multiplexes D) 8:1 multiplexes

Q.92 The difference bit output of a half-subtractor is the same as: (Mark 1)

A) Difference bit output of a half-adder B) Sum bit output half of a half adder C) Sum bit output of a full adder D) Carry bit output of a half adder

Q.93 A sum bit output of full adder is same as ________ (Mark 1) A) Sum bit output of half adder B) Difference bit output of half subtractor C) Carry bit output of half adder D) Difference bit output of full subtractor

Q.94 Which of the following statement is correct related to the full-adder

(Mark 1) A) Two inputs are used to add two binary digits. It produces their sum and

carry as input B) Three inputs are used to add two binary digits plus a carry. It produces

their sum and carry as outputs C) Used in the least significant position when adding two binary digits with no

carry-on to consider. It produces their sum and carry as outputs. D) Two input and two outputs

Q.95 Which of the following simplification method is most suitable when input variables exceeds five variables (Mark 1)

A) K-map B) Boolean algebra C) Quine McCluskey D) All of these

Q.96 If a three variable switching function us expressed as the product of maxterms

by f(A,B,C) = (0,3,5,6), then it can also be expressed as the sum of minterms by A) (1,2,4,7) (Mark 1) B) (1,2,3,7) C) (0,3,5,6) D) (1,2,4,7)

Q.97 The Boolean expression (Mark 2)

Y = m(0,3,6,7,10,12) is equivalent to _________

A) Y = M(0,3,6,7,10,12,15) B) Y = M(1,2,4,5,8,9,11,13,14,15) C) Y = m(1,2,4,5,8,9,11,13,14,15) D) Y = m(0,3,10,12)

Q.98 The Boolean expression (Mark 1) Y = M(1,4,6,9,10,11,14,15) is equivalent to _________

A) Y = M(0,3,6,7,10,12,13) B) Y = M(1,2,4,5,8,9,11,13,14,13) C) Y = m(1,2,4,5,8,9,11,13,14,15) D) Y = m(0,2,3,5,7,8,12,13)

Q.99 An encoder converts _______ (Mark 1)

A) Noncoded information into coded form B) Coded information into noncoded form C) HIGHs to LOWs D) LOWs to HIGHs

Q.100 A multiplexer is also known as _______ (Mark 1)

A) Data selecter B) Data recorder C) Data encoder D) Data decoder