ELEC3720 Chapter 7 Computer Arithmetic

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ELEC3720-2009-B6-PSB ACADEMY-LKH-Chapter 07 1

ELEC3720 Programmable Logic DesignELEC3720 Programmable Logic DesignChapter 07 Computer ArithmeticChapter 07 Computer Arithmetic


A Simple Computer Model

• ALU = Arithmetic Logic Unit, it is an important block of a processor

• To carry out the arithmetic or logic operations, data are fetched from thememory


Outline

• Numbers and Number Systems

• Basic Arithmetic

• Floating-Point Numbers and Arithmetic

• A Basic Arithmetic-Logic Unit


Numbers

• Bit patterns have no inherent meaning– Conventions define relationship between bits and

numbers or code• Positive binary integers

• Binary numbers (base 2) are efficient for computers to use1000 1100 1010 1110 0110 0100 0010 0000 two

• More compactly represented in hexadecimal notation 8CAE6420 hex or 0x8CAE6420

Example:


Negative Numbers

• Signed-Magnitude

• Two representations of zero!– Testing for equality typically done by checking a-b=0

SignBit

Positive Binary Number

0 => Positive 1 => Negative

Example:


Radix ComplementRadix representation:

Complement of X is:

Digit complements:

So that:

And:

Example:Consider two numbers, X = 873 and Y = 218. Radix complement can be used to compute X - Y using solely addition.For decimal number, 10’s complement is used. The 9’s (digit) complement of Y,

Y = 999 - 218 = 781.The 10’s complement of Y,

R - Y = 781 + 1 = 782Therefore,

X - Y = 873 + 782 = 1665

To drop


Diminished-Radix ComplementDefine the complement as

Simplifies complement operation, but has two representations of zero!

In decimal numbering system,Radix complement = 10’s complement

Diminished radix complement = 9’s complement

In binary numbering system,Radix complement = 2’s complement

Diminished radix complement = 1’s complement


Diminished-Radix Complement• Signed numbers are best represented using two’s

complement– largest positive number: 0111two = 7ten

– smallest negative number: 1000two = 8ten

– note: 1111two = 1ten

• Two’s complement numbers can be negated by inverting all of their bits and adding 1 (two’s complement operation)


Diminished-Radix Complement

Graphical Interpretation of 4-bit 2’s Complement Numbers


Excess

• Excess-B (is a biased representation)– M-bit string, 0 ≤ M ≤ 2M, represents M - B

Example2m-1 = 22 = 4 represents Excess-4

Each digit is represented by 3 bits as BCD value plus 4 (the "excess” amount), e.g. -4 + 4 = 0 = 0002


Signed Digit

• Allow individual digits to have signs

• Redundant number system, example

• Useful for high-speed multiplication/division

In signed digit, 1st digit is the sign: 0 = positive, 1 = negative

For negative, radix complement is used.


Addition and Subtraction Operations• Addition is done bit by bit from right to left, with carries

passed to the next bit on the left011 carry0011

+00110110 sum

• Subtraction can be easily done using addition of the negated number

0111 0111 0111-0110 = +(-0110) = +(1010)

2’s complement of 110


Addition - Ripple Carry

Addition circuit:

Overflow: addends’ signs the same but sum’s sign differentOR carries in and out of sign bit are different (c3 ≠c4)


Addition - Overflow • Overflow (result cannot be represented by the finite word

length):– e.g., adding two n-bit numbers yields a (n+1)-bit

number

0111 note that the overflow term in MIPS refers + 0001 to overflow in signed arithmetic and does

1000 not simply mean a carry “overflow” for unsigned arithmetic

(+7) + (+1) = +8, but a 4-bit representation of signed numbers is not able to represent +8 (1000 is -8 in 2’s complement). Overflow is detected: sum of 2 +ve numbersis a negative number. The carry in of the MSB is 1, the carry out is 0 (carry in ≠ carry out)


Addition - Detecting Overflow • No overflow when adding a positive and a negative

number• No overflow when signs are the same for subtraction• Overflow occurs when the value affects the sign of the

result:– overflow when adding two positives yields a negative – or, adding two negatives gives a positive– or, subtract a negative from a positive and get a

negative– or, subtract a positive from a negative and get a

positive• Consider the operations A + B, and A – B

– Can overflow occur if B is 0?– Can overflow occur if A is 0?


Addition - Detecting Overflow • Overflow conditions for addition and subtraction:

• A simpler check for overflow is to see if the CarryIn to the most significant (sign) bit is not the same as the CarryOutof the most significant bit

• A detection of overflow will cause an exception (interrupt)


Subtraction• Radix complement subtraction easy!

Complement is:

We see that:

Subtraction:

If:If:


Carry-Look-Ahead

• How are carries generated/propagated?– Generated:– Propagated:

Define:

From:

We see that:

In binary, A + B generates iff both A and B are 1.

A + B is said to propagate if A + B will carry whenever there is a carry in. This implies A or B is 1.


Multiplication

Multiplication as we know it:

Negatedmultiplicand


Division• Division is generally difficult and covered in ELEC4700• BUT: Can develop an algorithm similar to how we normally

do long division (“Restoring Division”)


Restoring Division• Restoring division operates on fixed-point fractional numbers and depends

on the following assumptions:N < D and 0 < N,D < 1

• The quotient digits q are formed from the digit set {0,1}• The basic algorithm for binary (radix 2) restoring division is:

P := ND := D << n - P and D need twice the word width of N and Qfor i = n-1..0 do - for example 31..0 for 32 bits

P := 2P - D - trial subtraction from shifted valueif P >= 0 then

q(i) := 1 - result-bit 1else

q(i) := 0 - result-bit 0P := P + D - new partial remainder is (restored) shifted value

endend

where N=Numerator, D=Denominator, n=#bits, P=Partial remainder, q(i)=bit #i of quotient


Floating-Point Numbers• Floating-point number F consists of a mantissa (M) and an

exponent (E):

• IEEE-754 Standard

– Single-Precision (32-bit)» 8-bit exponent (Excess), 23-bit mantissa (positive

fraction)– Double-Precision (64-bit)

» 11-bit exponent (Excess), 52-bit mantissa (positive fraction)


Floating-Point Multiplication/Division• Floating-point multiplication/division are easier than

addition/subtraction– Add/subtract the exponents– Multiply/divide the mantissas


Floating-Point Addition/Subtraction

• For addition/subtraction, exponents must be equal!

• Alignment achieved by shifting smaller number |E1 - E2| positions to the right

• Postnormalisation step may be required to correct for over/underflow


Constructing an ALU

• A 1-bit ALU for addition - Full Adder (FA):

• How could we build a 1-bit ALU for ADD, AND, and OR?• How could we build a 32-bit ALU?

cout = a.b + a.cin + b.cinSum = a.b’.cin’ + a’.b. cin’+ a’.b’.cin + a.b.cin

= a xor b xor cin

a b CarryIn CarryOut Sum0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1


Building a 1-Bit ALU

A 1-bit ALU that performs AND, OR, and additions

How do we build a 1-bit ALU for AND and OR?Operation = selector of MUX

multiplexer


Building a 32-Bit ALU

A 32-bit ALU constructed from 32 1-bit ALUs

How do we build a 32-Bit ALU?


What about Subtraction (a – b) ?• Two's complement approach: just negate b and add.• Negating b is obtained simply by inverting b and adding 1

to the least significant bit (LSB) i.e. setting CarryIn = 1 for LSB


Adding a NOR function• Can also choose to invert a• How to get “a NOR b” ?

A 1-bit ALU with AND, OR, ADD, NOT A and NOT B


• set-on-less-than (slt a, b)

– slt is an arithmetic instruction

– produces a 1 if a < b and 0 otherwise

– use subtraction: (a-b) < 0 (negative) implies a < b

– only need to check the ‘sign’ bit

• Test for equality (not an instruction, but needed in branch or jump on condition instructions)

– use subtraction: (a-b) = 0 implies a = b

Some Common Instructions

Correct if no overflowMSB of ALU

Sign

Supporting slt

ELEC3720-2009-T1-PSB ACADEMY-LKH-Chapter 08 31

for slt

Correct if no overflow

Supporting slt

ELEC3720-2009-T1-PSB ACADEMY-LKH-Chapter 08

• Try to figure out the idea?• Subtract b from a, if the difference

is negative then a < b,a – b < 0 (a – b + b) < (0 + b)

a < b• For slt, connect 0 to Less input of

ALU1 to ALU31• The Less input of ALU0 (LSB) is

connected to the Set output of ALU31 (Sign), the result is either

0000….0000 (a > b)or 0000….0001 (a < b)

• ALU31 also sets the Overflow bit accordingly


Test for Equality• It is also necessary to support conditional branch

instructions• The instruction will branch according to the content of two

register, based on subtract operation,a – b = 0 a = b

• For 32-bit operation, testing for result = 0 is to use the NOR function

Zero = 1 when all outputs are 0 (which means a = b)• The 4 input bits (1-bit Ainvert, 1-bit Binvert, 2-bit Operation)

are taken 4-bit control lines for the ALU

Zero Result31 Result30 ... Result1 Result0


Test for Equality• Configuring the control lines: (Ainvert, Bnegate, Operation)

0000 = AND0001 = OR0010 = add0110 = subtract0111 = slt1100 = NOR

Note: zero is a 1 when the result is zero!

21


Summary

• Numbers and Number Systems

• Basic Arithmetic (much more in ELEC4700!)

• Floating-Point Numbers (ditto!)

• Basic ALU

ELEC3720 Chapter 7 Computer Arithmetic

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