Solid-State Electronics 48 (2004) 937–945

www.elsevier.com/locate/sse

Double gate silicon on insulator transistors.A Monte Carlo study

F. G�amiz *, J.B. Rold�an, A. Godoy, J.E. Carceller, P. Cartujo

Departamento de Electr�onica y Tecnolog�ıa de Computadores, Universidad de Granada, Campus Universitario,

Avd. Fuentenueva s/n, 18071 Granada, Spain

The review of this paper was arranged by Prof. S. Cristoloveanu

Abstract

Electron transport properties in double-gate-silicon-on-insulator (DGSOI) transistors are comprehensively studied.

Quantum effects are analyzed by self-consistently solving the 1 D Poisson and Schroedinger equations. Once the

electron distribution is known, the Bolztmann transport equation is solved by the Monte Carlo method, and the role of

volume inversion is analyzed both at room and at lower temperatures. A comparison between symmetrical-gate and

asymmetrical-gate configurations is also provided, showing the superior performance of symmetric devices. Finally,

velocity overshoot is also studied. Monte Carlo simulations were performed to clarify the dependence of velocity

overshoot effects on the low-field mobility, channel inversion charge and silicon layer thickness. We show that electron

mobility is mainly determined by the increase in the phonon scattering rate as the silicon thickness is reduced, i.e., the

lower the silicon thickness the lower the electron mobility, while velocity overshoot effects for ultrathin DGSOI

inversion layers are dominated by the reduction of the average conduction effective mass, i.e., the lower the silicon

thickness the higher the velocity overshoot peak.

� 2004 Elsevier Ltd. All rights reserved.

PACS: 73.40.Qv; 72.20.Fr; 71.70.Fk; 72.10.Fk

1. Introduction

A double-gate-silicon-on-insulator (DGSOI) struc-

ture consists, basically, of a silicon slab sandwiched

between two oxide layers. A metal or polysilicon film is

deposited on each oxide [1]. Each of these films then acts

as a gate electrode (front and back gate), which is

capable of generating an inversion region near the two

Si–SiO2 interfaces, if the appropriate bias is applied.

Thus, two metal-oxide-semiconductor-field-effect-tran-

sistors (MOSFETs) would be sharing the substrate, the

source and the drain. However, the main feature of these

structures arises from the concept of volume inversion,

* Corresponding author. Tel.: +34-958-246145; fax: +34-958-

243230.

E-mail address: fgamiz@ugr.es (F. G�amiz).

0038-1101/$ - see front matter � 2004 Elsevier Ltd. All rights reserv

doi:10.1016/j.sse.2003.12.017

introduced and demonstrated some time ago by Balestra

et al. [2,3] by simultaneously biasing the two gates of a

fully depleted (FD) SOI transistor: if the Si film is

thicker than the sum of the depletion regions induced by

the two gates, no interaction is produced between the

two inversion layers, and the operation of this device is

similar to that of two conventional MOSFETs con-

nected in parallel. However, if the Si thickness is suffi-

ciently reduced, the whole silicon film is depleted and an

important degree of interaction takes place between the

two potential wells. In such conditions the inversion

layer is formed not only at the top and bottom of the

silicon slab (i.e., near the two silicon–oxide interfaces),

but throughout the entire silicon film thickness. The

device is then said to operate in volume inversion, i.e.,

the carriers are no longer confined to one interface, but

are distributed throughout the entire silicon volume.

Several authors have claimed that volume inversion

ed.

938 F. G�amiz et al. / Solid-State Electronics 48 (2004) 937–945

presents a significant number of advantages, such as: (i)

an enhancement of the number of minority carriers; (ii)

an increase in carrier mobility and velocity due to re-

duced influence of the scattering associated with oxide

and interface charges and surface roughness; (iii) as a

consequence of the latter, an increase in drain current

and transconductance; (iv) a decrease in low-frequency

noise; (v) a great reduction in hot carrier effects; (vi) a

steep subthreshold slope [2,3]. In addition, like other

dual gated devices, DGMOSFETs are claimed to be

more immune to short channel effects (SCE) than bulk

silicon MOSFETs and even than single-gate fully de-

pleted SOI MOSFETs [1]. This is due to the fact that the

two gate electrodes jointly control the carriers, thus

screening the drain field away from the channel [4]. This

characteristic would permit a much greater scaling down

of these devices than ever imagined for conventional

MOSFETs [5].

We have deeply studied the electron transport prop-

erties in these devices along the last years. We are trying

to summarize our results for this special issue in the

present paper. We have used a one-electron Monte

Carlo method to study the stationary electron transport

properties in DGSOI inversion layers (crystal orienta-

tion was considered to be 100), focusing our attention on

the evaluation of the stationary drift velocity and the

low-field mobility at room temperature. Electron quan-

tization in the inversion layer was appropriately taken

into account, and 1 D Poisson’s and 1 D Schroedinger’s

equations were self-consistently solved assuming a sim-

ple non-parabolic band model for the silicon. Once the

electron distribution in the silicon layer had been

determined, the Boltzmann transport equation was

solved by the Monte Carlo method. As demonstrated

elsewhere, [6–10], the presence of two close silicon–oxide

interfaces in both single- and double-gate SOI MOS-

FETs produces a significant difference with respect to

their standard-bulk counterparts. Therefore, we had to

develop improved models capable of taking into account

the effect of the roughness of both interfaces [7,8] on the

total scattering rate, and models to calculate the Cou-

lomb scattering rate in ultrathin SOI structures [10],

which have been shown to be different from the models

used for conventional silicon bulk inversion layers. We

considered n-channel DGSOI MOSFETs with different

values of silicon thickness and different temperatures.

The distribution of the electrons was evaluated by self-

consistently solving the Poisson and Schroedinger

equations. Electron mobility behavior at room temper-

ature is studied in Section 2 using a one-electron Monte

Carlo simulator to solve the Boltzmann transport

equation for different values of the silicon thickness, and

for different inversion charge concentrations. The role of

volume inversion as the temperature is reduced is

investigated and the electron mobility curves for DGSOI

MOSFETs are evaluated in Section 3. The relation of

electron mobility to the silicon thickness and the tem-

perature is shown.

There are two main types of DG MOSFETs: (1) a

symmetric type with both gates of identical work func-

tions so that the two surface channels turn on at the

same gate voltage and (2) an asymmetric type with dif-

ferent work functions for the gates and in which only

one channel turns on at the threshold voltage [11,12].

The threshold voltage of the symmetric device is deter-

mined by the work function of the gate material, and it is

negligibly dependent on the silicon thickness, the silicon

doping concentration or the oxide thickness [3]. As al-

ready known [12], the threshold voltage values obtained

with the symmetric structure are, depending on the type

of doping of the gate polys, too high (�1 V for pþ-

polysilicon gates) or too low (�)0.1 V for nþ-polysilicon

gates), and in any case, inadequate for the state-of-the-

art technology. Therefore, it is necessary to look for new

gate materials if we want these symmetric DGSOI de-

vices to have an appropriate threshold voltage to be used

in low-power and high speed applications. However,

Suzuki et al. [12] proved that it is still possible to control

the threshold voltage of a DGSOI device with polysil-

icon gates if an asymmetric nþ–pþ structure is used.

Therefore, from this point of view, it seems that an

asymmetric configuration could prove superior to a

symmetric one. However, one may wonder whether the

electron transport properties in asymmetrical-gate de-

vices will be the same as in symmetrical-gate devices.

The evolution of the electron mobility with the silicon

thickness in asymmetric devices is compared with that

for symmetric devices in Section 4.

Velocity overshoot (VO) is one of the most important

new effects observed in very short channel MOSFETs, as

this is directly related to the increase in current drive

and transconductance experimentally observed [13–16].

Velocity overshoot in symmetric DGSOI transistors is

characterized as a function of the silicon thickness and

of the electron inversion density in Section 5. A paral-

lelism between low-field electron mobility and velocity

overshoot peak is established. Finally, the main con-

clusions of this work are drawn in Section 6.

2. Electron mobility at room temperature

First of all [6,7], we studied the electron mobility in a

symmetric DGSOI device as a function of the transverse

effective field and silicon layer thickness at room tem-

perature. The contributions of the main scattering mec-

hanisms (phonon scattering, surface roughness scattering

due to both Si–SiO2 interfaces, and Coulomb interaction

with the interface traps of both interfaces (Nit ¼ 5� 1010

cm�2)) were taken into account and carefully analyzed.

We demonstrated that the contribution of surface scat-

tering mechanisms is by no means negligible; on the

0

200

400

600

0 10 20 30 400

75

150

225

300

375

EEFF=5x105V/cm

EEFF=5x106V/cm

Phonon+Surface Roughness

DGSO I

SG SO I

Ele

ctro

n M

obili

ty (

cm2 /V

s)

Silicon Thickness (nm)

Fig. 1. Evolution of electron mobility for a symmetric DGSOI

(solid line) and a SGSOI (dashed line) with the thicknesses of

the silicon layer. Phonon and surface roughness scatterings

have been taken into account.

F. G�amiz et al. / Solid-State Electronics 48 (2004) 937–945 939

contrary, it plays a very important role which must be

taken into account when calculating the mobility in these

structures. The structure we have considered consists of a

silicon layer sandwiched between two oxide layers. Two

polycrystalline silicon (polysilicon) gates were assumed

as control electrodes. The front upper and back lower

gates were nþ-doped (ND-poly ¼ 1� 1020 cm�3) and the

same gate voltage was applied simultaneously to both

gates (VG1 ¼ VG2 � VG). Different silicon layer thick-

nesses, ranging from Tw ¼ 1:5 nm to Tw ¼ 50:0 nm were

considered. We assumed that the silicon layer was left

undoped. In a DGMOSFET, short channel effects are

controlled by device geometry [4,5], while in a bulk FET

the short channel effects are controlled by doping

(channel doping and/or halo doping). Therefore, in

principle, the channel of a DGMOSFET can be un-

doped, which allows better carrier transport and avoids

threshold voltage fluctuation due to discrete, random

dopant placement.

Quantum size effects are known to become very

important in these devices (since carriers are confined by

the silicon thickness, which is comparable to the De

Broglie wavelength of the carriers) and therefore, the

self-consistent solution of Poisson’s and Schroedinger’s

equations is required to evaluate the spatial distribution

of the electrons in the silicon layer. To solve Poisson’s

equation, we considered a non-uniform adaptive mesh,

employing an iterative-Newton scheme. The actual

band-bending through the whole structure and the finite

height of the barrier at the Si–SiO2 interfaces were

considered. A non-parabolic band model for the silicon

was taken into account assuming a ¼ 0:5 eV, where a is

the parameter of non-parabolicity [17]. This limited our

study to low-electron energies (below 0.5 eV). The

effective electron masses were assumed to be those of

bulk silicon [6,18].

We basically show that two opposite trends appear

with respect to electron mobility as the silicon thickness

is reduced:

(i) On the one hand, the subband modulation effect

[19], produced by the splitting of the degeneracy of

the silicon conduction band due to size quantization.

The subband modulation effect produces a greater

separation between the energy subbands of non-

primed and primed valleys [20], and consequently

a redistribution of the electrons among the different

subbands, which causes an increase in the popula-

tion of non-primed subbands at the expense of the

population of primed subbands, which logically de-

creases. As the conduction effective mass of electrons

in non-primed valleys is lower (0:190m0, m0 being the

electron free mass) than the conduction effective

mass of electrons in primed valleys (0:315m0), an ini-

tial effect of subband modulation is a decrease in the

average conduction effective mass of the electrons.

The subband modulation effect also produces a

reduction in the intervalley scattering rate among

non-equivalent valleys, produced by the greater

energy separation between primed and non-primed

subbands. Both effects facilitate electron trans-

port, and therefore contribute to an increase in the

mobility.

(ii) On the other hand, the reduction in the silicon thick-

ness produces a greater confinement of the carriers,

and taking into account the uncertainty principle, an

increase in the phonon scattering rate [21], which im-

pedes electron transport, and therefore, contributes

to a decrease in the mobility. However, it has been

shown that for symmetric DGSOI inversion layers

at room temperature, in the range 5–20 nm (this

range depends on the inversion electron density,

Ninv) phonon scattering decreases instead of increas-

ing, and a phonon scattering rate lower than that for

bulk silicon inversion layers is obtained [6,22,23].

The variation in electron mobility in symmetric

DGSOI devices as Tw decreases was compared with that

in single-gate silicon-on-insulator (SGSOI) structures

and in bulk silicon inversion layers. For this purpose,

SGSOI devices with the same silicon thickness, gate

940 F. G�amiz et al. / Solid-State Electronics 48 (2004) 937–945

oxide thickness and doping concentration as symmetric

DGSOI devices are considered. (Buried oxide in SGSOI

devices was considered to be 80 nm thick). Fig. 1 shows

the evolution of electron mobility versus the silicon

thickness for different values of the transverse effective

field. Phonon and surface roughness scattering have

been considered. From this comparison we deter-

mined the existence of the following three regions: (i) An

initial region for thick silicon layers (Tw > 20–30 nm),

where the mobility for both structures tends to coin-

cide, approaching the bulk value. (ii) As Tw decreases we

show that volume inversion modifies the electron

transport properties by reducing the effect of all scat-

tering mechanisms and a reduction in the conduction

effective mass. Accordingly, the electron mobility in

symmetric DGSOI inversion layers increases by an

important factor which depends on the silicon thick-

ness and the transverse effective field. (iii) Finally, for

very small thicknesses, the limitations to electron

transport are due to the greater confinement of the

electrons because of the size quantization; therefore the

two mobility curves, which again coincide, fall abruptly.

5

10

15

20

25

30

35

1011 1012 10130.0

1.5

3.0

4.5

6.0

TSi=1.5nm

TSi=3nm

TSi=5nm

TSi=10nm

TSi=20nm

T= 25K

Ele

ctro

n M

obili

ty (

x103

cm2 /

Vs)

Ele

ctro

n M

obili

ty (

x103

cm2 /

Vs)

Inversion Electrons (cm-2)

1011 1012 1013

T= 130K

Fig. 2. Electron mobility curves in a symmetric DGSOI invers

We show the existence of a range of thicknesses of a

silicon layer (between 5 and 20 nm) in which electron

mobility is improved by 25% or more, due to volume

inversion. Therefore, volume inversion plays an impor-

tant role in the electron mobility in these symmetric

DGSOI devices as the silicon thickness is reduced below

20 nm.

3. Behavior at low temperatures

As shown in the section above, the distribution of the

electrons in the silicon layer plays a very important role

in the determination of transport properties of electrons

in symmetric DGSOI devices. It is well known that the

distribution of the electrons in inversion layers varies

greatly with temperature changes [20]. For example,

a priori, it is well known that as temperature decreases,

quantum size effects become more important, even for

bulk silicon inversion layers, where at low temperatures

the population of electrons in non-primed subbands is

0.0

2.5

5.0

7.5

10.0

12.5

15.0

0.0

0.2

0.4

0.6

0.8

1.0

T= 77K

1011 1012 1013

1011 1012 1013

Inversion Electrons (cm-2)

T= 300K

ion layer as a function of Ninv for different temperatures.

Ninv=5x1012 cm-2

0 10 20 30 40 500.0

0.5

1.0

1.5

2.0

2.5

3.0

Nor

mal

ized

Mob

ility

Silicon Thickness (nm)

T=25KT=77KT=130KT=200KT=300K

Fig. 4. Evolution of the factor lDGSOI

lBulkwith the silicon thickness

for different temperatures, lDGSOI being the mobility for sym-

metric DGSOI inversion layer with a silicon thickness Tw and

lBulk the electron mobility in a bulk silicon inversion layer at the

same temperature.

F. G�amiz et al. / Solid-State Electronics 48 (2004) 937–945 941

very high. As shown by Ando et al. [20] the fraction of

the electrons in the non-primed subbands in a bulk sil-

icon inversion layer is 1 for very low temperatures. This

means, for example, that the influence of subband

modulation effects becomes weaker and weaker as the

temperature is reduced.

Fig. 2 shows electron mobility curves versus the

inversion charge sheet for different values of silicon

thickness. Phonon and surface roughness scattering have

been included. Different temperatures were considered,

namely T ¼ 25 K, T ¼ 77 K, T ¼ 130 K and T ¼ 300 K.

It can be observed that, for all the temperatures con-

sidered, there is more than one trend in the electron

mobility as the silicon thickness decreases. In addition,

this trend strongly depends on the inversion electron

density. To see this more clearly, Fig. 3 shows the evo-

lution of the mobility with the silicon layer thickness for

the temperatures considered in this study. Note that all

the curves present the shape described in Section 2 above

for the behavior of the mobility in symmetric DGSOI

devices at room temperature. To obtain a clearer idea of

the effect of volume inversion, we have normalized each

mobility curve shown in Fig. 3 by the corresponding

value of the mobility in a bulk silicon inversion layer at

the same temperature. The results of this are shown in

Fig. 4. As can be observed, the improvement in the

mobility in a symmetric DGSOI inversion layer, lDGSOI,

with regard to the mobility in a bulk silicon inversion

layer, lBulk, is greater as the temperature is reduced: the

maximum improvement, lDGSOI

lBulk, is 1.35 at room temper-

ature for Tw ¼ 10 nm, this quotient reaching 2.33 for

T ¼ 25 K for the same silicon thickness.

0

1

2

Ele

ctro

n M

obili

ty (

x103

cm2 /V

s) T=25KT=77KT=130KT=200KT=300K

Ninv=1x1013cm-2

0 10 20 30 40 50Silicon Thickness (nm)

Fig. 3. Evolution of the electron mobility in a symmetric

DGSOI inversion layer with the silicon thickness for different

temperature values (Ninv ¼ 1� 1013 cm�2).

4. Symmetrical versus asymmetrical gate configuration

We have also solved the Poisson and Schroedinger

equations in asymmetric DGSOI devices, and have

evaluated the electron distribution for different values of

the silicon thickness and different values of the inversion

charge concentration. From the comparison of the two

kinds of devices (symmetric and asymmetric), we drew

the following conclusions for devices with Tw > 5 nm:

i(i) As the silicon thickness is reduced, the conduction

effective mass of electrons in the asymmetric case

is lower than that in the symmetric case. This effect

is produced because the lack of symmetry makes

electrons to be more confined towards the nþ-gate

side; as known, the greater the size quantization

the higher the population of non-primed subbands,

where the conduction effective mass of electrons is

lower. This would contribute to an increase in the

electron mobility in the former devices.

(ii) The greater confinement of electrons in the asym-

metric case, produced by the deeper potential well

in the nþ-gate side, produces an increase in the pho-

non scattering rate. This would contribute to a de-

crease in the mobility in the asymmetric case.

Therefore, taking both facts into account, a priori, it

is not possible to foresee the behavior of the mobility

until a solution of the Boltzmann transport equation is

provided.

Fig. 5 shows the evolution of the electron mobility

versus the silicon thickness for two values of the total

200

400

600

800

200

400

600

800

Phonon+Surface roughness

Ele

ctro

n M

obili

ty (

cm2 /V

s)

Symmetrical

Asymmetrical

N*inv=1x1013cm-2

N*inv=5x1012cm-2

0 10 20 30 40 50

Silicon Thickness (nm)

Fig. 6. Evolution of electron mobility for a symmetric nþ–nþ

DGSOI (solid line) and an asymmetric nþ–pþ DGSOI (dashed

line) with the thicknesses of the silicon layer. Two different

values of the inversion charge concentration were considered.

Only phonon and surface-roughness scattering were taken into

account.

200

400

600

800

200

400

600

800

Only phonons

Ele

ctro

n M

obili

ty(c

m2 /V

s)

Symmetrical

Asymmetrical

Symmetrical

Asymmetrical

N*inv=5x1012cm-2

N*inv=1x1013cm-2

0 10 20 30 40 50Silicon Thickness (nm)

Fig. 5. Evolution of electron mobility for a symmetric nþ–nþ

DGSOI (solid line) and an asymmetric nþ–pþ DGSOI (dashed

line) with the thicknesses of the silicon layer. Two different

values of the inversion charge concentration were considered.

Only phonon scattering was taken into account.

942 F. G�amiz et al. / Solid-State Electronics 48 (2004) 937–945

inversion charge concentration, N �inv, (symmetric-gate

devices in solid line and asymmetric-gate devices in da-

shed line). (In this section, N �inv is the electron concen-

tration in the whole silicon layer, while in the rest of the

work, i.e. when we are dealing with only symmetric

devices, Ninv is the electron concentration in the half of

the silicon layer). Only phonon scattering has been taken

into account in this figure. The first result obtained is

that the lack of symmetry in the asymmetric devices

results in a lower degree of mobility than in their sym-

metric counterparts, for silicon layer thicknesses in the

range 5 nm < Tw < 20 nm. Therefore, the second of the

effects (increase in the phonon scattering) rate is domi-

nant on the lower conduction effective mass. However,

for the thinnest samples (Tw < 3 nm) the two curves

(symmetric and asymmetric) tend to behave similarly

(although the mobility peak around 2–3 nm is lower in

the asymmetric-gate case). (This behavior is the direct

consequence of the superposition of the two opposite

trends mentioned in Section 2. For a detailed discussion

of phonon-limited mobility behavior in ultrathin SOI

devices see Ref. [6,9,24]). Therefore, we can conclude

that in the range 5 nm < Tw < 20 nm, phonon-limited

mobility in asymmetric-gate devices is considerably

below the phonon-limited mobility in symmetric DGSOI

due to the lack of volume inversion, and that for Tw < 3

nm phonon-limited mobility behaves similarly in both

devices, due to the geometrical confinement of carriers in

a very narrow space in both devices.

Phonon scattering is not the only scattering mecha-

nism which affects carriers transport in these devices. In

Ref. [6], we show that interface scattering mechanisms

are by no means negligible. Surface roughness scattering

due to the deviation of the Si/SiO2 interface from an

ideal plane is also an important scattering mechanism,

mainly for ultrathin silicon layers [7,8]. We have also

studied the evolution of the mobility with the silicon

thickness for both structures (symmetric and asymmetric

devices) when phonon and surface roughness scattering

are simultaneously taken into account. Fig. 6 shows the

evolution of the mobility with the silicon thickness for

two values of the inversion charge concentration (sym-

0 10 20 30 40 501.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

N*inv=5x1012cm-2

N*inv=1x1013cm-2

µ S

ymm

etric

al /µ

Asy

mm

etric

al

Phonon+Surface Roughness

Silicon Thickness (nm)

Fig. 7. Ratio between electron mobility for a symmetric nþ–nþ

DGSOI and an asymmetric nþ–pþ DGSOI with the thicknesses

of the silicon layer.

106

107

20

40

60

80

100

Vel

ocity

(cm

/s)

T=300KTW=5nm

TOX1=TOX2=5nm

(a)

(b)

Ninv=1.87x1012cm-2

Ninv=3.38x1012cm-2

Ene

rgy

(meV

)

Time (ps)1.2 2.22.01.81.61.4

Fig. 8. Monte Carlo calculated transient velocity overshoot

with a sudden application of a longitudinal field 1· 105 V/cm at

room temperature (applied at t ¼ 1:5 ps) for different inversion

charges (Ninv ¼ 1:87� 1012 cm�2 (solid line), Ninv ¼ 38:8� 1012

cm�2 (dotted line)). The initial steady-state electron distribution

was achieved under the influence of a longitudinal field of 1000

V/cm for t < 1:5 ps. (a) Electron velocity and (b) electron en-

ergy for a symmetric DGSOI transistor. T ¼ 300 K, Tw ¼ 5 nm,

Tox1 ¼ 2 nm, Tox2 ¼ 2 nm.

F. G�amiz et al. / Solid-State Electronics 48 (2004) 937–945 943

metric-gate devices in solid line and asymmetric-gate

devices in dashed line). From this figure we can conclude

that the lack of symmetry and volume inversion, and the

greater effect of surface roughness scattering mean that

electron mobility in asymmetric DGSOI devices is con-

siderably below the mobility curves corresponding to

symmetric devices, in the whole range of silicon thick-

nesses. This difference is larger in the range 5–25 nm,

where electron mobility in symmetric DGSOI inversion

layers is greatly improved by the volume inversion effect.

Fig. 7 shows that electron mobility in symmetric DGSOI

devices could be 2.5 times higher than that in asym-

metric devices.

5. Electron velocity overshoot

We simulated the evolution of the energy and

velocity of a distribution of electrons (Fig. 8) when a

sudden high longitudinal electric field (105 V/cm) is ap-

plied to a steady-state symmetric DGSOI electron dis-

tribution achieved under the influence of a lower electric

field (103 V/cm). As can be seen in Fig. 8, while electron

energy slowly tends to the new steady-state value cor-

responding to the new longitudinal electric field, the

electron velocity sharply increases, surpasses the new

steady-state value, reaches a maximum, and then finally

decreases until the new steady-state value is achieved. It

takes approximately 0.1 ps to reach the steady-state

velocity corresponding to the high longitudinal electric

field applied, corresponding to the energy relaxation

time values obtained for the 0.04–0.08 eV interval which

are the values shown by electrons when their velocities

are close to the velocity overshoot peak (VOP) (Fig. 8).

Fig. 9 shows the evolution of VOP with the silicon

thickness, Tw, for different values of Ninv. As observed,

the higher VOP values are obtained for ultrathin silicon

layers. Then the velocity peak decreases as the silicon

thickness increases until a minimum is reached at

around Tw ¼ 5 nm and then slightly increases with the

silicon thickness. This figure is very different from the

one showing the evolution of electron mobility with

silicon thickness (shown, for example, in Fig. 1 and

widely discussed elsewhere [6,22]). The situation is

completely different for velocity overshoot peak repre-

sentation (Fig. 9). At low silicon layer thicknesses,

higher values of VOP are obtained, in contrast to what

happens to the mobility curves. At these thicknesses

(Tw < 5 nm) the phonon scattering rate is very high, but

it is also true that the average conduction effective mass

attains lower values. Then, as the silicon thickness in-

creases, the average conduction effective mass also in-

creases, and the velocity overshoot peak decreases,

although the phonon scattering rate decreases and the

0 5 10 15 201.8

2.0

2.2

2.4

2.6

2.8

3.0

v pea

k(x1

07 cm

/s)

Silicon Thickness (nm)

Ninv=1x1012cm-2

Ninv=1x1013cm-2

Ninv=2x1013cm-2

Fig. 9. Evolution of the velocity overshoot peak with the silicon

thickness for different values of the electron inversion density,

Ninv in a symmetric DGSOI.

944 F. G�amiz et al. / Solid-State Electronics 48 (2004) 937–945

electron mobility increases. Thus, taking into account

Figs. 1 and 9, we conclude that for Tw < 5 nm the

behavior of electron mobility is mainly controlled by the

phonon scattering rate, i.e., the higher the phonon

scattering rate the lower the mobility, while the velocity

overshoot peak is controlled by the average conduction

effective mass evolution, i.e., the lower the conduction

effective mass the higher the VOP. To understand this

effect more clearly, we can recall the explanation of Prof.

Hess about velocity overshoot [25]: Assume that all

electrons start at k ¼ 0 at time t ¼ 0 (at which we apply

the high electric field). The electrons are then accelerated

and for a short time period do not scatter. The electron

acceleration will depend on the conduction effective

mass: the lower the conduction effective mass the higher

the electron velocity. Since all electrons go in the for-

ward direction, very high velocities will be reached. (The

lower the average conduction effective mass, the higher

the velocity peak). As time goes on scattering events

occur, and the electron average velocity decreases until

the new steady-state velocity value (corresponding to the

new high electric field) is reached.

Finally note that a very important result is obtained

from Figs. 1 and 9. From the mobility viewpoint, sym-

metric DGSOI transistors with silicon thicknesses

smaller than 5 nm are not adequate, since electron

mobility falls for such thicknesses, and therefore such

silicon thicknesses are excluded (Fig. 1). However, these

thicknesses (Tw < 5 nm) are the ones with the highest

VOP values. Therefore, in those devices where velocity

overshoot is important (ultrashort channel devices),

small silicon thickness should be used (Tw < 5 nm). In

contrast, in those devices where transport is limited by

electron mobility, silicon thicknesses in the range

5 nm < Tw < 10 nm should be used. This fact allows a

further reduction in the device channel length: DGSOI

transistors have been shown to meet the electrosta-

tic requirements for sub-25 nm channel length devices

[5,26]. However, for this to be so, the silicon thickness,

Tw, should be reduced in close proportion to the channel

length, Lg. In the case of symmetric DGSOI devices, for

example, theoretical studies show that the silicon

thickness, Tw, must fulfil the following relation with the

channel length, Lg [26–29]:

Tw <2

3Lg ð1Þ

According to the mobility criterium mentioned

above, Tw > 5 nm, and therefore, Lg > 7:5 nm. However,

for such channel lengths, velocity overshoot will be the

dominant effect, and therefore, silicon thicknesses

smaller than 5 nm could be used, and therefore, shorter

channels could be achieved.

6. Conclusions

A comprehensive study of electron transport in

double-gate silicon on insulator devices has been per-

formed. A Monte Carlo simulator was used to calculate

velocity overshoot effects and low-field mobilities at

room and lower temperatures. In general, electron

transport properties in symmetric DGSOI inversion

layers are governed by two opposite effects as the silicon

thickness decreases: the reduction in the average con-

duction effective mass and the increase in the phonon

scattering rate. However, we have seen that while elec-

tron mobility is mainly limited by the phonon scattering

rate, the velocity overshoot peak is mainly determined

by the average conduction effective mass, such that

highest VOP values are achieved for the smallest silicon

thicknesses, where the minimum values of the conduc-

tion effective mass (and the highest phonon scattering

rates) are obtained. In ultrashort channel length devices,

where velocity overshoot dominates the electron trans-

port through the channel, the best performance is ob-

tained as the silicon thickness is reduced below 5 nm.

However, from the point of view of electron mobility,

silicon thicknesses ranging from 5 to 10 nm are pre-

ferred. We have also compared the electron mobility in

symmetric and asymmetric devices. We have shown that

the lack of symmetry, together with volume inversion,

and the greater effect of surface roughness scattering,

means that the electron mobility in asymmetric DGSOI

devices is considerably below the mobility curves cor-

responding to symmetric devices, in the whole range of

silicon thicknesses. The difference is greater in the range

F. G�amiz et al. / Solid-State Electronics 48 (2004) 937–945 945

5–25 nm, where electron mobility in symmetric DGSOI

inversion layers is greatly improved by the volume

inversion effect. We have shown that mobility in sym-

metric devices could be 2.5 times higher than that in

their asymmetric counterparts.

Acknowledgements

This work has been carried out within the framework

of Research Project No. TIC2001-3243 supported by the

Spanish Government.

References

[1] Celler G, Cristoloveanu S. J Appl Phys 2003;93:4955–78.

[2] Balestra F, Cristoloveanu S, Benachir M, Brini J, Elewa T.

IEEE Electron Dev Lett 1987;EDL-9:410–2.

[3] Cristoloveanu S, Li SS. Electrical characterization of

silicon-on-insulator materials and devices. Boston: Kluwer;

1995.

[4] Frank DJ, Laux SE, Fischetti MV. IEDM Tech Dig, 1992.

p. 553–6.

[5] Wong H-SP, Frank DJ, Solomon PM. IEDM Tech Dig,

December 1998. p. 407–10.

[6] G�amiz F, Fischetti MV. J Appl Phys 2001;89:5478.

[7] Gamiz F, Roldan JB, Cartujo-Cassinello P, Lopez-

Villanueva JA, Cartujo P. J Appl Phys 2001;89:1764.

[8] Gamiz F, Roldan JB, Lopez-Villanueva JA, Cartujo-

Cassinello P, Carceller JE. J Appl Phys 1999;86:6854.

[9] Gamiz F, Roldan JB, Cartujo-Cassinello P, Carceller JE,

Lopez-Villanueva JA, Rodriguez S. J Appl Phys 1999;86:

6269.

[10] Gamiz F, Jimenez-Molinos F, Roldan JB, Cartujo-

Cassinello P. Appl Phys Lett 2002;80:3835.

[11] Tanaka T, Suzuki K, Horie H, Sugii T. IEEE Electron Dev

Lett 1994;15(Oct.):386–8.

[12] Suzuki K, Sugii T. IEEE Trans Electron Dev 1995;

42(Oct.):1940–8.

[13] Sai-Halasz GA, Wordeman MR, Kern DP, Rishton S,

Ganin E. IEEE Electron Dev Lett 1988;EDL-9:464.

[14] Chou SY, Antoniadis DA, Smith HI. IEEE Electron Dev

Lett 1985;EDL-6:665.

[15] Shahidi GG, Antoniadis DA, Smith HI. IEEE Electron

Dev Lett 1988;EDL-9:94.

[16] Assaderaghi F, Ko P, Hu C. IEEE Electron Dev Lett

1993;EDL-14:484.

[17] Fischetti MV, Laux SE. Phys Rev B 1993;48:2244.

[18] Jacoboni C, Reggiani L. Rev Mod Phys 1983;55:645.

[19] Takagi S, Koga J, Toriumi A. IEEE IEDM Tech Dig,

Piscataway, NJ, 1997. p. 219.

[20] Ando T, Fowler AB, Stern F. Rev Mod Phys 1982;54:

437.

[21] Price PJ. Ann Phys (NY) 1981;133:217.

[22] Shoji M, Omura Y, Tomizawa M. J Appl Phys 1997;81:

786–94.

[23] Shoji M, Horiguchi S. J Appl Phys 1999;85:2722.

[24] G�amiz F, Rold�an JB, L�opez-Villanueva JA. J Appl Phys

1998;83:4802–6.

[25] Hess K. In: Advanced theory of semiconductor devices.

Singapore: Prentice-Hall International; 1988. p. 137.

[26] Wong H-SP. IBM J Res Dev 2002;46(2/3):133.

[27] Hisamoto D. 2001 IEEE International Device Meeting.

Tech Dig, 2001. p. 19.3.1–4.

[28] Huang X, Lee W, Kuo C, Hisamoto D, Chang L,

Kedzierski J, et al. IEDM Tech Dig, 1999. p. 67.

[29] Doyle B, Arghavani R, Barlage D, Datta S, Duczy M,

Kavalieros J, et al. Intel Technol J 2002;6(2):42–55.