3.5.1 tugas Multiplexer3.5.2 Data Tabel Kebenaran MultiplexerInputOutput

SRABCDY

000xxx0

001xxx1

01x0xx0

01x1xx1

10xx0x0

10xx1x1

11xxx00

11xxx11

Keterangan : S : Selector 1R : selector 2X : kondisi dont careA : 0B : 1C : 2D : 3Y : Output

3.5.3 Rangkaian

Persamaannya :Y=(SRA)+(SRB)+(SRC)+(SRD)

3.5.4 Listing Programlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;entity multiplexer1 is Port ( S : in STD_LOGIC; R : in STD_LOGIC; A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; D : in STD_LOGIC; Y : out STD_LOGIC);end multiplexer1;

architecture Behavioral of multiplexer1 is

begin

Y Parameter TMPDIR set to xst/projnav.tmp

Total REAL time to Xst completion: 1.00 secsTotal CPU time to Xst completion: 0.29 secs --> Parameter xsthdpdir set to xst

Total REAL time to Xst completion: 1.00 secsTotal CPU time to Xst completion: 0.30 secs --> Reading design: multiplexer1.prj

TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Parsing 3) HDL Elaboration 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Partition Report 8) Design Summary 8.1) Primitive and Black Box Usage 8.2) Device utilization summary 8.3) Partition Resource Summary 8.4) Timing Report 8.4.1) Clock Information 8.4.2) Asynchronous Control Signals Information 8.4.3) Timing Summary 8.4.4) Timing Details 8.4.5) Cross Clock Domains Report

=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "multiplexer1.prj"Ignore Synthesis Constraint File : NO

---- Target ParametersOutput File Name : "multiplexer1"Output Format : NGCTarget Device : xa7a100t-2I-csg324

---- Source OptionsTop Module Name : multiplexer1Automatic FSM Extraction : YESFSM Encoding Algorithm : AutoSafe Implementation : NoFSM Style : LUTRAM Extraction : YesRAM Style : AutoROM Extraction : YesShift Register Extraction : YESROM Style : AutoResource Sharing : YESAsynchronous To Synchronous : NOShift Register Minimum Size : 2Use DSP Block : AutoAutomatic Register Balancing : No

---- Target OptionsLUT Combining : AutoReduce Control Sets : AutoAdd IO Buffers : YESGlobal Maximum Fanout : 100000Add Generic Clock Buffer(BUFG) : 32Register Duplication : YESOptimize Instantiated Primitives : NOUse Clock Enable : AutoUse Synchronous Set : AutoUse Synchronous Reset : AutoPack IO Registers into IOBs : AutoEquivalent register Removal : YES

---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Power Reduction : NOKeep Hierarchy : NoNetlist Hierarchy : As_OptimizedRTL Output : YesGlobal Optimization : AllClockNetsRead Cores : YESWrite Timing Constraints : NOCross Clock Analysis : NOHierarchy Separator : /Bus Delimiter : Case Specifier : MaintainSlice Utilization Ratio : 100BRAM Utilization Ratio : 100DSP48 Utilization Ratio : 100Auto BRAM Packing : NOSlice Utilization Ratio Delta : 5

=========================================================================

=========================================================================* HDL Parsing *=========================================================================Parsing VHDL file "D:\Project xilinx\bab32\multiplexer1.vhd" into library workParsing entity .Parsing architecture of entity .

=========================================================================* HDL Elaboration *=========================================================================

Elaborating entity (architecture ) from library .

=========================================================================* HDL Synthesis *=========================================================================

Synthesizing Unit . Related source file is "D:\Project xilinx\bab32\multiplexer1.vhd". Summary:no macro.Unit synthesized.

=========================================================================HDL Synthesis Report

Found no macro=========================================================================

=========================================================================* Advanced HDL Synthesis *=========================================================================

WARNING:Xst - The specified part-type was not generated at build time. XST is loading the full part-type and will therefore consume more CPU and memory.Loading device for application Rf_Device from file '7a100t.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.Loading device for application Rf_Device from file '7a100t.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.

=========================================================================Advanced HDL Synthesis Report

Found no macro=========================================================================

=========================================================================* Low Level Synthesis *=========================================================================

Optimizing unit ...

Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block multiplexer1, actual ratio is 0.

Final Macro Processing ...

=========================================================================Final Register Report

Found no macro=========================================================================

=========================================================================* Partition Report *=========================================================================

Partition Implementation Status-------------------------------

No Partitions were found in this design.

-------------------------------

=========================================================================* Design Summary *=========================================================================

Top Level Output File Name : multiplexer1.ngc

Primitive and Black Box Usage:------------------------------# BELS : 1# LUT6 : 1# IO Buffers : 7# IBUF : 6# OBUF : 1

Device utilization summary:---------------------------

Selected Device : xa7a100tcsg324-2i

Slice Logic Utilization: Number of Slice LUTs: 1 out of 63400 0% Number used as Logic: 1 out of 63400 0%

Slice Logic Distribution: Number of LUT Flip Flop pairs used: 1 Number with an unused Flip Flop: 1 out of 1 100% Number with an unused LUT: 0 out of 1 0% Number of fully used LUT-FF pairs: 0 out of 1 0% Number of unique control sets: 0

IO Utilization: Number of IOs: 7 Number of bonded IOBs: 7 out of 210 3%

Specific Feature Utilization:

---------------------------Partition Resource Summary:---------------------------

No Partitions were found in this design.

---------------------------

=========================================================================Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.

Clock Information:------------------No clock signals found in this design

Asynchronous Control Signals Information:----------------------------------------No asynchronous control signals found in this design

Timing Summary:---------------Speed Grade: -2

Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 1.190ns

Timing Details:---------------All values displayed in nanoseconds (ns)

=========================================================================Timing constraint: Default path analysis Total number of paths / destination ports: 6 / 1-------------------------------------------------------------------------Delay: 1.190ns (Levels of Logic = 3) Source: R (PAD) Destination: Y (PAD)

Data Path: R to Y Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 1 0.001 0.753 R_IBUF (R_IBUF) LUT6:I0->O 1 0.097 0.339 Y1 (Y_OBUF) OBUF:I->O 0.000 Y_OBUF (Y) ---------------------------------------- Total 1.190ns (0.098ns logic, 1.092ns route) (8.2% logic, 91.8% route)

=========================================================================

Cross Clock Domains Report:--------------------------

=========================================================================

Total REAL time to Xst completion: 84.00 secsTotal CPU time to Xst completion: 83.50 secs -->

Total memory usage is 755816 kilobytes

Number of errors : 0 ( 0 filtered)Number of warnings : 1 ( 0 filtered)Number of infos : 0 ( 0 filtered)

3.5.7 Synthesis File

3.1.7 Analisa DataDari hasil percobaan yang telah dilakukan dapat dianalisa bahwa pada perancangan Rangkaian Logika Multiplexer 4 masukan menggunakan 2 Gerbang NOT (Inverting), 4 Gerbang AND, dan 1 Gerbang OR dengan 4 masukan. Jadi dalam perancangannya hasil yang akan terjadi akan sesuai dengan tabel yaitu keluaran akan bernilai 1(High) sesuai dengan masukan oleh Set. Set di sini berfungsi sebagai pemilih apakah yang akan keluar itu nilai dari masukan yang mana.Library yang digunakan dalam xilinx masih menggunakan library standart yaitu menggunakan library use iee.std.logic.1164.all dan tidak menggunakan jenis library yang lain dikarenakan dalam listing hanya berupa proses logic dan belum menggunakan perintah perhitungan unyuk menggunakan lib lain seperi use.std.logic.arith.all.Pada strukur desain coding VHDL terdapat library yang berfungsi untuk paket dari program atau inti dari program yang sudah diisi dengan ieee . Pada didalam library tedapat : USE ieee.std_logic_1164.ALL yang artinya menggunakan logic standart 1164 didalam ieee, 1164 juga biasanya digunakan untuk gerbang (AND, OR,NOR,NAND dan XOR). Entity merupakan tempat untuk menentukan variabel masukan dan keluaran yang ada port. Architecture merupakan isi dari program yang diimplementasikan atau dianalogikan ke rangkaian, architecture juga merupakan dalam hardware Tanda (-) berfungsi untuk sebagai petunjuk pengguna dan tidak membaca program Dari tabel di atas di dapatkan Y= SRA+SRB+SRC+SRD. Y akan bernilai 1 ketika SRA+SRB+SRC+SRD. Nilai A=0,B=1,C=2,D=3,S=2 pangkat 0,R=2 pangkat 1.Pada saat semua inputan bernilai 0 maka output berlogika 1,saat R dan B bernilai 1 maka Y juga bernilai 1, saat S dan C bernilai 1 maka Y akan bernilai 1 dan pada saat R dan S bernilai 1 Y akan bernilai 1, selain itu Y akan berlogika 1. 3.1.8 KesimpulanMultiplexer adalah dari banyak masukan akan diseleksi oleh pemilih untuk kasus di sini menggunakan Selector yang nantinya akan dikeluarkan data atau nilainya ke keluaran.Cara kerjamultipleksera dalah memilih input yang akan diteruskan kebagian output dengan mengaturlogik akendalinya. . Dengan menggunakan selector, kita dapat memilih salah satu inputnya untuk dijadikan output.Sehingga dapat dikatakan bahwa multiplexer ini mempunyai 4 input, 2 selector ,dan 1 output.