tugas praktikum demulti

8/10/2019 tugas praktikum demulti

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3.5.3 Data Tabel Kebenaran Demultiplexer

INPUT OUTPUT

S R I W X Y Z

0 0 0 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1

Persamaannya :

W=SRI

X=SRI

Y=SRI

Z=SRI


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Listing Program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity demultiplexer1 is

Port ( s : in STD_LOGIC;

r : in STD_LOGIC;

i : in STD_LOGIC;

w : out STD_LOGIC;

x : out STD_LOGIC;

y : out STD_LOGIC;

z : out STD_LOGIC);

end demultiplexer1;

architecture Behavioral of demultiplexer1 is

begin

w


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Timing Diagram

File Report

Release 14.7 - xst P.20131013 (nt64)

Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

--> Parameter TMPDIR set to xst/projnav.tmp

Total REAL time to Xst completion: 3.00 secs

Total CPU time to Xst completion: 3.24 secs

--> Parameter xsthdpdir set to xst



--> Reading design: demultiplexer1.prj


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TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Compilation

3) Design Hierarchy Analysis

4) HDL Analysis

5) HDL Synthesis

5.1) HDL Synthesis Report

6) Advanced HDL Synthesis

6.1) Advanced HDL Synthesis Report

7) Low Level Synthesis

8) Partition Report

9) Final Report

9.1) Device utilization summary

9.2) Partition Resource Summary

9.3) TIMING REPORT

==========================================================

===============

* Synthesis Options Summary *

==========================================================

===============

---- Source Parameters

Input File Name : "demultiplexer1.prj"

Input Format : mixed


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Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "demultiplexer1"

Output Format : NGC

Target Device : xc3s500e-4-fg320

---- Source Options

Top Module Name : demultiplexer1

Automatic FSM Extraction : YES

FSM Encoding Algorithm : Auto

Safe Implementation : No

FSM Style : LUT

RAM Extraction : Yes

RAM Style : Auto

ROM Extraction : Yes

Mux Style : Auto

Decoder Extraction : YES

Priority Encoder Extraction : Yes

Shift Register Extraction : YES

Logical Shifter Extraction : YES

XOR Collapsing : YES

ROM Style : Auto

Mux Extraction : Yes

Resource Sharing : YES


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Asynchronous To Synchronous : NO

Multiplier Style : Auto

Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES

Global Maximum Fanout : 500

Add Generic Clock Buffer(BUFG) : 24

Register Duplication : YES

Slice Packing : YES

Optimize Instantiated Primitives : NO

Use Clock Enable : Yes

Use Synchronous Set : Yes

Use Synchronous Reset : Yes

Pack IO Registers into IOBs : Auto

Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed

Optimization Effort : 1

Keep Hierarchy : No

Netlist Hierarchy : As_Optimized

RTL Output : Yes

Global Optimization : AllClockNets

Read Cores : YES


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Write Timing Constraints : NO

Cross Clock Analysis : NO

Hierarchy Separator : /

Bus Delimiter :

Case Specifier : Maintain

Slice Utilization Ratio : 100

BRAM Utilization Ratio : 100

Verilog 2001 : YES

Auto BRAM Packing : NO

Slice Utilization Ratio Delta : 5

==========================================================

===============

==========================================================

===============

* HDL Compilation *

==========================================================

===============

Compiling vhdl file "D:/Project xilinx/bab33/demultiplexer1.vhd" in Library

work.

Entity compiled.

Entity (Architecture ) compiled.

==========================================================

===============


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* Design Hierarchy Analysis *

=========================================================================

Analyzing hierarchy for entity in library (architecture

).

==========================================================

===============

* HDL Analysis *

==========================================================

===============

Analyzing Entity in library (Architecture

).

Entity analyzed. Unit generated.

==========================================================

===============

* HDL Synthesis *

==========================================================

===============

Performing bidirectional port resolution...

Synthesizing Unit .

Related source file is "D:/Project xilinx/bab33/demultiplexer1.vhd".

Unit synthesized.


10/18

==========================================================

===============

HDL Synthesis Report

Found no macro

=========================================================================

==========================================================

===============

* Advanced HDL Synthesis *

==========================================================

===============

==========================================================

===============

Advanced HDL Synthesis Report

Found no macro

==========================================================

===============

==========================================================

===============

* Low Level Synthesis *


11/18

==========================================================

===============

Optimizing unit ...

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block demultiplexer1, actual ratio is 0.

Final Macro Processing ...

==========================================================

===============

Final Register Report

Found no macro

==========================================================

===============

==========================================================

===============

* Partition Report *

==========================================================

===============

Partition Implementation Status

-------------------------------


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No Partitions were found in this design.

==========================================================

===============

* Final Report *

=========================================================================

Final Results

RTL Top Level Output File Name : demultiplexer1.ngr

Top Level Output File Name : demultiplexer1

Output Format : NGC

Optimization Goal : Speed

Keep Hierarchy : No

Design Statistics

# IOs : 7

Cell Usage :

# BELS : 4

# LUT3 : 4

# IO Buffers : 7

# IBUF : 3

# OBUF : 4


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==========================================================

===============

Device utilization summary:

---------------------------

Selected Device : 3s500efg320-4

Number of Slices: 2 out of 4656 0%

Number of 4 input LUTs: 4 out of 9312 0%

Number of IOs: 7

Number of bonded IOBs: 7 out of 232 3%

---------------------------

Partition Resource Summary:

---------------------------

No Partitions were found in this design.

---------------------------

==========================================================

===============

TIMING REPORT


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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THETRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------------------

No clock signals found in this design

Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design

Timing Summary:

---------------

Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 6.376ns

Timing Detail:

--------------

All values displayed in nanoseconds (ns)


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=========================================================================

Timing constraint: Default path analysis

Total number of paths / destination ports: 12 / 4

-------------------------------------------------------------------------

Delay: 6.376ns (Levels of Logic = 3)

Source: s (PAD)

Destination: w (PAD)

Data Path: s to w

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 4 1.218 0.762 s_IBUF (s_IBUF)

LUT3:I0->O 1 0.704 0.420 x1 (x_OBUF)

OBUF:I->O 3.272 x_OBUF (x)

----------------------------------------

Total 6.376ns (5.194ns logic, 1.182ns route)

(81.5% logic, 18.5% route)

==========================================================

===============



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-->

Total memory usage is 242944 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)

Number of infos : 0 ( 0 filtered)


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Synthesis File

3.3.1.7

Analisa data

Demultiplxer atau dapat disingkat Demux merupakan suatu rangkaian

elektronika yang mempunyai output dua atau lebih dan hanya mempunyai satu

input (jumlah input dapat bergantung dari jumlah keluarannya), didalam

demultiplexer terdapat suatu pemilih keluaran/outputnya, jadi demultiplexer

merupakan rangkaian yang dapat dipilih outputnya untuk meneruskan data dari

inputnya. Berkebalikan dari multiplexer yang dapat dipilih intputnya,

demultiplexer ini yang dipilih adalah outputnya.

Demultiplexer merupakan kebalikan dari Multiplexer, Mempunyai satu

input data dan beberapa output( yang dicontrol oleh selector untuk menentukan

keluaran yang diinginkan) dan Merupakan Data Distributor (Pendistribusi data )

dengan Jumlah masukan (1 Input) < Jumlah Keluaran (Output).


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Pada program demultiplexer output yang bekerja adalah sesuai dengan

selector yang dipilih, ketika selektor S=0,R=0 , I =0 maka outputnya w = 0 , pada

saat selektor S=0 dan R=1 I : 1 maka outputnya x = 1, , saat selektor S=0 dan

R=1 I: output x= 0 , saat selektor S=1 dan R=1 I:0 ,maka outputnya z =0

saat selektor S=1 dan R=1 I:1 ,maka outputnya z =1.

Dari tabel dapat diketahui bahwa Input sama dengan outputan ,saat inputnya 0

maka outputnya juga sama dengan 0.

Fungsi dari selector adalah merupakan binery dari output , saat binery sudah

menunjukan hasil output , kondisi input harus bernilai 1 agar output bernilai satu.

3.3.1.8

Kesimpulan

Demultiplexer merupakan kebalikan dari Multiplexer, Mempunyai satu

input data dan beberapa output( yang dicontrol oleh selector untuk

menentukan keluaran yang diinginkan) dan Merupakan Data Distributor

(Pendistribusi data ) dengan Jumlah masukan (1 Input) < Jumlah Keluaran

(Output).

Fungsi dari selector adalah merupakan binery dari output , saat binery

sudah menunjukan hasil output , kondisi input harus bernilai 1 agar output

bernilai satu.

Library yang digunakan dalam xilinx masih menggunakan library standart

yaitu menggunakan library use iee.std.logic.1164.all dan tidak

menggunakan jenis library yang lain dikarenakan dalam listing hanya

berupa proses logic dan belum menggunakan perintah perhitungan unyuk

menggunakan lib lain seperi use.std.logic.arith.all.

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