Duke
Complex Multiplier for FFT
ECE 261 Project 2008
Team Members:
Xuan Bao Xiaoyan YinKai Wang Yang Jiang
Progress Report II
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Index
Overview of Our Present Step1
Basic Components2
4*4 Bits Signed Multipliers3
System Summarization4
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Overview of Our Present StepThis is the top level schematic of our project.
Every block here has already been fully defined.
All components and the whole system have correctly passed digital simulation.
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Introduction to the FIFO
This is the schematic of one FIFO component. It contains 8 Dflipflops with reset (for further testing) and works as a buffer for both input and output.
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Introduction to the FIFO
This is the digital simulation result of FIFO component. All possible patterns have been exhaustively tested. To make top level testing easier, we then rewrote the verilog for Dflipflop. The key part of codes is shown above.
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Index
Overview of Our Present Step1
2
4*4 Bits Signed Multipliers3
System Summarization4
Basic Components
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8-bit Ripple Carry Subtractor
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Index
Overview of Our Present Step1
Basic Components2
3
System Summarization4
4*4 Bits Signed Multipliers
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4*4 Bits Signed Multiplier
Quick Overview…Unsigned Multiplication: Signed Multiplication:
Algorithm: shift and addition Algorithm: Baugh-Woodley technique
Substitute AND2 gates to NAND2 gates, plus inverter… Schematics?
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Verification of Multiplier’s Results:
Results: 0*8=0 -3*-5=15
-3*3=-93*2=-6
-4*2=-8…
Realizes the multiplication of input X and Y, with the correct outcome Z=XY, which will be sent to Ripple Carry Adder and Subtractor to calculate: AD+BC & AC-BD
Consists of:
Nand2 × 6And2 × 10
Full Adders × 9Half Adders × 3
Inv × 1
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Index
Overview of Our Present Step1
Basic Components2
3
System Summarization4
Signed Multiplier
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(A+Bj)(C+Dj)=(AC-BD)+j(BC+AD)
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Feature estimation
Components
SUM*1 DIFF*1 MULT*4 FIFO*6
252 288 434*4 256*6 3812
Totaltransistors
Number of transistors
Area (mm^2)
0.5150.030*60.047*40.0330.028
FIFO*6MULT*4DIFF*1SUM*1
120%*Totalarea
Components
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Feature estimationPower consumption
( ) ( ) ( )
2
2 60.1 3812 12 0.8 / 2 2 / 5 10
0.0915 /
P C V f
m fF m
mW MHz
α
λ μ λ μ
= ⋅ ⋅ ⋅
= ⋅ ⋅ ⋅ ⋅ ⋅ ⋅⎡ ⎤⎣ ⎦=
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Floor Plan
overall
DIFF
MULTIPLIER
FIFO
FIFO
FIFOFIFO FIFO
FIFO
MULTIPLIER MULTIPLIER
MULTIPLIER
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