Solid-State Electronics 47 (2003) 1909–1915
www.elsevier.com/locate/sse
A unified I–V model for PD/FD SOI MOSFETs witha compact model for floating body effects
Sara Bolouki a, Mahnaz Maddah a, Ali Afzali-Kusha a,*, Mahmoud El Nokali b
a Department of Electrical and Computer Engineering, Faculty of Engineering, University of Tehran,
North Kargar Avenue, P.O. Box 14395/515, Tehran, Iranb Department of Electrical Engineering, University of Pittsburgh, 440 Benedum Hall, Pittsburgh, PA 15261, USA
Received 19 July 2002; received in revised form 29 May 2003; accepted 16 June 2003
Abstract
In this paper, a unified analytical I–V model for silicon-on-insulator (SOI) MOSFET is presented. The model is valid
for possible transitions between partially depleted and fully depleted modes during the transistor operation. It is based
on a non-pinned surface potential approach that is valid for all regions of operation. Small geometry effects such as
channel length modulation and high field mobility effects are also included. It also considers the self-heating effect,
which is important for complete modeling of SOI devices. To include the floating body effect, the parasitic current in
each mode of operation is modeled with a proper formulation while a smoothing function is invoked for the transition
between the operation modes. A comparison between the model and the experimental results shows good agreement
over a wide range of drain and gate voltages.
� 2003 Elsevier Ltd. All rights reserved.
Keywords: SOI MOSFETs; Unified model; Body effect; Parasitic BJT current; Fully depleted; Partially depleted
1. Introduction
Silicon-on-insulator (SOI) MOSFETs switch signals
faster, run at lower voltages and are much less vulner-
able to signal noise from background cosmic ray parti-
cles. Since on an SOI wafer each transistor is isolated
from its neighbor by a complete layer of silicon dioxide,
they are immune to ‘‘latch-up’’ problems and can be
spaced closer together than transistors built on bulk
silicon wafers. This results in smaller IC devices and
more chips per wafer. MOS transistors fabricated in SOI
technologies have relatively thin body regions which are
isolated from the Si substrate, as depicted in Fig. 1.
During normal device operation, this region is either
* Corresponding author. Tel.: +98-21-802-0403; fax: +98-21-
877-8690.
E-mail addresses: [email protected] (S. Bolouki),
[email protected] (M. Maddah), [email protected] (A. Afzali-
Kusha), [email protected] (M. El Nokali).
0038-1101/$ - see front matter � 2003 Elsevier Ltd. All rights reserv
doi:10.1016/S0038-1101(03)00259-4
fully- or partially depleted from majority carriers. The
amount of depletion is a function of the applied biases,
the silicon film thickness, and doping concentration.
Depending on the silicon film thickness, a transistor is
considered an fully depleted (FD) or a partially depleted
(PD) device. Compact I–V models for circuit simula-
tions have been developed for the FD operation mode
(see, e.g., [3–6]) and for the PD operation mode (see,
e.g., [1,2,7,8]). A practical device may, however, go
through transitions between FD and PD modes. For
example, an FD device becomes PD when the gate bias
approaches the flat-band voltage [9]. This may occur
during the read/write operation of SOI SRAM cells, if
the pass transistors are biased into accumulation. Simi-
larly, a short-channel PD device may become FD under
high enough applied gate and/or drain biases. An ac-
curate model therefore must take into account the
transitions between FD and PD modes of operation [9].
Two unified approaches have been published in the lit-
erature to deal with this modeling problem [9,10]. In [9],
the mode of operation is not known a priori and hence
ed.
Fig. 1. The cross-section of an SOI MOSFET.
1910 S. Bolouki et al. / Solid-State Electronics 47 (2003) 1909–1915
to calculate the drain current, a numerical technique
with an iterative procedure is employed to determine the
operation mode and calculate the front surface poten-
tial. This approach is computationally expensive for
circuit simulation applications. In [10], first the critical
gate voltage at which the transition between the opera-
tion modes occur, is obtained. Then, the surface po-
tential values for both PD and FD modes are calculated
and by utilizing a smoothing function, a unified surface
potential formula is proposed. This, however, may not
be an accurate model due to the fact that the values of
the front surface potential in the accumulation and the
strong inversion regions are considerably different from
numerical result [11].
In this work, we present a new unified I–V model for
PD/FD SOI, which includes channel length modulation
(CLM), self-heating, impact ionization and parasitic
BJT current effects. We first obtain the switching gate
voltage in terms of channel doping and SOI thickness
and thus for a given gate voltage, the mode of operation
is defined. Then an iterative procedure is used to extract
an accurate surface potential. This method, however, is
faster than the method of [9], as the mode of operation
has previously been determined. Having the unified
surface potential, we derive the I–V characteristics of the
device. Since the formulations for the impact ionization
and the parasitic BJT currents are different for PD and
FD modes of operation, to have an accurate unified
model, each mode of operation should use its corre-
sponding expressions. The previous works have not con-
sidered this difference and have taken into account either
PD [9] or FD [10] BJT current for their unified I–Vmodels. In our model, the floating body effects are cal-
culated for both modes of operation and then combined
to a unified form by using a smoothing function. The
simulation results show the accuracy and efficiency of
the presented model.
This paper organized as follows: In Section 2, we
discuss how to determine the operation mode and the
front surface potential. The modeling of the drain cur-
rent is given in Section 3. The results and discussion are
presented in Section 4 while Section 5 contains the
summary.
2. Operation mode and surface potential
In the modeling approach taken in this work, the
front surface potential is required to calculate the drain
current. As will be explained later in this section, for a
more efficient calculation of the potential, the operation
mode of the transistor should be known as a priori. The
mode, for a given film thickness and film doping, may
alternate between PD and FD when changing the (front)
gate bias voltage, VGF (the source is assumed to be at
zero potential). To determine the gate voltage at which
this mode change occurs, a critical gate voltage, VGFD, is
defined [10]. When VGF is larger than VGFD, the entire
film thickness becomes depleted and the device operates
in FD mode. For lower gate voltages, just part of the
film thickness is depleted and a floating body exits be-
tween the depleted part and the back oxide leading to
the PD operation mode. Solving the 2-D Poisson�sequation, one can obtain the critical gate voltage, VGFD,
as
VGFD ¼ qNcht2sies
þ VFf �tsiesVtCd
� expVGFD � ðVT � DVTÞ � gfVcs
gfVt; ð1Þ
where q is the electronic charge, Nch is the substrate
concentration, Vt is the thermal voltage, es is the silicon
permittivity, VT is the threshold voltage, DVT is the
threshold voltage reduction due to longitudinal electric
field, VFf is the front flat-band voltage, tsi is the SOI film
thickness, Cd is the bulk depletion capacitance, gf is a
factor accounting for the reduction of the free channel
charge due to the channel potential, and Vcs is the
channel-source electron quasi-Fermi potential. The crit-
ical gate voltage as a function of the film doping and
thickness is plotted in Fig. 2. As expected, this voltage
increases by increasing the doping and the thickness of
the film.
The next step in calculating the drain current is to
obtain the front surface potential. Poisson�s equation
and the boundary conditions at the Si/SiO2 interface are
utilized to derive an implicit equation of both the front
and back gate surface potentials, wsf and wsb, respec-
tively. Integrating 1-D surface potential and applying
the boundary conditions at the Si/SiO2 interface, the
following implicit equation for the front and back sur-
face potential is derived [9]:
Fig. 2. The critical gate voltage, VGFD, as a function of the film
thickness for different doping levels. For gate voltages higher
than VGFD, the transistor operates in FD mode.
Fig. 3. Front and back surface potentials for (a) tsi ¼ 150 nm,
(b) tsi ¼ 50 nm.
S. Bolouki et al. / Solid-State Electronics 47 (2003) 1909–1915 1911
1
c2ðVGB
�� VFb � usfÞ
2 � t2oxt2oxb
ðVGB � VFb � usbÞ2
�¼ Vte�ð2/f�VbÞVtðeusf=Vt � eusb=VtÞ þ Vtðe�usf=Vt � e�usb=VtÞþ usf � usb; ð2Þ
where toxf and toxb are the top and back insulator
thicknesses, respectively, Vb is the body potential and
VGB is the back gate voltage. Eq. (3) is then used to omit
the back surface potential from the above implicit ex-
pressions of the surface potentials.
wsb ¼0 in PD mode;wsf � qNcht2si=es in FD mode:
�ð3Þ
Comparing to [9], no iteration is necessary to determine
the operation mode as has been determined by Eq. (1) in
the proposed method. Hence, this new implicit equation
is simpler compared to the equations used in [9], and
can be solved using a second order Newton-Raphson�smethod coupled with a good initial guess in about 30%
less time. In Fig. 3, the front and back surface potentials
as a function of the gate voltage are shown for 50 and
150 nm-thick devices. The difference between the two
potentials in the PD mode is greater for a larger silicon
film thickness as is predicted by (3).
3. Drain current model
3.1. Channel current model
Having a unified front surface potential, the drain
current and the bulk charge can be derived following the
approach presented in [12]. Small geometry effects such
as channel length modulation (CLM) and high field
mobility effects are included in the formulation. Self-
heating effect, which is important for complete modeling
of SOI devices, is also included in our model based on
the approach of [13].
3.2. Floating body effects
SOI MOSFETs can operate with or without body
contact. In body-contacted structures, the body-ties,
which are typically non-ideal, consume extra area, in-
troduce source/drain asymmetry, and add more com-
plexity to layout and fabrication. For mainstream digital
applications, floating body operation is more desirable
[14]. The floating body however gives rise to a parasitic
BJT current flowing in the body of the transistor. In the
PD mode, a portion of the silicon film is not completely
depleted while in the FD mode the whole thickness is
depleted. This difference between the two modes leads to
different formulations for the parasitic BJT current in
the PD and FD modes of operation. For an accurate
unified model, corresponding formalism should be used
in each mode of operation. In the previously reported
1912 S. Bolouki et al. / Solid-State Electronics 47 (2003) 1909–1915
unified models, either the PD model [9] or the FD model
[10] has been used to include the parasitic BJT current in
the model. In the model proposed in this paper, we in-
corporate suitable models for the parasitic current in
each mode of operation. In the following, first, the
modeling approaches of the parasitic BJT and the im-
pact ionization currents in PD and FD modes are de-
scribed, and then a smoothing function is introduced to
model the parasitic current in the transition between the
modes.
3.2.1. The impact ionization and parasitic BJT effects in
FD
As the device is biased in the saturation region with a
large lateral electric field in the inversion layer at the
oxide/silicon interface, there is a channel current, Ich,which is due to the drifting of the electrons and is
modeled as discussed in Section 3. In the high electric
field region near the drain, the drifting electrons collide
with the lattice, giving rise to the generation of electron
and hole pairs. The generated electrons and holes move
in the opposite direction as a result of the electric field.
This results in the impact ionization current, Iii [3]. ForFD devices, the parasitic BJT with its emitter at the
source and its collector at the drain above the buried
oxide should be also considered. A portion of the impact
ionization current KIii is directed vertically toward the
buried oxide owing to the vertical field. As a result, in
the area above the buried oxide, accumulation of holes
exists, which leads to the activation of the parasitic bi-
polar transistor and the flow of the emitter and collector
currents, Ie and Ic, respectively. As the parasitic BJT is
activated, these holes recombine with the electrons in the
base region. In the parasitic bipolar device, a portion of
the collector current, K 0Ic, which is mainly composed of
electrons, moves toward the high electric field region due
to the vertical electric field. These electrons also collide
with the lattice, and consequently generate additional
electron-hole pairs increasing the impact ionization
current.
The total drain current, Id, is composed of the channel
current, Ich, the impact ionization current, and the col-
lector current [3]:
Id ¼ Ich þ Iii þ Ic: ð4Þ
The last two terms on the RHS comprise the parasitic
current, Ip.The collector current can be expressed in terms of the
emitter current Ie:
Ic ¼ a0Ie þ Icbo; ð5Þ
where Icbo is the leakage current between the collector
and the base with the emitter–base junction opened and
is given by [4]:
Icbo ¼ WtsiIso
1þ htðVGF � VTÞ: ð6Þ
Iso is the leakage current per unit crosses section in
the collector–base junction and ht is a fitting parameter.
The source current, Is, can be expressed as the sum of the
channel current, some portion of the impact ionization
current, ð1� KÞIii, and the emitter current [3]:
Is ¼ Ich þ ð1� KÞIii þ Ie: ð7Þ
The impact ionization current is a function of the
channel current and a portion of the collector current
flowing through the high electric filed region:
Iii ¼ ðM � 1ÞðIch þ K 0IcÞ: ð8Þ
Here M is the multiplication factor given by [3]:
M � 1 ¼ aðVds � VDSÞ exp �bVds � VDS
� �; ð9Þ
where a and b are process-dependent fitting parameters.
From a dc point of view, the source current should be
equivalent to the drain current. Therefore, using Eqs.
(5)–(8), one obtains the emitter current and the impact
ionization current as [3]:
Ie ¼KðM � 1Þ
1� ð1þ KK 0ðM � 1ÞÞa0Ich
þ 1þ KK 0ðM � 1Þ1� ð1þ KK 0ðM � 1ÞÞa0
Icho; ð10Þ
Iii ¼ ðM � 1Þ 1� a01� ð1þ KK 0ðM � 1ÞÞa0
Ich
�
þ K 0
1� ð1þ KK 0ðM � 1ÞÞa0Icbo
�; ð11Þ
where a0 is a fitting parameter. Combining (5), (6), (10),
(11), the total drain current is obtained as
Id ¼ GIch þ HIcbo; ð12Þ
where
G ¼ 1þ ðM � 1Þð1� ð1� KÞa0Þ1� ð1þ KK 0ðM � 1ÞÞa0
ð13Þ
and
H ¼ ðM � 1ÞK 0 þ 1
1� ð1þ KK 0ðM � 1ÞÞa0: ð14Þ
3.2.2. The impact ionization and parasitic BJT effects in
PD
The injection in the upper depletion region of the PD
mode is similar to that of the FD mode, but it is different
in the underlying neutral region where we assume low-
injection conditions. The BJT transport current is hence
Fig. 4. The transition between PD and FD parasitic current
using the smoothing function with a ¼ 1 and b ¼ 0:2. The
critical gate voltage is 1 V and the PD and FD parasitic currents
are normalized to 1.2 and 1.0, respectively.
S. Bolouki et al. / Solid-State Electronics 47 (2003) 1909–1915 1913
modeled as consisting of components in both the de-
pleted body and the neutral body [2]:
Ie ¼ Ireco expVbg2Vt
� �þ Ies exp
Vbg1Vt
� �; ð15Þ
where
Ireco ¼qniWtsiWbe
2sr; ð16Þ
Ies ¼ q
ffiffiffiffiffiffiDn
sn
rn2iNch
Wtsi ð17Þ
and Vb is the body–source voltage. The ideality factors g1and g2 are g1 � 1 and g2 � 2 [8]. In Eqs. (16) and (17) niis the intrinsic carrier concentration, sr is the recombi-
nation lifetime, sn is the electron lifetime in the neutral
region, Dn is the diffusion coefficient, and Wbe is the de-
pletion width of the body–emitter junction. The width is
given by
Wbe ¼
ffiffiffiffiffiffiffiffiffiffiffi2es/b
qNch
s;
/b ¼ 2Vt lnNch
ni
� �:
The body–source voltage ðVbÞ can be obtained using
[10]:
Vb ¼2KTq
lnIreco þ
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiI2reco � 4IesIch
p2Ies
!: ð18Þ
The lifetime parameters in (16) and (17) are important
parameters affecting the leakage current of the device
and hence the temperature dependencies of these pa-
rameters should be incorporated in the model. Follow-
ing [7], we invoke the following relations:
sn ¼ sn0T300
� �2:2
; ð19Þ
sr ¼ 2sn0T300
� �2:5
; ð20Þ
where sn0 is the electron lifetime at 300 K.
Finally, the total generation current due to the impact
ionization is expressed as
Iii ffi ðM � 1ÞðIch þ IeÞ; ð21Þ
where M is the multiplication factor given by (9). The
total source and drain currents can be found from Eqs.
(4) and (7).
Id ¼ Ich þ Iii þ Ic: ð22Þ
3.2.3. Compact model for the transition regime
For the transition regime between the FD and PD
modes, the proposed unified model makes use of the
following smoothing function to calculate the parasitic
current Ip. Using this function, the total current is
modeled in continues form:
Ip ¼Ip;FD
1þ a exp � VGF�VGFD
bVt
� þ Ip;PD
1þ a exp VGF�VGFD
bVt
� :ð23Þ
Here a and b are fitting parameters. The parasitic cur-
rent, Ip, reduces to Ip;FDðIp;PDÞ as VGF becomes larger
(smaller) than VGFD. The effect of the function on the
smooth transition between the two currents, when the
critical gate voltage is 1 V and the FD and PD parasitic
currents are normalized to 1.0 and 1.2, respectively, is
depicted in Fig. 4. The fitting parameters used for this
figure are a ¼ 1 and b ¼ 0:2.
4. Results and discussion
To illustrate the validity of the proposed unified
model, the I–V characteristics predicted by the model
have been compared with the measured dc drain char-
acteristics of four practical devices of [9]. For the first
device in which W =L ¼ 14=0:7 lm, tsi ¼ 150 nm, and
Nch ¼ 4:3� 1016 cm�3, the drain current versus the drain
voltages, VDS, for different values of gate voltage, VGS is
shown in Fig. 5(a). In this case, the critical gate voltage
is 0.53 V implying that the device operates in the PD
mode for the smallest gate voltage and in the FD mode
for the next five gate voltages. The characteristic with
Fig. 5. The drain current versus the drain voltage for different gate voltages with (a) W =L ¼ 14=0:35 lm and tsi ¼ 150 nm; (b)
W =L ¼ 14=0:7 lm and tsi ¼ 150 nm; (c) W =L ¼ 14=0:35 lm and tsi ¼ 200 nm; (d) W =L ¼ 14=0:35 lm and tsi ¼ 70 nm. Solid lines are
the results predicted by the model and circles are the experimental results [9].
1914 S. Bolouki et al. / Solid-State Electronics 47 (2003) 1909–1915
VGS ¼ 0:53 V, clearly reveal the well-known ‘‘kink’’ effect
which shows itself as an increase in the drain current
predicted by the model. Also, the effect of impact ion-
ization at higher drain voltages is more pronounced in
this device.
The critical gate voltage for the second transistor is
the same as in the previous case, which is due to the
same silicon thickness and channel doping. Therefore,
for the transistor whose I–V characteristics are given in
Fig. 5(b), the device operation mode is PD for the
smallest gate voltage and FD for the rest of the gate
voltages. Fitting both of the devices shown in Fig. 5(a)
and (b) with either an FD or PD model would be diffi-
cult, as a PD model would always show the presence of a
‘‘kink’’ and an FD model would never show a ‘‘kink’’.
Devices that have a thicker and thinner tsi were also
fitted to the model. Fig. 5(c) and (d) show results of
fitting the model to 200 and 70 nm thick devices. The
thicker tsi makes the device to be PD for the three
smallest gate voltages and in the FD mode for higher
voltages. This illustrates that even at relatively large tsivalues, a model containing the correct transitions from
PD to FD behavior is important. The critical gate
voltage is 1.57 V for this device. The thinner silicon
thickness of the device in Fig. 5(d) will cause this device
to behave more FD than the previously examined de-
vices and no kink effect is present. Self-heating is in-
creased for tsi ¼ 70 nm as expected and especially in
higher VGS curves of Fig. 5(d).
5. Summary
In this work, a unified I–V model for SOI MOSFETs
was presented. The model is valid for both fully depleted
and partially depleted modes of operation. First, a
critical gate voltage was utilized to determine the oper-
ation mode of the device. Then, using the Poisson�sequation the surface potential was calculated accurately
and efficiently. Having the front surface potential, the
drain current, including the channel length modulation,
the velocity saturation and the self-heating effects, were
calculated. The floating body effect which leads to kink
effect was also included in the model. To have an ac-
S. Bolouki et al. / Solid-State Electronics 47 (2003) 1909–1915 1915
curate model for the parasitic current due to the floating
body effect, the proper formulations for each mode of
operation were considered and then a function was used
for a smooth transition between the two modes of op-
eration. The results of the I–V characteristics predicted
by the model showed a very good agreement with the
experimental results.
Acknowledgements
The co-authors from the University of Tehran ac-
knowledge the financial support from the Research
Council of the University of Tehran. The authors also
appreciate Ali Khakifirooz of MIT for his kind assis-
tance and useful discussion.
References
[1] Hammed MY, Schroder DK. Analytical modeling of the
partially depleted SOI MOSFET. IEEE Trans Electron
Dev 2001;48(2):252–8.
[2] Suh D, Fossum JG. A physical charge-based model for
non-fully depleted SOI MOSFET�S and its use in assessing
floating-body effects in SOI CMOS circuits. IEEE Trans
Electron Dev 1995;42(4):728–36.
[3] Chen YG, Kue JB, Yu Z, Dutton RW. An analytical drain
current model for short-channel fully-depleted ultrathin
SOI NMOS devices. Solid State Electron 1995;38(12):
2051–7.
[4] Hu MC, Jsng SL, Chen YS, Liu SS, Lin JM. An analytical
fully-depleted silicon-on-insulator metal-oxide-semicon-
ductor field-effect-transistor model considering the effects
of self-heating, source/drain resistance, impact-ionization,
and parasitic bipolar junction transistor. Jpn J Appl Phys
Part 1 1997;36(5A):2606–13.
[5] Su LT, Antoniadis DA, Arora ND, Doyle BS, Krakauuer
DB. SPICE model and parameters for fully-depleted SOI
MOSFET�s including self-heating. IEEE Electron Dev Lett
1994;15(10):374–6.
[6] Jang SL, Lie SS. New submicron and deep submicron met-
al-oxide-semiconductor field-effect-transistor I–V and C–Vmodel. Jpn J Appl Phys Part 1 1998;37(7):3942–7.
[7] Lin SC, Kuo JB. Temperature-dependent kink effect model
for partially-depleted SOI NMOS devices. IEEE Trans
Electron Dev 1999;46(1).
[8] Lee MSL, Tenbroek BM, White W, Benson J, Uren MJ. A
physically based compact model of partially depleted SOI
MOSFETs for analog circuit simulation. IEEE J Solid-
State Circ 2001;36(1):110–21.
[9] Sleight JW, Rios R. A continuous compact MOSFET
model for fully- and partially depleted SOI devices. IEEE
Trans Electron Dev 1998;45(4):821–5.
[10] Jang SL, Huang B, Ju J-J. A unified analytical fully
depleted and partially depleted SOI MOSFET model.
IEEE Trans Electron Dev 1999;46(9):1872–6.
[11] Yu YS, Hwang SW, Ahn D. A unified analytical SOI
MOSFET model for fully- and partially-depleted SOI
devices. 2001 Asia-Pacific Workshop on Fundamental
and Application of Advanced Semiconductor Devices
(AWAD 2001), Cheju, Korea, 4–7 July 2001. p. 329–
34.
[12] Park HJ, Ko PK, Hu C. A charge sheet capacitance model
of short channel MOSFET�s for SPICE. IEEE Trans
Comput Aided Des 1991;10(3):376–89.
[13] Su LT, Chung JE, Antoniadis DA, Goodson KE, Flik MI.
Measurement and modeling of self-heating in SOI NMOS-
FET�s. IEEE Trans Electron Dev 1994;41(1):69–71.
[14] Wei A, Sherony MJ, Antoniadis DA. Effect of floating-
body charge on SOI MOSFET design. IEEE Trans
Electron Dev 1998;45(2):430–3.
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