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Transcript of NetFPGA - UNAB Creative
NetFPGA
Open Hardware and open so-ware for fast prototyping of networking
NetFPGA La:noamerica
Abril de 2015
NetFPGA genesis
Defini:on and main elements
Example: IPv4
Router
Who, How, Why
What to do next?
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 2
Outline
So#ware Defined Networks* (1)
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 3
Ver:cally integrated Closed, proprietary Slow innova:on Small industry
Specialized Opera:ng System
Specialized Hardware
Specialized Applica:ons
Horizontal Open interfaces Rapid innova:on Huge industry
Microprocessor
Open Interface
Linux Mac OS
Windows (OS) or or
Open Interface
App App App App App App App App App App App
* Taken from Nick McKeown presenta:on at Sigcomm 2012, Helsinki.
So#ware Defined Networks* (2)
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 4
Ver:cally integrated Closed, proprietary Slow innova:on
Horizontal Open interfaces Rapid innova:on
Control Plane
Control Plane
Control Plane or or
Open Interface
Specialized Control Plane
Specialized Hardware
Specialized Features
Merchant Switching Chips
Open Interface
App App App App App App App App App App App
* Taken from Nick McKeown presenta:on at Sigcomm 2012, Helsinki.
NetFPGA: An open pla;orm for networking teaching and research innovaEon
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 5
Open hardware
Open so-ware
Community
Innova:on on research and teaching
TradiEonal teaching on networking
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 6
Just technology transfer
Zero innova:on
Minimum technology development
New way to teach and learn about networks
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 7
MAC RxQ
CPU RxQ
MAC RxQ
CPU RxQ
MAC RxQ
CPU RxQ
MAC RxQ
CPU RxQ
Input Arbiter
Output Port Lookup
MAC TxQ
CPU TxQ
MAC TxQ
CPU TxQ
MAC TxQ
CPU TxQ
MAC TxQ
CPU TxQ
Output Queues
NetFPGA genesis
Defini:on and main elements
Example: IPv4
Router
Who, How, Why
What to do next?
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 8
Outline
NetFPGA Board Comparison
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 10
NetFPGA 1G 2006
NetFPGA 1G CML 2014
NetFPGA 10G 2010
NetFPGA 100G 2014
4 x 1Gbps Ethernet Ports
4 x 1Gbps Ethernet Ports
4 x 10Gbps Ethernet Ports
4 x 10Gbps Ethernet Ports
4.5 MB ZBT SRAM 64 MB DDR2 SDRAM
4.5 MB QDRII+SRAM 512 MB DDR3 DRAM
27 MB QDRII-‐SRAM 288 MB RLDRAM-‐II
27 MB QDRII-‐SRAM 8 GB DDR3 (up to 32)
PCI PCI Express x4 Gen. 2 PCI Express x8 Gen. 1 PCI Express x8 Gen. 3
Virtex II-‐Pro 50 Kintex 7-‐375T Virtex 5 TX240T Virtex 7 690T
NetFPGA board
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 11
PCI-Express
CPU Memory
PC with NetFPGA
Networking Software running on a standard PC
A hardware accelerator built with a Field Programmable Gate Array driving Gigabit network links
NetFPGA Board
FPGA
Memory
10GbE
10GbE
10GbE
10GbE
NetFPGA’s Defining CharacterisEcs
• Line-‐Rate - Processes back-‐to-‐back packets
ü Without dropping packets ü At full rate
- Opera:ng on packet headers ü For switching, rou:ng, and firewall rules
- And packet payloads ü For content processing and intrusion preven:on
• Open-‐source Hardware - Similar to open-‐source so-ware
ü Full source code available ü BSD-‐Style License for 1G and LGPL 2.1 for 10G
- But harder, because ü Hardware modules must mee:ng :ming ü Verilog & VHDL Components have more complex interfaces ü Hardware designers need high confidence in specifica:on of modules
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 12
Test-‐Driven Design
• Regression tests - Have repeatable results - Define the supported features - Provide clear expecta:on on func:onality
• Example: Internet Router - Drops packets with bad IP checksum - Performs Longest Prefix Matching on des:na:on address - Forwards IPv4 packets of length 64-‐1500 bytes - Generates ICMP message for packets with TTL <= 1 - Defines how to handle packets with IP op:ons or non IPv4
ü … and dozens more … Every feature is defined by a regression test
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 13
FPGA
Memory
10GE
10GE
10GE
10GE
Running the Router Kit
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 14
PCI
CPU Memory OSPF BGP
My Protocol user
kernel Routing
Table
IPv4 Router
10GE
10GE
10GE
10GE
Fwding Table
Packet Buffer
“Mirror”
FPGA
Memory
10GE
10GE
10GE
10GE
Enhancing Modular Reference Designs
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 15
PCI
CPU Memory
NetFPGA Driver
Java GUI Front Panel (Extensible)
PW-‐OSPF
In Q Mgmt
IP Lookup
L2 Parse
L3 Parse
Out Q Mgmt
10GE
10GE
10GE
10GE Verilog modules interconnected by FIFO interfaces
My Block
Verilog EDA Tools (Xilinx,
Mentor, etc.)
1. Design 2. Simulate 3. Synthesize 4. Download
FPGA
Memory
10GE
10GE
10GE
10GE
Creating new systems
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 16
PCI
CPU Memory
NetFPGA Driver
10GE
10GE
10GE
10GE
My Design
(1GE MAC is so-/replaceable)
Verilog EDA Tools (Xilinx,
Mentor, etc.) 1. Design 2. Simulate 3. Synthesize 4. Download
Tools + Reference Designs
• Compile designs • Verify designs • Interact with hardware
Tools
• Router (HW) • Switch (HW) • Network Interface Card (HW) • Router Kit (SW) • SCONE (SW)
Reference designs
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 18
OpenFlow (hUps://www.opennetworking.org/sdn-‐resources/openflow)
• The most prominent NetFPGA success • Has reignited the So-ware Defined Networking movement • NetFPGA enabled OpenFlow
- A widely available open-‐source development plaporm - Capable of line-‐rate and
• was, un:l its commercial uptake, the reference plaporm for OpenFlow.
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 20
Previous contributed projects
Pla;orm Project Contributor 1G OpenFlow switch Stanford University
Packet generator Stanford University NetFlow Probe Brno University NetThreads University of Toronto zFilter (Sp)router Ericsson Traffic Monitor University of Catania DFA UMass Lowell
10G Bluespec switch MIT/SRI Interna:onal Traffic Monitor University of Pisa NF1G legacy on NF10G Uni Pisa & Uni Cambridge Simple/berer DMA core Stanford RAMcloud project
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 21
Some Ongoing Projects
Compu:ng
• Stand alone compu:ng unit (CHERI so- core)
• Security and capabili:es over NetFPGA-‐10G (Cambridge & SRI)
Measurements
• Open Source Network Tester (6 contrib groups)
• Accurate Internet measurements (Cambridge & TAU)
SDN
• OpenFlow switch 1.4 (Cambridge & SRI)
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 22
Open Source Network Tester (www.osnt.org)
• OSNT-‐TG (Traffic Generator) - A single card, genera:ng packets on four 10GbE ports
• OSNT-‐MON (Traffic Monitor) - a single card, capturing packets from four 10GbE ports
• Hybrid OSNT - the combina:on of OSNT-‐TG and OSNT-‐MON - On a single card
• Scalable OSNT - Coordina:ng mul:ple generators and monitors - Synchronized by a common :me-‐base
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 23
Community
• NetFPGA website (hrp://neppga.org) and Wiki - Documenta:on - User’s Guide “so you just got your first NetFPGA” - Developer’s Guide “so you want to build a …” - Encourage users to contribute
• Forums - Support by users for users - Ac:ve community -‐ 10s-‐100s of posts/week
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 25
NetFPGA genesis
Defini:on and main elements
Example: IPv4
Router
Who, How, Why
What to do next?
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 26
Outline
Internet Protocol (IP)
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 27
Data
Data IP Hdr
Eth Hdr Data IP
Hdr
Data to be transmired:
IP packets:
Ethernet Frames:
Data IP Hdr Data IP
Hdr
Eth Hdr Data IP
Hdr Eth Hdr Data IP
Hdr
…
…
Internet Protocol (IP)
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 28
Data
Data IP Hdr …
16 32 4 1
Op:ons (if any)
Des:na:on Address
Source Address
Header Checksum Protocol TTL
Fragment Offset Flags Fragment ID
Total Packet Length T.Service HLen Ver
20 bytes
Basic operaEon of an IP router
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 29
R3
A
B
C
R1
R2
R4 D
E
F R5
R5 F R3 E R3 D Next Hop Des:na:on
D
Basic operaEon of an IP router
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 30
A
B
C
R1
R2
R3
R4 D
E
F R5
Forwarding tables
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 31
Entry Destination Port 1 2 ⋮
232
0.0.0.0 0.0.0.1 ⋮
255.255.255.255
1 2 ⋮
12
~ 4 billion entries
Naïve approach: One entry per address
Improved approach: Group entries to reduce table size
Entry Destination Port 1 2 ⋮
50
0.0.0.0 – 127.255.255.255 128.0.0.1 – 128.255.255.255
⋮ 248.0.0.0 – 255.255.255.255
1 2 ⋮
12
IP address 32 bits wide → ~ 4 billion unique address
IP addresses as a line
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 32
0 232-‐1
Entry DesEnaEon Port
1 2 3 4 5
Stanford Berkeley
North America Asia
Everywhere (default)
1 2 3 4 5
All IP addresses
North America Asia
Berkeley Stanford
Your computer My computer
Longest Prefix Match (LPM)
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 33
Entry Destination Port 1 2 3 4 5
Stanford Berkeley
North America Asia
Everywhere (default)
1 2 3 4 5
Universi:es
Con:nents
Planet
Data To: Stanford
Matching entries: • Stanford • North America • Everywhere
Most specific
Longest Prefix Match (LPM)
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 34
Entry Destination Port 1 2 3 4 5
Stanford Berkeley
North America Asia
Everywhere (default)
1 2 3 4 5
Universi:es
Con:nents
Planet
Data To: Canada
Matching entries: • North America • Everywhere
Most specific
ImplemenEng Longest Prefix Match
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 35
Entry Destination Port 1 2 3 4 5
Stanford Berkeley
North America Asia
Everywhere (default)
1 2 3 4 5
Most specific
Least specific
Searching
FOUND
Basic components of an IP router
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 36
Control Plane
Data Plane per-‐packet processing
Switching Forwarding Table
Rou:ng Table
Rou:ng Protocols
Management & CLI
So-ware
Hardware
Queuing
IP router components in NetFPGA
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 37
SCONE
Rou:ng Table
Rou:ng Protocols
Management & CLI
Output Port Lookup
Forwarding Table
Input Arbiter
Output Queues
Switching Queuing
Linux
Rou:ng Table
Rou:ng Protocols
Management & CLI
Router Kit
OR
So-ware
Hardware
NetFPGA genesis
Defini:on and main elements
Example: IPv4
Router
Who, How, Why
What to do next?
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 38
Outline
Who, How, Why
• Who uses the NetFPGA? - Teachers - Students - Researchers
• How do they use the NetFPGA? - To run the Router Kit - To build modular reference designs - IPv4 router - 4-‐port NIC - Ethernet switch, …
• Why do they use the NetFPGA? - To measure performance of Internet systems - To prototype new networking systems
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 39
NetFPGA in the Classroom (hrp://neppga.org/teachers.html)
• Stanford University - EE109 “Build an Ethernet Switch”
ü Undergraduate course for EE students: hrp://www.stanford.edu/class/ee109/ - CS344 “Building an Internet Router” (since ‘05)
ü Quarter-‐long course targeted at graduates: hrp://cs344.stanford.edu • Rice University
- Network Systems Architecture (since ‘08): hrp://comp519.cs.rice.edu/ • Cambridge University
- Build an Internet Router (since ‘09): hrp://www.cl.cam.ac.uk/teaching/current/P33/
• University of Wisconsin - CS838 “Rethinking the Internet Architecture”: hrp://pages.cs.wisc.edu/~akella/CS838/F09/
• University of Bonn - “Building a Hardware Router”: hrp://bit.ly/Kmo0rA
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 40
Typical NetFPGA Course Plan
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 41
Week Socware Hardware Deliver
1 Verify So-ware Tools Verify CAD Tools Write Design Document
2 Build So-ware Router Build Non-‐Learning Switch Run So-ware Router
3 Cmd. Line Interface Build Learning Switch Run Basic Switch
4 Router Protocols Output Queues Run Learning Switch
5 Implement Protocol Forwarding Path Interface SW & HW
6 Control Hardware Hardware Registers HW/SW Test
7 Interoperate So-ware & Hardware Router Submission
8 Plan New Advanced Feature Project Design Plan
9 Show new Advanced Feature Demonstra:on
NetFPGA genesis
Defini:on and main elements
Example: IPv4
Router
Who, How, Why
What to do next?
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 42
Outline
Start with an idea, then work on a project
• Think on any telema:cs applica:on running at the so-ware level. ¿Would it be useful to run part or all of it at hardware speed and security? - We can discuss ideas in our seminars
• It is :me to start planning your doctorate, master or undergraduate project. - This is a hot topic (state of the art in networking) - High chance to publish and to get accepted.
• Make connec:ons - Remember… community is one of the key NetFPGA elements - Begin connec:ng with us
• Learn by yourself … - We have the equipment
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 43
Learn Verilog or VHDL … and Python
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 44
• Module defini:on: module <module name> (<I/O signals>);
• I/O signals declara:ons input output
• Module func:onality • Module termina:on
endmodule
module example(in1,in2,out); input in1,in2; output out; //Module functionality ...... endmodule
example in1
in2 out
Scared by Verilog?
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 45
Try the Online Verilog tutor (with NetFPGA extensions) @ www-‐neppga.cl.cam.ac.uk
AUend the NetFPGA events like this ….
… and others from hrp://neppga.org/2014/#/events/
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 46
Acknowledgments (I)
• NetFPGA Team at Stanford University (Past and Present): - Nick McKeown, Glen Gibb, Jad Naous, David Erickson, G. Adam Covington, John W. Lockwood, Jianying Luo, Brandon Heller, Paul Hartke, Neda Behesh:, Sara Bolouki, James Zeng, Jonathan Ellithorpe, Sachidanandan Sambandan, Eric Lo
• NetFPGA Team at University of Cambridge (Past and Present): - Andrew Moore, David Miller, Muhammad Shahbaz, Mar:n Zadnik, Marhew Grosvenor, Yury Audzevich, Neelakandan Manihary-‐Bojan, Georgina Kalogeridou, Jong Hun Han, Noa Zilberman, Gianni An:chi, Marco Forconesi
• NetFPGA La:noamerica - Manuel Jaimes, Diana Parra, Johana Manrique, John Padilla, Dixon Salcedo
• All Community members (including but not limited to): - Paul Rodman, Kumar Sanghvi, Wojciech A. Koszek, Yahsar Ganjali, Mar:n Labrecque, Jeff Shafer, Eric Keller , Tatsuya Yabe, Bilal Anwer, Yashar Ganjali, Mar:n Labrecque, Kees Vissers, Michaela Blor, Shep Siegel
NetFPGA: Open Hardware and open so-ware for fast prototyping of networking 47