COURSE HANDOUT - LBRCE

LAKKIREDDY BALI REDDY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

(Autonomous & Affiliated to JNTUK, Kakinada & Approved by AICTE, New Delhi, NAAC Accredited with ‘A’ grade, Accredited by NBA, Certified by ISO 9001:2015)

L B Reddy Nagar, Mylavaram-521 230, Krishna District, Andhra Pradesh.

COURSE HANDOUT

PROGRAM : M.Tech. I-Sem., ECE

ACADEMIC YEAR : 2017-18

COURSE NAME & CODE : Embedded System Design Lab & 17VE61

L-T-P STRUCTURE : 0-0-2

COURSE CREDITS : 1

COURSE INSTRUCTOR : Mr. G.Venkat Rao

COURSE COORDINATOR : Mr. G.Venkat Rao

COURSE OBJECTIVE: In This Laboratory student will learn about

COURSE ARTICULATION MATRIX (Correlation between COs&POs,PSOs):

CO Statement At the end of the course, student will be able to

PSO

1 PSO

2 PSO

3 PSO

4 PSO

5

1 Develop the Assembly Language Programs for ARM

processors.

1 2 3 3

2 Develop the interfacing programs for ARM processors

and I/O devices. 1 2 3 3

3 Design an Embedded System using the FPGA and

EDK tools. 1 2 3 3 3

Note: Enter Correlation Levels 1 or 2 or 3. If there is no correlation, put ‘-’ 1- Slight (Low), 2 – Moderate (Medium), 3 - Substantial (High).

BOS APPROVED REFERENCE BOOKS:

1 JHON.F.Wakerly, “Digital Design Principles & Practices” III Edition, Prentice Hall Publishers.

EMBEDDED SYSTEM DESIGN LAB SCHEDULE (LESSON PLAN)

S.No. Topics to be covered

No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

CYCLE-1

1. ARM Programming Introduction

2 16-08-2018

TLM2

2. ARM Assembly Language

Programming-I

2 23-08-2018

TLM5,8


Programming-II

2 30-08-2018

TLM5,8

4. Program to Interface 8 Bit LED 2 06-09-2018

TLM5,8

5.

Program to demonstrate Time

delay program using built in

Timer/Counter feature

2 20-09-2018

TLM5,8

6.

Program to Displaying a

message in a 2 line x 16

Characters LCD display and

verify the result in debug

terminal.

2 27-09-2018

TLM5,8

7. Generation of PWM Signal 2 03-10-2018 TLM5,8

CYCLE-2

8. Serial Communication

2 25-10-2018

TLM5,8

9. Traffic light Controller 2 01-11-2018 TLM5,8

10. Stepper motor Controller 2 08-11-2018 TLM5,8

11. Program to demonstrate I2C

Interface on IDE environment

2 15-11-2018

TLM5,8

12.

Design of System On Chip

platform using Xilinx FPGAs

and Embedded Development Kit

2 22-11-2018

TLM5,8

Tools

13.

Hardware Software co-design

using Xilinx EDK Tools and

Advanced FPGA Board Zynq

7000 series

2 29-11-2018

TLM5,8

14. Revision lab 2 06-12-2018 TLM5,8

15. Internal Examination 2 13-12-2018

No. of classes required to complete LAB No. of classes conducted:

Contents beyond the Syllabus

Teaching Learning Methods

TLM1 Chalk and Talk TLM4 Problem Solving TLM7 Seminars or GD

TLM2 PPT TLM5 Programming TLM8 Lab Demo

TLM3 Tutorial TLM6 Assignment or Quiz TLM9 Case Study

ACADEMIC CALENDAR:

Description From To Weeks

Orientation Classes 13-08-2018 18-08-2018 1w

I Phase of Instructions-1 20-08-2018 06-10-2018 7W

I Mid Examinations 08-10-2018 13-10-2018 1 W

II Phase of Instructions 15-10-2018 15-12-2018 9W

II Mid Examinations 17-12-2018 22-12-2018 1 W

Preparation and Practicals 24-12-2018 29-12-2018 1W

Semester End Examinations 31-12-2018 12-01-2019 2W

EVALUATION PROCESS:

Evaluation Task COs Marks

Day to Day work 1 A1=10

Record Writing 2 A2=10

Internal Lab Examination 1,2 B=10

Viva voce 1,2 C=10

Cumulative Internal Examination : A+B+C 3 A+B+C=40

Semester End Examinations 3 D=60

Total Marks: A+B+C+D 3 100

G.Venkat Rao G.Venkat Rao Dr.P.Lachi Reddy Dr.Y.Amar Babu

Course Instructor Course Coordinator Module Coordinator BOS Chairman&HOD




COURSE HANDOUT

Part – A

PROGRAM : M. Tech., I Sem., ECE (VLSI & ES)


COURSE NAME & CODE : Advanced Computer Architecture – 17VE90


COURSE CREDITS : 3

COURSE INSTRUCTOR : Dr. P. Lachi Reddy, Professor

COURSE COORDINATOR : Dr. P. Lachi Reddy, Professor

Pre-Requisite : Computer Organization

COURSE OBJECTIVE: In this course student will learn about the

classification of parallel architectures, mechanisms, general pipelining,

vector processing and its architecture, multiprocessors and its

interconnected networks, VLSI architectures and Data flow computers and their architectures.

COURSE ARTICULATION MATRIX(Correlation between Cos, POs &

PSOs):


PSO

1

PSO

2 PSO

3 PSO

4 PSO

5

CO1 Identify the differences between serial processing and parallel

processing architectures and their applications

1 2

CO2 Describe the functionality of pipelining and vector processor

structures, hazards in various pipelining structures

1 2

CO3 Develop the computer systems using SIMD processors with various

interconnection networks

2 2 3

CO4 Design the multi-processor systems with different memory

configurations

2 2 3

CO5 Analyze the working of Instruction flow computers and Data flow

computers for VLSI computations

2 2

Note: Enter Correlation Levels 1 or 2 or 3. If there is no correlation, put ‘-’

1- Slight(Low), 2 - Moderate(Medium), 3 - Substantial (High).

BOS APPROVED TEXT BOOKS:

T1. Kai Hwang and Faye A. Briggs, “Computer Architecture and Parallel Processing”,

McGraw Hill International Edition, 2000.


R1. Sima D, Fountain T and Peter Kacsuk, “Advanced Computer Architectures: A Design

Space Approach”, Pearson Education, 2005.

R2 John L. Hennessy and David a. Patterson, “Computer Architecture A Quantitative

Approach”, Elsevier, Fourth Edition, 2008.

R3.

Kai Hwang, “Advanced Computer Architecture: Parallelism, Scalability,

Programmability”, TMH, 2000.

Part - B COURSE DELIVERY PLAN (LESSON PLAN):

UNIT-I: INTRODUCTION TO PARALLEL PROCESSING

S. No.

Topics to be covered No. of

Classes Required

Tentative Date of

Completion

Actual Date of

Completion

Teaching Learning

Methods

Learning

Outcome

COs

Text

Book

followed

HOD Sign

Weekly

1. R-17 Regulations &

Guidelines 1 13.08.2018 TLM1

2. R-17 Course Structure & Add on course

1 14.08.2018 TLM1

3. Introduction to ACA subject

1 16.08.2018 TLM1 T1

4. Fundamentals of Computer Architecture

1 17.08.2018 TLM1, TLM2 CO1 T1

5.

Trends Towards Parallel Processing, Parallel Processing Mechanisms

1 20.08.2018 TLM1, TLM2 CO1 T1

6. Architectural Classification

1 21.08.2018 TLM1, TLM2 CO1 T1

7. Parallel Computer

Structures, Pipeline Computers

1 23.08.2018 TLM1, TLM2 CO1 T1

8. Array Computers,

Multi Processor Systems

1 24.08.2018 TLM1, TLM2 CO1 T1

9. Data Flow and New Concepts

1 27.08.2018 TLM1, TLM2 CO1 T1

10. Parallel Processing Applications

1 28.08.2018 TLM1, TLM2 CO1 T1

11. SEMINAR 2 30.08.2018, 31.08.2018

TLM1, TLM2 CO1 T1

No. of classes required to complete UNIT-I

12

No. of classes taken:

UNIT-II: PRINCIPLES OF PIPELINING AND VECTOR PROCESSING

S. No.


Classes Required

Tentative Date of

Completion

Actual Date of

Completion


Learning

Outcome

COs

Text

Book

followed

HOD Sign

Weekly

12. Principles of Linear

Pipelining 1 04.09.2018 TLM1, TLM2 CO2 T1

13. General Pipelines and Reservation

Tables,

1 06.09.2018 TLM1, TLM2 CO2 T1

14. Interleaved Memory

Organizations 1 07.09.2018 TLM1, TLM2 CO2 T1

15. Design of Pipelined

Instruction Units 1 10.09.2018 TLM1, TLM2 CO2 T1

16. Instruction Prefetch

and Branch Handling

1 11.09.2018 TLM1, TLM2 CO2 T1

17. Data Buffering and

Busing Structures 1 14.09.2018 TLM1, TLM2 CO2 T1

18. Internal Forwarding

and Register

Tagging

1 17.09.2018 TLM1, TLM2 CO2 T1

19. Hazard Detection and Resolution

1 18.09.2018 TLM1, TLM2 CO2 T1

20. Job Sequencing and

Collision Prevention 1 20.09.2018 TLM1, TLM2 CO2 T1

21. Characteristics of Vector Processing

1 24.09.2018 TLM1, TLM2 CO2 T1

22. Pipelined Vector

Processing Methods 1 25.09.2018 TLM1, TLM2 CO2 T1

23. SEMINAR 2 27.09.2018, 28.09.2018

TLM1, TLM2 CO2 T1

No. of classes required to complete UNIT-II

13


UNIT-III: STRUCTURES AND ALGORITHMS FOR ARRAY PROCESSORS

S. No.


Classes Required

Tentative Date of

Completion

Actual Date of

Completion


Learning

Outcome

COs

Text

Book

followed

HOD Sign

Weekly

24. SIMD Array

Processors, 1 01.10.2018

TLM1, TLM2 CO3 T1

25. SIMD Computer Organizations

1 04.10.2018 TLM1, TLM2

CO3 T1

26. Inter PE

Communications 1 05.10.2018

TLM1, TLM2

CO3 T1

27. SIMD Interconnection

Networks

1 15.10.2018 TLM1, TLM2

CO3 T1

28. Parallel Algorithms for Array Processors

1 16.10.2018 TLM1, TLM2

CO3 T1

29. SIMD Matrix

Multiplication 1 19.10.2018

TLM1, TLM2 CO3 T1

30. Parallel Sorting on Array Processors

1 22.10.2018 TLM1, TLM2

CO3 T1

31. Associative Memory

Organizations 1 23.10.2018

TLM1, TLM2

CO3 T1

32. Associative Processors

1 25.10.2018 TLM1, TLM2

CO3 T1

33. SEMINAR 2 26.10.2018,

29.10.2018

TLM1, TLM2 CO3 T1

No. of classes required to complete UNIT-III

11


UNIT-IV: MULTIPROCESSOR ARCHITECTURES

S. No.


Classes Required

Tentative Date of

Completion

Actual Date of

Completion


Learning

Outcome

COs

Text

Book

followed

HOD Sign

Weekly

34. Functional

Structures 2

30.10.2018, 01.11.2018

TLM1, TLM2 CO4 T1

35. Interconnection Networks

2 02.11.2018, 05.11.2018

TLM1, TLM2

CO4 T1

36. Parallel Memory

Organizations 1 06.11.2018

TLM1, TLM2 CO4 T1

37. Interleaved Memory Configurations

1 08.11.2018 TLM1, TLM2

CO4 T1

38. Multi Cache

Problems and

Solutions

1 09.11.2018 TLM1, TLM2

CO4 T1

39. Multiprocessor

Operating Systems 1 12.11.2018

TLM1, TLM2 CO4 T1

40. Exploiting

Concurrency for Multiprocessing

1 13.11.2018 TLM1, TLM2 CO4 T1

41. Language Features

to Exploit Parallelism

1 15.11.2018 TLM1, TLM2 CO4 T1

42. Detection of

Parallelism in

Programs

1 16.11.2018 TLM1, TLM2 CO4 T1

43. SEMINAR 2 19.11.2018, 20.11.2018

TLM1, TLM2 CO4 T1

No. of classes required to complete UNIT-IV

13


UNIT-V: DATA FLOW COMPUTERS AND VLSI COMPUTATIONS

S. No.


Classes Required

Tentative Date of

Completion

Actual Date of

Completion


Learning

Outcome

COs

Text

Book

followed

HOD Sign

Weekly

44. Data Driven

Computing and Languages

2 22.11.2018, 23.11.2018

TLM1, TLM2 CO5 T1

45.

Data Flow Computer

Architectures 2

26.11.2018,

27.11.2018

TLM1, TLM2

CO5 T1

46. VLSI Computing Structures

1 29.11.2018 TLM1, TLM2

CO5 T1

47. The Systolic Array Architecture

1 30.11.2018 TLM1, TLM2

CO5 T1

48. Reconfigurable

Processor Array 1 03.12.2018

TLM1, TLM2 CO5 T1

49. VLSI Matrix Arithmetic

Processors

1 04.12.2018 TLM1, TLM2

CO5 T1

50. VLSI Arithmetic

Modules 1 06.12.2018

TLM1, TLM2

CO5 T1

51. Partitioned Matrix

Algorithms, Matrix

Arithmetic Pipelines

1 07.12.2018 TLM1, TLM2

CO5 T1

52. SEMINAR 2 10.12.2018, 11.12.2018

TLM1, TLM2

CO5 T1

No. of classes required to

complete UNIT-V 12



S. No.


Classes Required

Tentative Date of

Completion

Actual Date of

Completion


Learning

Outcome

COs

Text

Book

followed

HOD Sign

Weekly

53. The MPP System Architecture

1 13.12.2018 TLM1, TLM2 T1

54. The C.mmp Multiprocessor System

1 14.12.2018 TLM1, TLM2

T1





ACADEMIC CALENDAR:


Orientation Programme 13-08-2018 18-08-2018 1 W

I Phase of Instructions-1 20-08-2018 06-10-2018 7 W


II Phase of Instructions 15-10-2018 15-12-2018 9 W


Preparation and Practicals 24-12-2018 29-12-2018 1 W

Semester End Examinations 31-12-2018 12-01-2019 2 W

Part - C EVALUATION PROCESS:


MID – I 1, 2 40

MID – II 3, 4, 5 40

Evaluation of Mid Marks: A = 75% of Max(A1, A2) + 25% of Min(A1, A2) 1,2,3,4,5 A=40

Semester End Examinations 1,2,3,4,5 B=60

Total Marks: A+B 1,2,3,4,5 100

PROGRAMME EDUCATIONAL OBJECTIVES (PEOs):

PEO1: To Attain a solid foundation in Electronics & Communication Engineering

fundamentals with an attitude to pursue continuing education. PEO2: To Function professionally in the rapidly changing world with advances in

technology. PEO3: To Contribute to the needs of the society in solving technical problems using

Electronics & Communication Engineering principles, tools and practices. PEO4: To Exercise leadership qualities, at levels appropriate to their experience, which

addresses issues in a responsive, ethical, and innovative manner.

PROGRAMME OUTCOMES (POs):

PO1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex

engineering problems. PO2: Problem analysis: Identify, formulate, review research literature, and analyze

complex engineering problems reaching substantiated conclusions using first

principles of mathematics, natural sciences, and engineering sciences. PO3: Design/development of solutions: Design solutions for complex engineering

problems and design system components or processes that meet the specified needs

with appropriate consideration for the public health and safety, and the cultural,

societal, and environmental considerations. PO4: Conduct investigations of complex problems: Use research-based knowledge and

research methods including design of experiments, analysis and interpretation of

data, and synthesis of the information to provide valid conclusions. PO5: Modern tool usage: Create, select, and apply appropriate techniques, resources, and

modern engineering and IT tools including prediction and modeling to complex

engineering activities with an understanding of the limitations. PO6: The engineer and society: Apply reasoning informed by the contextual knowledge

to assess societal, health, safety, legal and cultural issues and the consequent

responsibilities relevant to the professional engineering practice. PO7: Environment and sustainability: Understand the impact of the professional

engineering solutions in societal and environmental contexts, and demonstrate the

knowledge of, and need for sustainable development. PO8: Ethics: Apply ethical principles and commit to professional ethics and

responsibilities and norms of the engineering practice. PO9: Individual and team work: Function effectively as an individual, and as a member

or leader in diverse teams, and in multidisciplinary settings. PO10: Communication: Communicate effectively on complex engineering activities with

the engineering community and with society at large, such as, being able to

comprehend and write effective reports and design documentation, make effective

presentations, and give and receive clear instructions.

PO11: Project management and finance: Demonstrate knowledge and understanding of

the engineering and management principles and apply these to one’s own work, as a

member and leader in a team, to manage projects and in multidisciplinary

environments. PO12: Life-long learning: Recognize the need for, and have the preparation and ability to

engage in independent and life-long learning in the broadest context of technological

change.

PROGRAMME SPECIFIC OUTCOMES (PSOs):

PSO1: Communications: Design and develop modern communication technologies for

building inter disciplinary skills to meet current and future needs of industry. PSO2: VLSI & Embedded Systems: Design and Analyze Analog and Digital Electronic

Circuits or systems and Implement real time applications in the field of VLSI and

Embedded Systems using relevant tools. PSO3: Signal Processing: Apply the Signal processing techniques to synthesize and realize

the issues related to real time applications.

Dr. P. Lachi Reddy Dr. P. Lachi Reddy Dr. P. Lachi Reddy Dr. Y. Amar Babu

Course Instructor Course Coordinator Module Coordinator HOD




COURSE HANDOUT

PROGRAM : M.Tech., I-Sem., ECE


COURSE NAME & CODE : CPLD and FPGA Architectures and

Applications & 17VE03


COURSE CREDITS : 3

COURSE INSTRUCTOR : G.Venkat Rao

COURSE COORDINATOR : G.Venkat Rao

COURSE OBJECTIVE: In this course student will learn about the complex

programmable logic devices, field programmable gate arrays, architecture of

SRAM programmable and anti-fuse programmed FPGAs.



PSO

1 PSO

2 PSO

3 PSO

4 PSO

5

1 Analyze different types of Complex Programmable Logic Devices.

1 2 3 - 3

2 Understand different types of Field Programmable Gate Arrays. 2 2 3 3 3

3 Evaluate architecture of SRAM Programmable FPGAs. - - 3 3 3

4 Explain the device Architecture of Anti-Fuse Programmed FPGAs. - - 3 3 3

5 Design the application for Combinational and Sequential Circuits. - 2 3 - 3




1 Stephen M. Trimberger, “Field Programmable Gate Array Technology” Springer International Edition.

2 Charles H. Roth Jr, LizyKurian John, “Digital Systems Design”, Cengage Learning.


1 John V. Oldfield, Richard C. Dorf, “Field Programmable Gate Arrays”, Wiley India.

2 Pak K. Chan/SamihaMourad, “Digital Design Using Field Programmable Gate Arrays”

Pearson Low Price Edition.

COURSE DELIVERY PLAN (LESSON PLAN): UNIT-I : Introduction To Programmable Logic Devices.


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

55. Introduction to programmable logic devices

1 13/8/2018

TLM1

56. Simple programmable logic devices

1 14/8/2018

TLM1

57. Simple programmable logic devices

1 16/8/2018

TLM2

58. Read only Memories

1 17/8/2018

TLM2

59. Programmable logic arrays

1 20/8/2018

TLM1

60. Programmable logic arrays

1 21/8/2018

TLM1

61. Programmable array logic

1 23/8/2018

TLM1

62. Programmable array logic

1 24/8/2018

TLM1

63. Comparison of PLDs

1 27/8/2018

TLM2

64. Programmable logic devices

1 28/8/2018

TLM1

65. Generic Array logic

1 30/8/2018

TLM2

66. Sequential Programmable logic devices

1 31/8/2018

TLM1

67. Sequential Programmable logic devices

1 04/9/2018

TLM1

68. Complex Programmable logic devices

1 06/9/2018

TLM1

69. Complex Programmable logic devices

1 07/9/2018

TLM1

70. Architecture of Xilinx Cool runner

1 10/9/2018

TLM1

71. XCR3064XL CPLD

1 11/9/2018

TLM1

72. Implementation of a parallel adder with

Accumulation 1

14/9/2018

TLM1

73. Assignment/Quiz – 1

1 17/9/2018

TLM6

No. of classes required to complete UNIT-I 19 No. of classes taken:

UNIT-II: Field Programmable Gate Arrays


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

74. Organization of FPGAs

1 18/9/2018

TLM1

75. FPGA Programming Technologies

1 20/9/2018

TLM1

76. Programmable Logic Block Architectures

1 24/9/2018

TLM1

77. Programmable Logic Block Architectures

1 25/9/2018

TLM2

78. Programmable Inter connects

1 27/9/2018

TLM1

79. Programmable I/O blocks in FPGAs

1 28/9/2018

TLM2

80. Dedicated Specialized Components of

FPGAs 1

1/10/2018 TLM2

81. Applications of FPGAs

1 4/10/2018

TLM1

82. Assignment/Quiz – 2

1 5/10/2018

TLM6

No. of classes required to complete UNIT-II 9 No. of classes taken:

UNIT-III: SRAM Programmable FPGAs


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

83. SRAM Programmable FPGAs 1 15/10/2018 TLM1

84. Introduction 1 16/10/2018

TLM2

85. Programming Technology 1 19/10/2018

TLM1

86. Device Architecture 1 22/10/2018

TLM2

87. Advantages of SRAM FPGAs 1 23/10/2018

TLM2

88. Disadvantages of SRAM FPGAs 1 25/10/2018

TLM2

89. Configurable logic block :LUT 1 26/10/2018

TLM1

90. Programmable Interconnect Point, MUX 1 29/10/2018

TLM1

91. The Xilinx XC2000 Architecture 1 30/10/2018

TLM1

92. The XC2000 CLB 1 1/11/2018

TLM2

93. The XC2000 IOB,Wiring Architecture 1 2/11/2018

TLM1

94. The XC3000 CLB Architecture 1 5/11/2018

TLM1


TLM1

96. The Xilinx XC4000 Architecture 1 8/11/2018

TLM1

97. The XC4000 CLB Architecture 1 9/11/2018

TLM1


TLM1

99. ASSIGNMENT-III 1 13/11/2018

TLM6

No. of classes required to complete UNIT-III 17 No. of classes taken:

UNIT-IV : Anti-Fuse Programmed FPGAs


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

100. Introduction 1 15/11/2018

TLM1

101. Programming Technology

1 16/11/2018

TLM2

102. Device Architecture

1 19/11/2018

TLM1

103. Major elements of the Actel FPGA

1 20/11/2018

TLM1

104. Logic Module, Simple Logic Module

1 22/11/2018 TLM1

105. Combinatorial logic module

1 23/11/2018 TLM1

106. The Actel1 Architecture

1 26/11/2018 TLM1


1 27/11/2018 TLM1


1 29/11/2018

TLM1

109. ASSIGNMENT TEST

1 30/11/2018

TLM6

No. of classes required to complete UNIT-IV 10 No. of classes taken:

UNIT-V : Design Applications


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

110. General Design issues 1 3/12/2018

TLM1

111. Counter Examples

1 4/12/2018

TLM2

112. A Fast Video Controller

1 6/12/2018

TLM1

113. A Fast DMA controller

1 7/12/2018

TLM1

114. Designing Counters with ACT devices 1 10/12/2018

TLM2

115. Designing Adders and Accumulators with the ACT Architecture

1 11/12/2018

TLM1

116. ASSIGNMENT TEST

1 13/12/2018

TLM6

No. of classes required to complete UNIT-V 7 No. of classes taken:



No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

117. Voice and Gesture Controlled

Robot Using Android Applications 1

14/12/2018 TLM2





ACADEMIC CALENDAR:









EVALUATION PROCESS:


MID – I 1, 2 40

MID – II 3, 4, 5 40




G.Venkat Rao G.Venkat Rao Dr.P.Lachi Reddy Dr.Y.Amar Babu





COURSE HANDOUT

PROGRAM : M.Tech., I-Sem., ECE-VLSI&ES


COURSE NAME & CODE : Embedded System Design – 17VE02


COURSE CREDITS : 3

COURSE INSTRUCTOR : Dr. Y.Amar Babu, Professor

COURSE COORDINATOR : Dr. Y.Amar Babu, Professor

COURSE OBJECTIVE: This course provides the knowledge on typical

embedded system components, characteristics and quality attributes of

embedded systems, embedded hardware design and development, ARM architecture, IC Technology and Design technology to implement embedded

system. COURSE ARTICULATION MATRIX(Correlation between COs&POs,PSOs):


PSO

1

PSO

2 PSO

3 PSO

4 PSO

5

1 Choose different design methodologies to implement given specifications

3 2 1

2 Design control unit and Data path unit for given Embedded System 1 2 3

3 Use ARM processor architecture for development of Embedded

System 1 3 3 3

4 Develop interface between ARM processor core, memory and co-

processor 3 3

5 Build frame work for embedded system using IC & design technology

3 3 3




1 “Embedded System Design A unified Hardware/Software Introduction” Frank Vahid/

Tony Givargis, John Wiley & Sons Ptd.


1 Joseph Yiu, “The Definitive Guide to the ARM Cortex-M3”, Newnes, Elsevier, 2008.

2 James K Peckol, “Embedded Systems- A Contemporary Design Tool”, John Weily, 2008

COURSE DELIVERY PLAN (LESSON PLAN): UNIT-I : Embedded System Introduction


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

118. Embedded systems overview 1 13-08-2018

To 18-08-2018 13-08-2018

To 18-08-2018 TLM1, 2

119. Design challenge 1 20-08-2018

TLM1, 2

120. Processor technology 1 21-08-2018 TLM1, 2

121. IC technology 1 24-08-2018 TLM1, 2

122. Design Technology 1 27-08-2018 TLM1, 2

123. Trade-offs 1 28-08-2018 TLM1, 2

124. Single purpose processors 1 29-08-2018 TLM1, 2

125. RT-level combinational logic 1 31-08-2018 TLM1, 2

126. Sequential logic (RT level) 1 04-09-2018 TLM1, 2

127. Custom single purpose processor design (RT-level)

1 05-09-2018 TLM1, 2

128. Optimizing custom single purpose

processors 1 07-09-2018 TLM1, 2

129. Assignment/Tutorials-I 1 10-09-2018

No. of classes required to complete UNIT-I 12 No. of classes taken:

UNIT-II : Sate Machine and Concurrent Process Models


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

130. State Machine and Concurrent Process Models

1 11-9-2018 TLM1, 2

131. models Vs languages 1 12-9-2018 TLM1, 2

132. finite state machines with data path model (FSMD)

1 14-9-2018 TLM1, 2

133. using state machines 1 17-9-2018 TLM1, 2

134. program state machine model (PSM) 1 18-9-2018 TLM1, 2

135. concurrent process model , concurrent processes

1 19-9-2018 TLM1, 2

136. communication among processes 1 24-9-2018 TLM1, 2

137. synchronization among processes 1 25-9-2018 TLM1, 2

138. Implementation 1 26-9-2018 TLM1, 2

139. Data flow model 1 28-9-2018 TLM1, 2

140. real-time systems

1 1-10-2018 TLM1, 2

141. Assignment/Tutorials-II

1 3-10-2018

No. of classes required to complete UNIT-II 12 No. of classes taken:

UNIT-III : ARM Processor Architecture


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

142. ARM programmer's model 1 5-10-2018 TLM1, 2

143. ARM programmer's model 1 15-10-2018 TLM1, 2

144. ARM development tools 1 16-10-2018 TLM1, 2


Programming 1 19-10-2018

TLM1, 2

146. Data processing instructions 1 22-10-2018 TLM1, 2

147. Data processing instructions 1 23-10-2018 TLM1, 2

148. Data transfer instructions 1 24-10-2018 TLM1, 2

149. Data transfer instructions 1 26-10-2018 TLM1, 2

150. Control flow instructions 1 29-10-2018 TLM1, 2

151. Control flow instructions 1 30-10-2018 TLM1, 2

152. writing simple assembly language

programs 1 31-10-2018

TLM1, 2

153. Assignment/Tutorials-III 1 2-11-2018

No. of classes required to complete UNIT-III 12 No. of classes taken:

UNIT-IV : ARM Organization and Implementation


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

154. Introduction 1 5-11-2018 TLM1, 2

155. 3-stage pipeline ARM

organization 1 6-11-2018

TLM1, 2

156. 5-stage pipeline ARM

organization 1 9-11-2018

TLM1, 2

157. ARM instruction execution 1 12-11-2018 TLM1, 2

158. ARM implementation 1 13-11-2018 TLM1, 2

159. ARM coprocessor interface 1 14-11-2018 TLM1, 2

160. ARM memory interface 1 16--11-2018 TLM1, 2

161. ARM Instruction Set 1 19-11-2018 TLM1, 2

162. Thumb Instruction Set 1 20-11-2018 TLM1, 2

163. ARM Processor Core ARM7TDMI 1 23-11-2018 TLM1, 2

164. ARM Processor Core ARM7TDMI 1 26-11-2018 TLM1, 2

165. Assignment/Tutorials-IV 1 27-11-2018

TLM1, 2

No. of classes required to complete UNIT-IV 12 No. of classes taken:

UNIT-V : IC and Design Technology


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

166. Full custom IC Technology 1 28-11-2018 TLM1, 2

167. Semi custom IC Technology 1 30-11-2018 TLM1, 2

168. PLD IC Technology 1 3-12-2018 TLM1, 2

169. Design Technology 1 4-12-2018 TLM1, 2

170. Synthesis 1 5-12-2018 TLM1, 2

171. Logic Synthesis 1 5-12-2018 TLM1, 2

172. RT Synthesis 1 7-12-2018 TLM1, 2

173. Behavioral Synthesis 1 10-12-2018 TLM1, 2

174. Verification 1 11-12-2018 TLM1, 2

175. Reuse 1 12-12-2018 TLM1, 2

176. Design process models 1 14--12-2018 TLM1, 2

177. Assignment/Tutorials-V 1 14--12-2018 TLM1, 2

No. of classes required to complete UNIT-V 12 No. of classes taken:



No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

178. TinyOS 1 14--12-2018 TLM1, 2

179. Android OS 1 14--12-2018

TLM1, 2





ACADEMIC CALENDAR:









EVALUATION PROCESS:


MID – I 1, 2 40

MID – II 3, 4, 5 40




Dr. Y. Amar Babu Dr. Y. Amar Babu Dr. P. Lachi Reddy Dr. Y. Amar Babu

Course Instructor Course Coordinator Module Coordinator BOS

Chairman&HOD




COURSE HANDOUT

PROGRAM : M. Tech., I-Sem., ECE (VLSI & Embedded Systems)


COURSE NAME & CODE : Image and Video Processing


COURSE CREDITS : 3

COURSE INSTRUCTOR : B.Rajeswari , Sr.Asst.Professor

COURSE COORDINATOR : B.Rajeswari , Sr.Asst.Professor

COURSE OBJECTIVE: In this course student will learn about various compression, enhancement and segmentation techniques, image

transformation techniques, and algorithms for 2D video signals.

COURSE ARTICULATION MATRIX(Correlation between COs&POs,PSOs):

CO Statement

At the end of the course,

student will be able to

PO

1

PO

2 PO

3 PO

4 PO

5 PO

6 PO

7 PO

8 PO

9 PO

10 PO

11 PO

12 PSO

1 PSO

2 PSO

3

1 Examine different image transformation techniques.

3 - - - - - - - - - - - - - 3

2 Evaluate various image enhancement and segmentation techniques.

3 - - - - - - - - - - - - - 3

3 Analyze different compression techniques for images.

3 - - - - - - - - - - - - - 3

4 Infer time-varying image formation models in video.

3 - - - - - - - - - - - - - 3

5 Compare 2-D motion estimation algorithms for video signals.

3 - - - - - - - - - - - - - 3


1- Slight(Low), 2 - Moderate(Medium), 3 - Substantial (High). BOS APPROVED TEXT BOOKS:

1. Digital Image Processing – Gonzaleze and Woods, 3rd ed., Pearson.

2. Video processing and communication – Yao Wang, JoemOstermann and

Ya–quin Zhang. 1st Ed., PH Int. References :

Digital Video Processing – M. Tekalp, Prentice Hall International

COURSE DELIVERY PLAN (LESSON PLAN):

UNIT-I : Fundamentals of Image Processing and Image Transforms:

S.No. Topics to be covered No. of

Classes Required

Tentative Date of

Completion

Actual Date of

Completion


HOD Sign

Weekly

180. Introduction to Image

processing 1 20.08.18 TLM1 TLM2

181.

Fundamentals of image

processing system,

Applications of Digital

image processing.

1

23.08.18

TLM1

TLM2

182. Basic steps of Image

Processing system. 1

24.08.18

TLM1

TLM2

183. Sampling and

Quantization of an image 1

27.08.18

TLM1

TLM2

184. Basic Relationship

between pixels 2

29.08.18

TLM1

TLM2

185. Introduction to image

transforms 1

30.08.18

TLM1

TLM2

186.

Fourier transform, 2 D

Discrete Fourier

transform 1

31.08.18

TLM1

TLM2

TLM4

187.

Discrete Cosine

Transform 1

05.09.18

TLM1

TLM2

TLM4

188.

Wavelet Transform

introduction, Continuous

and Discrete Wavelet

transform

2

06.09.18

07.09.18

TLM1

TLM2


11 No. of classes taken:

UNIT-II : Image Processing Techniques : Image Enhancement, Image Segmentation


Classes Required

Tentative Date of

Completion

Actual Date of

Completion


HOD Sign

Weekly


processing Techniques 1

10.09.18

TLM1

TLM2

190. Basic Intensity 1 12.09.18

TLM1

transformation function TLM2

191.

Introduction to image

enhancement,

Enhancement in spatial

domain

1

14.09.18

TLM1

TLM2

192.

Introduction to

Histogram processing,

Histogram manipulation 1

17.09.18

TLM1

TLM2

193. Fundamentals of spatial

filtering 1

19.09.18

TLM1

TLM2

194. Spatial filtering methods

1 20.09.18

TLM1

TLM2

195.

Smoothing Spatial filters,

Smoothing Spatial

filtering Techniques 1

24.09.18

TLM1

TLM2

196.

Sharpening Spatial filters

,Sharpening Spatial filter

techniques 1

26.09.18

TLM1

TLM2

197.

Introduction and Basics

of filtering in frequency

domain 1

27.09.18

TLM1

TLM2

198.

Image Smoothing

techniques, Smoothing

Spatial filters 1

28.09.18

TLM1

TLM2

199.

Sharpening Spatial

filters, Image Sharpening

techniques 1

01.10.18

TLM1

TLM2

200.

Selective filtering, Image

Segmentation- Line,

point detection 1

03.10.18

TLM1

TLM2

201. Thresholding, edge

detection, 1

04.10.18

TLM1

TLM2

202. Region Based

segmentation 1

05.10.18



UNIT-III : Image Compression


Classes Required

Tentative Date of

Completion

Actual Date of

Completion


HOD Sign

Weekly


compression 1

15.10.18

TLM1

TLM2

204. Image Compression

Fundamentals 1

19.10.18

TLM1

TLM2

205.

About Coding

Redundancy, Spatial and

Temporal redundancy 1

22.10.18

TLM1

TLM2

206. Introduction to

compression models 1

24.10.18

TLM1

TLM2

207.

Lossy and Lossless

compression,

Introduction to Huffman

coding

1

25.10.18

TLM1

TLM2

208.

Huffman Coding,

Introduction to

Arithmetic coding 1

26.10.18

TLM1

TLM2

209. Arithmetic coding, LZW

Coding 1

29.10.18

TLM1

TLM2

TLM4

210.

Run length coding,

Biplane coding, JPEG

Standards 1

31.10.18

TLM1

TLM2

TLM4

211.

Introduction to

Transform coding,

Wavelet coding 1

01.11.18

TLM1

TLM2

TLM4

212. Predictive coding,

1

02.11.18

TLM1

TLM2

TLM4



UNIT-IV : Basic steps of Video Processing


Classes Required

Tentative Date of

Completion

Actual Date of

Completion


HOD Sign

Weekly

213. Introduction to Video

and its Processing 1

05.11.18

TLM1

TLM2

214. Basics steps of video

Processing 1

08.11.18

TLM1

TLM2

215. Analog video , Digital

video 1

09.11.18

TLM1

TLM2

216.

Introduction to Image

formation and its

models 1

12.11.18

TLM1

TLM2

217. 3-D Motion models

1 14.11.18

TLM1

TLM2

218. Geometric image

formation 1

15.11.18

TLM1

TLM2

219. Photometric Image

formation 1

16.11.18

TLM1

TLM2

220.

Sampling of analog and

digital Video signals,

Filtering Operations. 2

19.11.18

22.11.18

TLM1

TLM2



UNIT-V : 2-D Motion Estimation


Classes Required

Tentative Date of

Completion

Actual Date of

Completion


HOD Sign

Weekly

221. Optical flow, General

methodologies 1

23.11.18

TLM1

TLM2

222. Pixel based motion

estimation 2

26.11.18

28.11.18

TLM1

TLM2

223.

Block Matching

algorithm, Deformable

block matching

algorithms

2

29.11.18

30.11.18

TLM1

TLM2

224.

Mesh based Motion

estimation, Global

motion estimation 1 03.12.18

TLM1

TLM2

225.

Region based Motion

estimation, Multi

Resolution motion

1

05.12.18

06.12.18

TLM1

TLM2

estimation

226. Waveform based coding

1 07.12.18

TLM1

TLM2

227.

Block based transform

coding, Predictive

coding 1

10.12.18

12.12.18

TLM1

TLM2

228.

Applications of motion

estimation in video

coding. 1

13.12.18

TLM1

TLM2

No. of classes required to complete UNIT-V




Classes Required

Tentative Date of

Completion

Actual Date of

Completion


HOD Sign

Weekly

229. Kronecker product 1 14.12.18 TLM1

TLM2





ACADEMIC CALENDAR:


Orientation Programme 13/08/2018 18/08/2018 1W

I Phase of Instructions-1 20.08.2018 06.10.2018 7W

I Mid Examinations 08.10.2018 13.10.2018 1W

II Phase of Instructions 15.10.2018 15.12.2018 9W

II Mid Examinations 17.12.2018 22.12.2018 1W

Preparation and Practicals 24.12.2018 29.12.2018 1W

Semester End Examinations 31.12.2018 12.01.2019 2W

EVALUATION PROCESS:


Assignment/Quiz – 1 1 A1=5


I-Mid Examination 1,2 B1=20




II-Mid Examination 3,4,5 B2=20

Evaluation of Assignment/Quiz Marks: A=(A1+A2+A3+A4+A5)/5 1,2,3,4,5 A=5

Evaluation of Mid Marks: B=75% of Max(B1,B2)+25% of Min(B1,B2) 1,2,3,4,5 B=20

Cumulative Internal Examination : A+B 1,2,3,4,5 A+B=25

Semester End Examinations 1,2,3,4,5 C=75

Total Marks: A+B+C 1,2,3,4,5 100

B.Rajeswari B.Rajeswari Dr.M.Madhavi Dr.Y.Amar Babu


LAKIREDDY BALI REDDY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

(Autonomous & Affiliated to JNTUK, Kakinada & Approved by AICTE, New Delhi) (Certified by ISO 9001:2015)


COURSE HANDOUT

Part-A

Program : M.Tech., I-Sem., ECE Academic Year : 2018-19

Course Name & Code : SYSTEM MODELING AND SIMULATION-17VE08

Structure : 3-1-0 Course Credits : 3 Course Instructor : Mr. T.ANIL RAJU Course Coordinator : Mr. T.ANIL RAJU Pre-requisites: Signal Processing Basics, Random Process COURSE EDUCATIONAL OBJECTIVES (CEOs): This course provides the knowledge on to actually various simulation and programming Models, Optimization methodologies. COURSE OUTCOMES (COs) After completion of the course, the student will be able to CO1: Understand basic simulation models, characterizing and simulation diagrams. CO2: Model time driven systems and stochastic processes. CO3: Know how to simulate any discrete systems using queuing systems. CO4: Discuss system optimization, modeling and simulated methodology. CO5: Build simulation models with programming languages. COURSE ARTICULATION MATRIX (Correlation between Cos &POs ,PSOs):

COs PSO1 PSO2 PSO3 PSO4 PSO5

CO1 1 2

CO2 1 2

CO3 2 2 3

CO4 2 2 2 3

CO5 3 2 3

Note: Enter Correlation Levels 1 or 2 or 3. If there is no correlation, put ‘-’ 1- Slight (Low), 2 – Moderate (Medium), 3 - Substantial (High).


T1 Frank L. Severance, “System Modeling and Simulation” An Introduction, John Wiley&

Sons.2001.


R1: Averill M.Law, W.Davidkelton,” Simulation Modeling and Analysis-3ed TMH

R2: Geoffery Gordan,”Systems Simulation” PHI.

Part-B COURSE DELIVERY PLAN (LESSON PLAN):

UNIT-I : Simulation & Modeling, Systems


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

Learning

Outcome

COs

Text Book

followed

HOD

Sign

Weekly

230. Basic Simulation Modeling, Systems

1 13-08-2018 CO1 T1

231. Models and Simulation

1 14-08-2018 CO1 T1

232. Nature of Systems 1 17-08-2018 CO1 T1

233. Event Driven Models

1 20-08-2018 CO1 T1

234.

Simulation of single server Queuing systems

1 21-08-2018 CO1 T1,R1

235. Characterizing Systems

1 24-08-2018 CO1 T1

236. Simulation Diagrams

1 27-08-2018 CO1 T1



UNIT-II : Stochastic generators


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

Learning

Outcome

COs

Text Book

followed

HOD

Sign

Weekly

237. Stochastic generators 1 27-08-2018

CO2 T1, R2

238. Uniformly Distributed Random Numbers,

1 28-08-2018

CO2 T1

239. Statistical Properties of U[O, l] generators

1 29-08-2018

CO2 T1

240. Generation of Non-Uniform

1 31-07-2018

CO2 T1

241. Arbitrary Random Variables

1 04-09-2018

CO2 T1

242. Random processes 1 05-09-2018

CO2 T1, R2

243.

Characterizing and Generating Random Processes

1 07-09-2018

CO2 T1,R1,R2

244. White Noise 1 10-09-2018

CO2 T1,R1,R2

245. Modeling Time Driven Systems

1 11-09-2018

CO2 T1, R2

246. Modeling Input Signals 1 12-09-2018

CO2 T1,R1,R2

247. Discrete and Distributed Delays

1 14-09-2018

CO2 T1,R2

248. System Integration 1 17-09-2018

CO2 T1

249. Exogenous Signals and Events

1 18-09-2018

CO2 T1,R1,R2

250. Disturbance Signals 1 19-09-2018

CO2 T1,R2

251. State Machines 1 24-09-2018

CO2 T1

252. Petri Nets 1 25-09-2018

CO2 T1,R1,R2

253. Petri Nets Analysis 1 26-09-2018

254. System Encapsulation. 1 28-09-2018



UNIT-III : Markov Process


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teachi

ng

Learnin

g

Method

s

Learning

Outcome

COs

Text Book

followed HOD

Sign

Weekl

y

255. Markov Process 1 01-10-2018

CO3 T1,R1,R2

256. Probabilistic Models 1 03-10-2018

CO3 T1

257. Discrete Time Markov Processes

1 05-10-2018

CO3 T1

258. Random Walks 1 15-10-2018 CO3 T1

259. Poisson Processes 1 16-10-2018

CO3 T1

260. Exponential Distribution

1 19-10-2018 CO3 T1,R2

261. Simulating a Poisson Process

1 22-10-2018

CO3 T1,R1,R2

262. Continuous Time Markov Process Event

1 23-10-2018

CO3 T1

263. Driven Models Simulation Diagrams

1 24-10-2018

CO3 T1

264. Queuing Theory 1 26-10-2018

CO3 T1

265.

M/M/I Queues, Simulating Queuing Systems

1 29-10-2018

CO3 T1, R2

266. Finite Capacity Queues 1 30-10-2018

CO3 T1

267. Multiple Servers 1 31-10-2018

CO3 T1, R2

268. M/M/C Queues 1 01-11-2018

CO3 T1,R1,R2



UNIT-IV: System Optimization


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

Learning

Outcome

COs

Text Book

followed

HOD

Sign

Weekly

269. System Optimization 1

05-11-2018

CO4 T1, R2

270. System Identification 1 06-11-2018

CO4 T1, R2

271. Searches 1 09-11-2018

CO4 T1, R2

272. Examples 1 12-11-2018

CO4 T1,R2

273. Alpha trackers 1 13-11-2018

CO4 T1,R2

274. Beta trackers 1 14-11-2018

CO4 T1, R2

275. Multidimensional Optimization

1 16-11-2018

CO4 T1, R2

276. Modeling Methodology 1 19-11-2018

CO4 T1

277. Simulation Methodology

1 20-11-2018

CO4 T1, R2



UNIT-V : Simulation Software and Building Simulation Models


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

Learning

Outcome

COs

Text

Book

followed

HOD

Sign

Weekly

278.

Simulation Software and Building Simulation Models Guide

1

23-11-2018

CO5 T1,R2

279.

Comparison of Simulation Packages with Programming Languages

1

26-11-2018

CO5 T1,R2

280. Classification of simulation software

1 27-11-2018

CO5 T1,R2

281. Desirable software features

1 28-11-2018

CO5 T1,R2

282.

Extend :Guide lines for determining the level of model

1 30-11-2018

CO5 T1,R2

283.

General Purpose Simulation Packages-Arena

1 03-12-2018

CO5 T1,R2

284.

Extend: Guide lines for determining the level of Model detail

1 04-12-2018

CO5 T1,R2

285.

Techniques for increasing Model Viability

1 05-12-2018

CO5 T1,R2

286.

General Purpose Simulation Packages-Arena

1 07-12-2018

CO5 T1,R2

287.

Techniques for increasing Model Credibility

1 10-12-2018

CO5 T1,R2

No. of classes required to complete UNIT-V




No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

Learning

Outcome

COs

Text

Book

followed

HOD

Sign

Weekly

288. Application simulation model

1 11-12-2018

T1,R2

289. Soft computation models

1 12-12-2018

T1,R2

290. Evolutionary computation models

1 14-12-2018

T1,R2


TLM1 Chalk and Talk TLM4 Demonstration (Lab/Field Visit)

TLM2 PPT TLM5 ICT (NPTEL/Swayam Prabha/MOOCS)

TLM3 Tutorial TLM6 Group Discussion/Project

EVALUATION PROCESS: Part - C




I-Mid Examination 1,2 B1=20




II-Mid Examination 3,4,5 B2=20

Evaluation of Assignment/Quiz Marks: A=(A1+A2+A3+A4+A5)/5 1,2,3,4,5 A=5

Evaluation of Mid Marks: B=75% of Max(B1,B2)+25% of Min(B1,B2) 1,2,3,4,5 B=20

Cumulative Internal Examination : A+B 1,2,3,4,5 A+B=25

Semester End Examinations 1,2,3,4,5 C=75

Total Marks: A+B+C 1,2,3,4,5 100

T.Anil Raju T.Anil Raju

Course Instructor Course Coordinator

Module Coordinator

HOD




COURSE HANDOUT

PROGRAM : M.Tech, I-Sem., ECE


COURSE NAME & CODE : Technical Seminar


COURSE CREDITS : 1

COURSE INSTRUCTOR : Mr.G.Venkat Rao /Mr.T.Anil Raju

COURSE COORDINATOR : Mr.T.Anil Raju

COURSE OBJECTIVE:


CO

Statement

At the end of the course, student will be

able to

PSO1 PSO2 PSO3 PSO4 PSO5

1 Survey on latest developments in core

technical domain.

1 2

2

Develop audience centric presentation.

2 2 1

3

Adapt effective report writing skills.

3 2 1

Note: Enter Correlation Levels 1 or 2 or 3. If there is no correlation, put ‘-’ 1- Slight(Low), 2 - Moderate(Medium), 3 - Substantial (High).


1 Micheal alley, “craft of scintific writing” Springer International Edition.

2

TECHNICAL SEMINAR SCHEDULE (LESSON PLAN)


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

CYCLE-1

2. Introduction

2 29/8/2018

TLM7

16. Literature Survey 2

05/9/2018

TLM7

17. Literature Survey 2 12/9/2018

TLM7

18. Presentation1 2 19/9/2018

TLM7

19. Presentation1 2 26/9/2018

TLM7

20. Presentation1 2 03/10/2018 TLM7




24. Seminar Report 2 28/11/2018 TLM7

25. Quality of work 2 5/12/2018 TLM7

26. Interaction 2 12/12/2018 TLM7

No. of classes required to complete Seminars No. of classes conducted:





ACADEMIC CALENDAR:









EVALUATION PROCESS:


Survey 1 A=10

Quality of work 2 B=20

Presentation 2 C=30

Seminar Report 3 D=20

Interaction 2 E=20

Total Marks: A+B+C+D+E 1,2,3 100

G.Venkat Rao T.Anil Raju Dr.P.Lachi Reddy Dr.Y.Amar Babu



Autonomous & Affiliated to JNTUK, Kakinada & Approved by AICTE, New Delhi, L B Reddy Nagar, Mylavaram-521 230, Krishna District, Andhra Pradesh.

COURSE HANDOUT

PROGRAM : M.Tech. I-Sem., ECE

SPECILIZATION :VLSI & Embedded systems


COURSE NAME & CODE : Digital VLSI System Design Lab& 17VE60


COURSE CREDITS : 1

COURSE INSTRUCTOR : Mr.CH.Mallikharjuna Rao

COURSE COORDINATOR : Mr. K.Rani Rudramma

COURSE OBJECTIVE: In This Laboratory student will learn about Modeling

of CMOS logic circuits using Pyxis Schematic Editor, modeling of

combinational and sequential logic circuits using VHDL/Verilog and implementation of digital circuits using FPGA.


CO Statement



PO

1

PO

2 PO

3 PO

4 PO

5 PO

6 PO

7 PO

8 PO

9 PO

10 PO

11 PO

12 PSO

1 PSO

2 PSO

3

1 Design CMOS

Logic gates using

Pyxis Schematic Editor.

1 2 3 3 3

2 Model digital

modules using VHDL/Verilog

and Simulate.

1 2 3 3 3

3 Verify

Implementation of Digital Design

on FPGA Board.

1 2 3 3 3


1- Slight (Low), 2 – Moderate (Medium), 3 - Substantial (High).


1 JHON.F.Wakerly, “Digital Design Principles & Practices” III Edition, Prentice Hall Publishers.

DIGITAL VLSI SYSTEM DESIGN LAB SCHEDULE


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

CYCLE-1

3. Design of 8 input priority encoder

and 3 to 8 Decoder 2

21/08/2018

TLM5,8

27. Design of 8x1Mux and 1x8

Demux

2 28/08/2018 TLM5,8

28. Design of 4 bit adder 2 04/09/2018

TLM5,8

29. Design 4 bit Magnitude

Comparator

2 11/09/2018 TLM5,8

30. Design of BCD adder 2 18/09/2018

TLM5,8

31. Design of ALU 2 25/09/2018 TLM5,8

32. Design of D,T,JK Flip Flops 2 16/10/2018 TLM5,8

33. Design of Shift Registers 2 23/10/2018

TLM5,8

CYCLE-2

34. Design of Counters

2 30/10/2018

TLM5,8

35. Design of FSM( Moore’s, Mealy

Machines)

2 06/11/2018 TLM5,8

36. Design of CMOS Inverter 2 13/11/2018 TLM5,8

37. Design of CMOS NAND and

NOR gates.

2

20/11/2018

TLM5,8

38. Design of CMOS EX-OR and

MUX gates.

2

27/11/2018

TLM5,8

39. Design of CMOS one bit full

adder 2

04/12/2018 TLM5,8

40. Internal Lab Examination 2 11/12/2018

TLM5,8

No. of lab sessions required to complete syllabus

No. of lab sessions taken to complete syllabus





ACADEMIC CALENDAR:







Practical’s 24-12-2018 29-12-2018 1W


EVALUATION PROCESS:

Evaluation Task Marks

Day to Day work A=15

Record Writing B=5

Internal Lab Examination C=20

Cumulative Internal Examination : A+B+C A+B+C=40

Semester End Examinations D=60

Total Marks: A+B+C+D 100

CH.Mallikharjuna Rao K.Rani Rudramma Dr.P.Lachi Reddy Dr. Y.Amar Babu


LAKKIREDDY BALI REDDY COLLEGE OF ENGINEERING

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING (Autonomous & Affiliated to JNTUK, Kakinada & Approved by AICTE, New Delhi)


COURSE HANDOUT

PROGRAM : M.Tech., I-Sem.

SPECILIZATION :VLSI & Embedded systems


COURSE NAME & CODE : Digital VLSI system Design& 17VE01 L-T-P STRUCTURE : 4-0-0

COURSE CREDITS : 3

COURSE INSTRUCTOR : Mr. CH.Mallikharjuna Rao.

COURSE COORDINATOR : Mr. CH.Mallikharjuna Rao.

COURSE OBJECTIVE: This course gives the ability to analyze and design

digital system using Verilog HDL. To empower the students to understand the

design and analysis of combinational and sequential circuits and design of RISC

microprocessor.

COURSE ARTICULATION MATRIX(Correlation between COs&POs,PSOs):

CO Statement



PO

1

PO

2 PO

3 PO

4 PO

5 PO

6 PO

7 PO

8 PO

9 PO

10 PO

11 PO

12 PSO

1 PSO

2 PSO

3

1 Design

combinational and

sequential circuits

2 2 3 - 3 1 - - - - - - 1 3 1

2 Understand digital

system design flow

using verilog HDL.

1 2 2 2 3 - - - - - - - 1 3 1

3 Model digital

system using verilog

HDL.

2 2 2 2 3 - - - - - - - 1 3 1

4 Write verilog Tasks,

Functions, UDPs for

digital modules.

2 2 1 - 3 - - - - - - - 1 3 1




1. Digital Systems Design using VERILOG Charles H. Roth, Lizy kurian John

2. T.R.Padmanabhan and B. Bala Tripura Sundari, “ Design Through Verilog HDL”,

Wiley IEEE Press.


1. J.Bhaskar, A Verilog Primier, BSP publishers.

2. Douglas J.Smith, HDL Chip Design, Doorne Publications, USA.

.

COURSE DELIVERY PLAN (LESSON PLAN):

UNIT-I: REVIEW OF LOGIC DESIGN FUNDAMENTALS


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

291. MOS Devices and CMOS Logic 1 20/08/2018 TLM1

292. Combinational Logic 1 23/08/2018 TLM1

293. Boolean Algebra and Algebraic

Simplification 1

24/08/2018 TLM1

294. Karnaugh Maps 1 27/08/2018 TLM1

295. Designing with NAND and NOR

Gates 1

29/08/2018 TLM1

296. Hazards in Combinational Circuits 1 30/08/2018 TLM1

297. Flip-Flops and Latches 1 31/08/2018 TLM1

298. Mealy Sequential Circuit Design 1 05/09/2018 TLM1

299. Design of a Moore Sequential

Circuit 1

06/09/2018 TLM1

300. Equivalent States and Reduction of

State Tables 1

07/09/2018 TLM1

301. Sequential Circuit Timing 1 10/09/2018 TLM1

302. Tristate Logic and Busses 1 12/09/2018 TLM1

No. of classes required to complete UNIT-I 12 No. of classes taken to complete UNIT-I

UNIT-II: INTRODUCTION TO VERILOG


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

303. Computer-Aided Design. HDL 1 14/09/2018 TLM1

304. Verilog Description of

Combinational Circuits, Verilog

Modules

1

17/09/2018

TLM1

305. Verilog Assignments. Procedural

Assignments 1

19/09/2018 TLM1

306. Modeling Flip-Flops Using Always

Block 1

20/09/2018 TLM1

307. Always Blocks Using Event

Control Statements 1

24/09/2018 TLM1

308. Delays in Verilog 1 26/09/2018

TLM1

309. Compilation, Simulation, and 1 27/09/2018 TLM2

Synthesis of Verilog Code

310. Verilog Data Types and Operators,

Simple Synthesis Examples,

Verilog Models for Multiplexers

1

28/09/2018

TLM2

311. Modeling Registers and Counters

Using Verilog Always Statements 1

01/10/2018 TLM2

312. Behavioral and Structural Verilog 1 03/10/2018 TLM1

313. Constants, Arrays and Loops in

Verilog 1

04/10/2018 TLM2

314. Testing a Verilog Model, A Few

Things to Remember 1

05/10/2018 TLM1

No. of classes required to complete UNIT-II 12

No. of classes taken to complete UNIT-II

UNIT-III : DESIGN EXAMPLES


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

315. BCD to 7-Segment Display

Decoder, A BCD Adder 1

15/10/2018 TLM5

316. 32-Bit Adders 1 19/10/2018 TLM5

317. Traffic Light Controller 1 22/10/2018 TLM5

318. State Graphs for Control Circuits 1 24/10/2018

TLM5

319. Scoreboard and Controller 1 25/10/2018

TLM5

320. Synchronization and Debouncing, 1 26/10/2018 TLM5

321. A Shift-and-Add Multiplier 1 29/10/2018 TLM5

322. Array Multiplier 1 31/10/2018 TLM5

323. A Signed Integer/Fraction

Multiplier 1

01/11/2018 TLM5

324. Keypad Scanner 2 2/11/2018 &

05/11/2018

TLM5

325. Binary Dividers 2 08/11/2018 &

09/11/2018

TLM5

No. of classes required to complete UNIT-III 13 No. of classes taken to complete UNIT-III

UNIT-IV: SM CHARTS AND MIRCOPROGRAMMING.


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

326. State Machine Charts 1 12/11/2018 TLM2

327. Derivation of SM Charts 1 14/11/2018 TLM2

328. Realization of SM Charts 1 15/11/2018 TLM2

329. Implementation of the Dice Game 1 16/11/2018 TLM2

330. Microprogramming 1 19/11/2018 TLM2

331. Linked State Machines 1 22/11/2018

TLM2

No. of classes required to complete UNIT-IV 6 No. of classes taken to complete UNIT-IV

UNIT-V: ADDITIONAL TOPICS IN VERILOG & DESIGN OF A RISC

MICROPROCESSOR


No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

332. Verilog Functions. Verilog Tasks 1 23/11/2018

TLM1

333. Multi-Valued Logic and Signal

Resolution, Built-in Primitives 1

26/11/2018 TLM1

334. User Defined Primitives 1 28/11/2018 TLM1

335. SRAM Model, Model for SRAM

Read/Write System 1

29/11/2018 TLM2

336. Rise and Fall Delays of Gates,

Named Association 1

30/11/2018 TLM2

337. Generate Statements,

System Functions 1

3/12/2018 TLM1

338. Compiler Directives,

File I/O Functions. Timing Check 1

5/12/2018 TLM2

339. The RISC Philosophy 1 6/12/2018 TLM1

340. The MIPS ISA 1 7/12/2018

TLM2

341. MIPS Instruction Encoding 1 10/12/2018 TLM2

342. Implementation of a MIPS Subset 1 12/12/2018 TLM2

343. VHDL Model 1 13/12/2018 TLM2

No. of classes required to complete UNIT-V 12 No. of classes taken to complete UNIT-V



No. of

Classes

Required

Tentative

Date of

Completion

Actual

Date of

Completion

Teaching

Learning

Methods

HOD

Sign

Weekly

344. Introduction to system Verilog 1 14/12/2018 TLM2





EVALUATION PROCESS:

Evaluation Task Marks

Cumulative Internal Examination : 40

Semester End Examinations 60

Total Marks: 100

ACADEMIC CALENDAR:


Orientation classes 13-08-2018 18-08-2018 1w





Preparation and Practical’s 24-12-2018 29-12-2018 1W


CH.Mallikharjuna Rao CH.Mallikharjuna Rao Dr.P.Lachi Reddy Dr.Y.Amara Babu


COURSE HANDOUT - LBRCE

Documents

Transcript of COURSE HANDOUT - LBRCE