Conference Guide - FPL 2015

Conference Guide25th International Conference on Field-programmable Logic and Applications and associated Workshops and Tutorials

London, United Kingdom31 August – 4 September 2015

Conference Guide

24 years ago...

The 1st International Workshop on Field-programmable Logic and Applications4 – 6 September 1991Oxford, United Kingdom

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ContentsWelcome ................................................................................. 4General Information ................................................................ 6Venues.................................................................................... 8Social Programme .................................................................. 9Royal Institution Map.............................................................10Programme ........................................................................... 12Keynotes............................................................................... 20Programme Detail Monday 31 August 2015 .................................................. 28 Tuesday 1 September 2015 ............................................ 29 Wednesday 2 September 2015 ....................................... 30 Thursday 3 September 2015 ........................................... 36 Friday 4 September 2015 ................................................ 43Special Session .................................................................... 48Committees .......................................................................... 49City Map ............................................................................... 58Underground Map................................................................. 60About London ....................................................................... 62London Sights....................................................................... 64About Imperial College ......................................................... 72About the Royal Institution.....................................................74

Conference Guide

WelcomeOur warmest welcome to FPL 2015, celebrating 25 years of the International Conference on Field-programmable Logic and Applications!

The 25th FPL conference is hosted by Imperial College London from 2 to 4 September 2015 at the Royal Institution in London, where Michael Faraday conducted his famous experiments on electromagnetism. The FPL 2015 conference is accompanied by two-and-a-half days of tutorials and workshops taking place on 31 August, 1 and 4 September. In addition to three industrial workshops, there are four academic half- and full-day work-shops and four half-day tutorials.

Highlights of FPL 2015 include keynotes from acade-mia, funding agencies and industry. We are grateful to Professor Steve Furber (University of Manchester, UK), Dr Mike Hutton (Altera, US), Professor David Larivie-re (Columbia University, US), Dr Salil Raje (Xilinx, US) and Dr Panagiotis Tsarchopoulos (European Commission, BE) for accepting our invitations to be keynote speakers.

This year’s Technical Program Committee had 188 members organised into five tracks, with one track chair assigned to each. There were 303 abstract submissions and 240 submis-sions were received by the submission deadline, including 216 regular papers, 12 PhD Forum papers and 12 demos. The Technical Program Committee meeting was held at Imperial College London on 29 May 2015. The final outcome of the re-view process was that 48 submissions were accepted as full papers with oral presentation (22.2% full paper acceptance rate) and 41 submissions were accepted as poster papers (41.2% acceptance rate including full and poster papers). Fur-thermore, ten submissions were accepted for the PhD Forum and ten were accepted for the Demo Night session.

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To commemorate the quarter-century contribution of the FPL conference, the most significant papers from its first 25 years have been selected to represent those which have most stron-gly influenced theory and practice in the field. Selection was determined by an international Significant Papers Committee (SPC), chaired by Professor Philip Leong (University of Syd-ney, AU). In addition, a special session on the past 25 years and the next 25 years of FPL has been organised with distin-guished speakers.

We are grateful to our sponsors for their support. We express our sincere thanks to everyone involved with conference orga-nisation and the technical committees for their efforts in ma-king FPL 2015 a success. The Technical Program Committee members provided valuable assessments for paper selection and feedback to authors. The workshop and tutorial organisers came up with attractive topics and put together an interesting collection of satellite events. Last but not least, our thanks extend to all the authors who sent submissions to FPL 2015, whose research ideas have allowed us to put together an ex-citing programme.

The first 25 years of FPL have included many outstanding con-tributions to field-programmable logic and applications. With the support of the FPL community, we are confident that FPL will continue to flourish for the next 25 years and beyond.

Thank you for attending FPL 2015.

Peter Cheung and Wayne Luk (General Chairs)Cristina Silvano (Programme Chair)

Conference Guide

General InformationThis conference guide aims to give you all the information you should need during your attendance at FPL 2015. General in-formation on the conference can also be found on the confe-rence website, http://www.fpl2015.org.

Conference contact

Mrs Wiesia HsissenDepartment of Electrical and Electronic EngineeringImperial College LondonSW7 2BTPhone: +44 (0)207 594 6261E-mail: [email protected]

Wi-fi

For the duration of the conference and the associated work-shops/tutorials, free Wi-fi Internet access is provided.

At the Royal Institution, use the following wireless network:

SSID: RIGB-GuestKey: Cavendish

At Imperial College, either use Eduroam or:

1. Connect to the wireless network with SSID Imperial.2. Open a Web browser. You will see a log-in page.3. Open the Guest Registration link in a new tab.4. Enter the Unique ID conf35272 and click Proceed.5. Enter your details and click Proceed.6. Note down the Login Name and Password assigned to you.7. In the original tab, enter those credentials and click Login.

Proceedings

A link to download the proceedings was emailed to you before arrival. If you did not receive this or cannot find it, you can re-quest a new link at http://www.fpl2015.org/?page=proceedings.

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Transport

London boasts one of the most extensive and frequented pu-blic transport networks in the world. Underground (subway or tube), Overground (surface trains), light rail, trams, buses, coa-ches, river taxis and short-hire bicycles are integrated and ma-naged by Transport for London (TfL). National Rail (mainline train) services within London are also integrated.

Payment for TfL services is made by contactless (RFID) cards called Oyster cards. These can be obtained, in exchange for a £5.00 refundable deposit per card, from automated ticket machines at all TfL stations or staffed ticket windows at major stations (such as those at airports, train stations or important landmarks). Oyster cards can be ‘topped up’ with credit using cash, credit or debit cards at ticket machines or windows. Many convenience stores also service Oyster top-ups; those that do are externally marked with TfL branding. When buying new cards or topping up using ticket machines, remember to press the ‘print receipt’ button if you wish to receive a receipt; they are not printed automatically.

When starting a journey on Underground, Overground or light rail, ‘touch in’ using your Oyster card by holding it against a yel-low card reader. A single short beep will indicate that your card was read successfully, and the ticket gate (if present) will open. Two long beeps indicate a problem; usually lack of sufficient funds. Remember to touch in even if ticket gates are open or not present to be charged the correct fare. Repeat this process to ‘touch out’ at the end of your journey. Interchange between Underground, Overground and light rail lines at appropriate stations does not incur additional cost.

Oyster is based on a zonal fare system, with zones approxi-mately comprising concentric circles emanating from the cen-tre of the city. Due to this, fares for most services become high-er the further you travel. Fares are also different depending on the time you start your journey: those started between 06:30 and 09:30 or 16:00 and 19:00 on weekdays typically attract higher (peak) fares, while all others are off-peak.

Conference Guide

VenuesFPL 2015 is split across two venues: the Royal Institution, where talks will be delivered, and the Electrical Engineering building (number 16 on the campus map on page 9) of Imperial College London’s South Kensington campus, where tutorials and workshops will take place. The Royal Institution and Im-perial College are approximately two miles apart. Inter-venue travel is possible by direct Underground (Piccadilly line) or bus (routes 9 and 14) link as well as on foot or by bicycle.

Addresses

Imperial College LondonExhibition RoadSW7 2AZ

Royal InstitutionAlbermarle StreetW1S 4BS

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Social ProgrammeDemo Night and ReceptionRoyal Institution, 18:15 Wednesday 2 September 2015

A demo night and accompanying canapé reception will be held at the Royal Institution. There will be ten demos on display from academia and industry.

BanquetImperial College London, 18:15 Thursday 3 September 2015

The banquet will take place at Imperial College. We will be having the dinner in the the Queen’s Tower Rooms, located on the ground floor of the Sherfield Building (number 20 on the campus map, below). The papers that won this year’s best paper awards will also be announced at the event.

Conference Guide

Royal Institution Map

Conference Guide

ProgrammeMonday 31 August 2015Electrical Engineering, Imperial College London

Room 611 Room 1109 Room 507

08:30 – 09:00 Registration

09:00 – 10:30 Workshop

W1: ReC4P 2015

– First International

Workshop on Recon-

figurable Computing

for HPC and HPDA

Tutotial

T1: NetFPGA – Rapid

Prototyping of High-

bandwidth Devices in

Open Source

Industrial workshop

IW1: Xilinx System

Design with Zynq

10:30 – 11:00 Coffee break

Room 509

11:00 – 12:30 Workshop

W1: ReC4P 2015


Workshop on Recon-

figurable Computing

for HPC and HPDA

Tutotial

T1: NetFPGA – Rapid

Prototyping of High-

bandwidth Devices in

Open Source

Industrial workshop

IW1: Xilinx System

Design with Zynq

12:30 – 13:30 Lunch

Room 509

13:30 – 15:00 Tutorial

T2: Rapid Develop-

ment of Real-time

Applications with

National Instruments

LabVIEW

Industrial workshop

IW1: Xilinx System

Design with Zynq


Room 509

15:30 – 17:00 Tutorial

T2: Rapid Develop-

ment of Real-time

Applications with

National Instruments

LabVIEW

Industrial workshop

IW1: Xilinx System

Design with Zynq

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Tuesday 1 September 2015Electrical Engineering, Imperial College London

Room 611 Room 1109 Room 304 Room 507


09:00 – 10:30 Workshop

W3: FSP 2015

– Second

International

Workshop on

FPGAs for SW

Programmers

Tutotial

T3: Under-

neath the

FPGA Clothes

– Enhancing

Security

Industrial

workshop

IW2: Overview

of Altera‘s Cy-

clone V SoC

Devices and

Design Tools

Industrial

workshop

IW3: Xilinx SD-

SoC: Building

Software-defi-

ned Systems-

on-Chip


Room 509

11:00 – 12:30 Workshop

W3: FSP 2015

– Second

International

Workshop on

FPGAs for SW

Programmers

Tutotial

T3: Under-

neath the

FPGA Clothes

– Enhancing

Security

Industrial

workshop

IW2: Overview

of Altera‘s Cy-

clone V SoC

Devices and

Design Tools

Industrial

workshop

IW3: Xilinx SD-

SoC: Building

Software-defi-

ned Systems-

on-Chip

12:30 – 13:30 Lunch

Room 509

13:30 – 15:00 Workshop

W3: FSP 2015

– Second

International

Workshop on

FPGAs for SW

Programmers

Tutorial

T4: The LEAP

Run-time

System –

Rapid System

Integration of

HLS Kernels

Industrial

workshop

IW2: Overview

of Altera‘s Cy-

clone V SoC

Devices and

Design Tools

Industrial

workshop

IW3: Xilinx SD-

SoC: Building

Software-defi-

ned Systems-

on-Chip


Room 509

15:30 – 17:00 Workshop

W3: FSP 2015

– Second

International

Workshop on

FPGAs for SW

Programmers

Tutorial

T4: The LEAP

Run-time

System –

Rapid System

Integration of

HLS Kernels

Industrial

workshop

IW2: Overview

of Altera‘s Cy-

clone V SoC

Devices and

Design Tools

Industrial

workshop

IW3: Xilinx SD-

SoC: Building

Software-defi-

ned Systems-

on-Chip

Conference Guide

Wednesday 2 September 2015Royal Institution

Theatre Conversation Room Demo Room


08:45 – 09:00 Welcome session

Theatre

09:00 – 10:00 Keynote 1: Salil Raje (Xilinx, US)

Theatre

10:00 – 10:40 Coffee break & poster session: PhD Forum

Georgian Room

10:40 – 12:00 Technical session

Applications 1: Linear

Algebra and Control

Applications

Technical session

Architectures & Tech-

nology 1: Energy-ef-

ficient and Low-power

Architectures

Technical session

Design Methods &

Tools 1: Parallelism

and Logic Design

12:00 – 13:00 Lunch

Library & Georgian Room

13:00 – 14:00 Keynote 2: David Lariviere (Columbia University, US)

Theatre

14:00 – 15:00 Special session: FPL – The Past 25 Years and the Next 25 Years

Theatre

15:00 – 15:40 Coffee break & poster session: Applications

Georgian Room

15:40 – 17:00 Special session: FPL – The Past 25 Years and the Next 25 Years

Theatre

18:00 – 18:15 Introduction to significant papers: Philip Leong (University of Sydney, AU)

Library

18:15 – 20:00 Demo Night & reception

Library

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Thursday 3 September 2015Royal Institution (morning & afternoon)Electrical Engineering, Imperial College London (evening)



09:00 – 10:00 Keynote 3: Mike Hutton (Altera, US)

Theatre

10:00 – 10:40 Coffee break & poster session: Architectures & Technology

Georgian Room


Applications 2:

Computer Vision

and Numerical Appli-

cations

Technical session

Architectures &

Technology 2: Crypto-

graphy and Security

Architectures

Technical session

Design Methods &

Tools 2: Accelera-

tors and High-level

Synthesis

12:00 – 13:00 Lunch

Library & Georgian Room

13:00 – 14:00 Keynote 4: Panagiotis Tsarchopoulos (European Commission, BE)

Theatre


Applications 3:

Pattern-matching and

Search Applications

Technical session

Architectures &

Technology 3: Recon-

figurable Computing

and Architectures

Technical session

Design Methods &

Tools 3: Simulation

and Emulation

15:00 – 15:40 Coffee break & poster session: Design Methods & Tools

Georgian Room


Applications 4: High-

level Synthesis and

Optimisation

Technical session

Architectures & Tech-

nology 4: Architectu-

res and Synthesis

Technical session

Design Methods

& Tools 4: Hybrid

FPGA-based

Systems

Location change: Royal Institution → Imperial College London

18:15 – 21:00 Banquet & best paper awards

Queen‘s Tower Rooms

Conference Guide

Friday 4 September 2015Royal Institution (morning)Electrical Engineering, Imperial College London (afternoon)



09:00 – 10:00 Keynote 5: Steve Furber (University of Manchester, UK)

Theatre

10:00 – 10:40 Coffee break & poster session: Self-aware & Adaptive Systems

Georgian Room

10:40 – 12:15 Workshop

W4: RC4Masses –

Workshop on Recon-

figurable Computing

for the Masses,

Really?

Workshop

W5: WCS-IoT 2015


Workshop on Com-

ponents and Services

for IoT platforms

Technical session

Architectures &

Technology 5:

Memory Management

and Customised

Architectures

12:15 – 12:30 Closing session

Theatre

Location change: Royal Institution → Imperial College London

Room 408 Room 611

13:00 – 13:30 Lunch (for workshop attendees only)

Room 509

13:30 – 15:00 Workshop

W4: RC4Masses –

Workshop on Recon-

figurable Computing

for the Masses,

Really?

Workshop

W5: WCS-IoT 2015


Workshop on Com-


for IoT platforms


Room 509

15:30 – 17:00 Workshop

W4: RC4Masses –

Workshop on Recon-

figurable Computing

for the Masses,

Really?

Workshop

W5: WCS-IoT 2015


Workshop on Com-


for IoT platforms

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Conference Guide

KeynotesExtending the Power of FPGAs to Software DevelopersSalil Raje (Xilinx, US)Royal Institution Theatre, 09:00 Wednesday 2 September 2015

FPGAs have evolved from simple programmable logic arrays to complex SoCs with millions of programmable elements. As the FPGA device has evolved, so has the programming pa-radigm. The industry has made significant progress in raising the abstraction level of FPGA design by leveraging a large set of IP blocks, enabling abstract IP integration, and exploiting high-level synthesis technology that allows users to work at the algorithmic level. While these innovations have increased the productivity of FPGA designers, they have not unleashed the full potential of FPGAs to the software programmers of the world. If we are intent on expanding the reach of FPGAs, we need to drive towards fully software-programmable FPGAs that can be used for heterogeneous computing. The programming solution needs to have the same look and feel as standard IDEs and abstract away the complexities of the underlying hardware while exploiting the massive parallelism of FPGAs for hardware acceleration. Key to enabling the era of software programmability will be the concept of the programmable plat-form – an abstraction that will allow the FPGA to take on the persona of the application domain. The journey to embrace the software developer community has begun.

Salil Raje is Corporate Vice President of Software and IP Pro-ducts Development at Xilinx, where he has held a variety of roles in the development organisation since 2004. Prior to joi-ning Xilinx, he was the founder and CTO of Hier Design, an EDA startup focussed on hierarchical design methodology and design planning tools for the FPGA market. Prior to that, Salil was a director at Monterey Design Systems, an EDA startup working on place and route technology for standard-cell ASIC design. Salil began his career at IBM Research Center at York-town Heights, New York, working on high-level synthesis. He holds a BTech in Electrical Engineering from IIT, Madras and an MS and a PhD in Computer Science from Northwestern University.

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Applications of FPGAs to the Financial Trading IndustryDavid Lariviere (Columbia University, US)Royal Institution Theatre, 13:00 Wednesday 2 September 2015

Programmable logic is having a profound and increasingly dominant role in modern financial markets. This talk will pre-sent an overview of electronic trading systems, trends in the underlying technologies, and explore areas of opportunity for researchers and industry to become more involved.

Professor David Lariviere teaches at Columbia University in the City of New York as an adjunct professor in the Depart-ments of Computer Science and Electrical Engineering. His research focusses on the application of next-generation tech-nologies towards the intersection of electronic trading and ultra low-latency packet processing. In industry, Prof. Lariviere is a consulting expert in the electronic trading space, architecting systems responsible for safely and quickly processing packets worth trillions of dollars daily.

Conference Guide

Architectural Paths to Faster and More Robust FPGAsMike Hutton (Altera, US)Royal Institution Theatre, 09:00 Thursday 3 September 2015

For most of the 25 years of the FPL Conference, FPGA tech-nology has successfully ridden Moore’s Law to greater density, higher performance and lower power. We’re still getting den-sity and power benefits, but more performance is required by the end markets and spending more power to get there isn’t acceptable. On other fronts: the need for memory is growing but we don’t get more pins for DDR, and development effort and complexity is also increasing, making it harder to build a single device where everything just works first time and inside a reasonable budget. When you can’t count on only riding the process curve, architecture needs to come to the rescue! In this presentation, I will highlight several fundamental changes for FPGAs that are introduced in the new Stratix 10 family: (1) HyperFlex – a fresh re-design of routing fabric architecture allowing logic to be heavily pipelined without resource penal-ties and targetting twice the performance of existing FPGAs; (2) modularity and software-controlled FPGA configuration – allowing independent housekeeping and re-configuration for device sectors; and (3) extensive use of 3D integration across Intel’s embedded multi-die interconnect bridge (EMIB) tech-nology – allowing not just in-package memory and heteroge-neous devices but mixed-process development to de-risk and optimise analogue and digital design on different technology processes.

Mike Hutton is an IC design architect at Altera and principal in-vestigator in the Altera Technology Office. He is responsible for product architecture definition for new devices, most recently the Stratix 10 family, and research within the Technology Of-fice. He received a BMath and MMath in Computer Science from Waterloo and a PhD from the University of Toronto. He is Associate Editor of IEEE Trans. CAD, past Programme and General Chair of the Int’l Symposium on FPGAs and has ser-ved on the Technical Programme Committees for many re-search conferences, including DAC, DATE, FPGA, FPL and FPT.

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Title unavailable at time of printingPanagiotis Tsarchopoulos (European Commission, BE)Royal Institution Theatre, 13:00 Thursday 3 September 2015

Abstract unavailable at time of printing.

Conference Guide

Field-programmable NeurocomputingSteve Furber (University of Manchester, UK)Royal Institution Theatre, 09:00 Friday 4 September 2015

SpiNNaker is a massively parallel computer system, ultimate-ly to incorporate a million ARM processor cores (the largest machine to date has 100,000 cores) with an innovative, light-weight packet-switched communications fabric capable of sup-porting typical biological connectivity patterns in biological real time. One of the key principles in the design of SpiNNaker, based on the observation that different brain regions have dif-ferent connectivity patterns, is to virtualise topology, effectively decoupling the topology of the network being modelled from the topology of the machine itself. As a result, SpiNNaker can be viewed as a large field-programmable neurocomputer, whe-re the neural circuit can be configured flexibly at run-time. The network can be described using a neural HDL such as PyNN or Nengo, and then the design tools compile the network onto the machine where it runs in biological real time.

Steve Furber CBE FRS FREng is ICL Professor of Computer Engineering in the School of Computer Science at the Univer-sity of Manchester, UK. After completing a BA in mathematics and a PhD in aerodynamics at the University of Cambridge, UK, he spent the 1980s at Acorn Computers, where he was a principal designer of the BBC Microcomputer and the ARM 32-bit RISC microprocessor. Over 60 billion variants of the ARM processor have since been manufactured, powering much of the world‘s mobile and embedded computing. He moved to the ICL Chair at Manchester in 1990 where he leads research into asynchronous and low-power systems and, more recently, neural systems engineering, where the SpiNNaker project is delivering a computer incorporating a million ARM processors optimised for brain modelling applications.

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The London Centre houses a study abroad program for up to forty-two students and two faculty during each academic term.

In addition, the London Centre sponsors and cosponsors events with academic institutions in the UK and on the Euro-pean continent.

London Centre David Kirkham

Academic Director 27 Palace Court London W2 4LP

BYU London Centre Brigham Young University’s base of operations in the United Kingdom

Conference Guide

Programme Detail forMonday 31 August 2015

WorkshopW1: ReC4P 2015 – First International Workshop on Recon-figurable Computing for HPC and HPDAImperial College London EE room 611, 09:00 – 12:30Antonino Tumeo (Pacific Northwest National Laboratory, US)Gianluca Palermo (Politecnico di Milano, IT)

TutorialT1: NetFPGA – Rapid Prototyping of High-bandwidth De-vices in Open SourceImperial College London EE room 1109, 09:00 – 12:30Andrew Moore (University of Cambridge, UK)Noa Zilberman (University of Cambridge, UK)Yury Audzevich (University of Cambridge, UK)

TutorialT2: Rapid Development of Real-time Applications with Na-tional Instruments LabVIEWImperial College London EE room 1109, 13:30 – 17:00Dustyn Blasig (National Instruments, US)

Industrial workshopIW1: Xilinx System Design with ZynqImperial College London EE room 507, 09:00 – 17:00Cathal McCabe (Xilinx, IE)

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Programme Detail forTuesday 2 September 2015

WorkshopW3: FSP 2015 – Second International Workshop on FPGAs for Software ProgrammersImperial College London EE room 611, 09:00 – 17:00Tobias Becker (Maxeler, UK)Frank Hannig (Universität Erlangen-Nürnberg, DE)Dirk Koch (University of Manchester, UK)Daniel Ziener (Universität Erlangen-Nürnberg, DE)

TutorialT3: Underneath the FPGA Clothes – Enhancing SecurityImperial College London EE room 1109, 09:00 – 12:30Viktor Fischer (University of Saint-Etienne, FR)Lilian Bossuet (University of Saint-Etienne, FR)Jean-Luc Danger (TELECOM ParisTech, FR)

TutorialT4: The LEAP Run-time System – Rapid System Integrati-on of Your HLS KernelsImperial College London EE room 1109, 13:30 – 17:00Michael Adler (Intel, US)Kermin Fleming (Intel, US)Hsin-Jung Yang (Massachusetts Institute of Technology, US)Felix Winterstein (Imperial College London, UK)

Industrial workshopIW2: Overview of Altera’s Cyclone V SoC Devices and De-sign ToolsImperial College London EE room 304, 09:00 – 17:00Blair Fort (Altera, US)

Industrial workshopIW3: Xilinx SDSoC: Building Software-defined Systems-on-Chip with Zynq All-programmable SoCsImperial College London EE room 507, 09:00 – 17:00Cathal McCabe (Xilinx, IE)

Conference Guide

Programme Detail forWednesday 2 September 2015

Poster sessionPhD ForumRoyal Institution Georgian Room, 10:00 – 10:40

Greedy Approach-based Heuristics for Partitioning SpMxV on FPGAsJiasen Huang, Weina Lu and Junyan RenScheduling-aware Interconnect Synthesis for FPGA-based Multi-processor System-on-ChipEdoardo Fusella, Alessandro Cilardo and Antonino MazzeoRapid Prototyping and Design Space Exploration Methodolo-gies for Many-accelerator SystemsEfstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozi-os, George Economakos and Dimitrios SoudrisTowards a Guided Design Flow for Heterogeneous Reconfigu-rable ArchitecturesTimm Bostelmann and Sergei SawitzkiHigh-level Synthesis Extensions for Scalable Single-chip Ma-ny-accelerators on FPGAsDionysios Diamantopoulos, Sotirios Xydis, Kostas Siozios and Dimitrios SoudrisFPGA-based All-digital Software-defined Radio ReceiverAndré Prata, Arnaldo Oliveira and Nuno CarvalhoOver Effective Hard Real-time Hardware Tasks Scheduling and AllocationZakarya Guettatfi, Omar Kermia and Abdelhakim KhouasFPGA-based All-digital TransmittersRui Cordeiro, Arnaldo Oliveira and José VieiraA Framework for Integrated Monitoring of Real-time Embed-ded SoCGiacomo Valente

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Technical sessionApplications 1: Linear Algebra and Control ApplicationsRoyal Institution Theatre, 10:40 – 12:00

Efficient Assembly for High-order Unstructured FEM MeshesPavel Burovskiy, Paul Grigoras, Spencer Sherwin and Wayne LukA Scalable FPGA Architecture for Non-negative Least Squares ProblemsAlric Althoff and Ryan KastnerTowards Heterogeneous Solvers for Large-scale Linear Sys-temsStylianos Venieris, Grigorios Mingas and Christos-Savvas BouganisA Software Configurable Coprocessor-based State-space ControllerAaron Mills, Pei Zhang, Sudhanshu Vyas, Phillip Jones and Joseph Zambreno

Technical sessionArchitectures & Technology 1: Energy-efficient and Low-power ArchitecturesRoyal Institution Conversation Room, 10:40 – 12:00

Automatic Generation of High-throughput Energy-efficient Streaming Architectures for Arbitrary Fixed PermutationsRen Chen and Viktor PrasannaUsing FPGA-style Intra-CLB Routing in Low-power FPGAsOluseyi Ayorinde and Benton CalhounEnergy Optimization of FPGA-based Stream-oriented Compu-ting with Power GatingMohammad Hosseinabady and Jose Nunez-YanezEnergy-efficient Partitioning of Dynamic Reconfigurable MRAM-FPGAsAli Ahari, Mojtaba Ebrahimi and Mehdi Tahoori

Conference Guide

Technical sessionDesign Methods & Tools 1: Parallelism and Logic DesignRoyal Institution Demo Room, 10:40 – 12:00

Automatic Support for Multi-module Parallelism from Compu-tational PatternsNithin George, HyoukJoong Lee, David Novo, Muhsen Owai-da, David Andrews, Kunle Olukotun and Paolo IenneParaLaR: A Parallel FPGA Router Based on Lagrangian Re-laxationChin Hau Hoo, Akash Kumar and Yajun HaFine-tuning CLB Placement to Speed Up Reconfigurations in NVM-based FPGAsYuan Xue, Patrick Cronin, Chengmo Yang and Jingtong HuA Technology Mapper for Depth-constrained FPGA Logic CellsZhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Liqun Yang, Zhihong Huang, Haigang Yang and Paolo Ienne

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Poster sessionApplicationsRoyal Institution Georgian Room, 15:00 – 15:40

An FPGA Implementation of a Phylogenetic Tree Reconstruc-tion Algorithm Using an Alternative Second-pass OptimizationHenry Block and Tsutomu MaruyamaUltra Low-latency Dataflow RendererSebastian Friston, Anthony Steed, Simon Tilbury and Georgi GaydadjievExploring with Pipe Implementations using an OpenCL Frame-work for FPGAsVincent Mirian and Paul ChowParallel Feature Extraction and Heterogeneous Object Detec-tion for Multi-camera Driver Assistance SystemsStefan Wonneberger, Peter Muehlfellner, Pedro Ceriotti, Thorsten Graf and Rolf ErnstA Transport Layer Network for Distributed FPGA PlatformsSang-Woo Jun, Ming Liu, Shuotao Xu and Arvind ArvindGenerating FPGA Accelerators for Chemical Similarity Assess-mentNikolaos AlachiotisrrBox: A Remote Dynamically Reconfigurable Network-proces-sing MiddleboxTze Tan, Chia Ooi and Nadzir MarsonoFPGA-based Nonlinear Support Vector Machine Training Using an Ensemble LearningMudhar Rabieah and Christos-Savvas Bouganis

Conference Guide

Demo NightRoyal Institution Library, 18:15 – 20:00

AmBRAMs – An Analysis Tool, Method and Framework for Advanced Measurements And Reliability Assessments on Mo-dern Nanoscale FPGAsPetr Pfeifer7 MOPS/Lemon-battery Image Processing Demonstration with an Ultra Low-power Reconfigurable Accelerator CMA-SOTB-2Koichiro Masuyama, Yu Fujita, Hayate Okuhara and Hideharu AmanoDesign and Simulation Tools for Embedded NoCs on FPGAsMohamed Abdelfattah, Andrew Bitar, Ange Yaghi and Vaughn BetzNetFPGA – Rapid Prototyping of High-bandwidth Devices in Open SourceNoa Zilberman, Yury Audzevich, Georgina Kalogeridou, Nee-lakandan Manihatty-Bojan, Jingyun Zhang and Andrew MooreBuilding a Distributed Key-value Store with FPGA-based Mic-ro-serversZsolt Istvan, David Sidler and Gustavo AlonsoHigh-Level FPGA Logic Synthesis from .NET Programs for Software DevelopersZoltán Lehóczky, Richárd Tóth and Krisztián SomogyiHierarchical Library-based Power Estimator for Versatile FP-GAsHao Liang, Wei Zhang, Sharad Sinha, Yi-Chung Chen and Hai LiFPGA-based All-digital Software-defined Radio System De-monstrationRui Cordeiro, André Prata, Arnaldo Oliveira, Nuno Carvalho and José VieiraComputing to the Limit with CPU-FPGA Hybrids and Adaptive Voltage ScalingJose Nunez-YanezDynamic Voltage and Frequency Scaling: a Real-world Ex-ampleJames Davis, Joshua Levine, Edward Stott, George Constan-tinides and Peter Cheung

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The Maxeler AdvantageDataflow computing from Maxeler transforms business and science with order-of-magnitude improvements in performance, computation per watt and total cost of ownership compared to conventional computing systems, completely redefining what is possible. Dataflow computing optimizes the movement of data in an application and utilizes massive parallelism between thousands of tiny dataflow cores.

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Conference Guide

Programme Detail forThursday 3 September 2015

Poster sessionArchitectures & TechnologyRoyal Institution Georgian Room, 10:00 – 10:40

Optimizing Energy-efficient Low-swing Interconnect for Sub-threshold FPGAsHe Qi, Oluseyi Ayorinde, Yu Huang and Benton CalhounAn Automated Technique to Generate Relocatable Partial Bit-streams for Xilinx FPGAsRoel Oomen, Tuan Nguyen, Akash Kumar and Henk CorporaalPipelined and Customized NoC Router Architecture Design on FPGAQi Chen and Qiang LiuAccurate Power Analysis for Near-Vt RRAM-based FPGAXifan Tang, Pierre-Emmanuel Gaillardon and Giovanni De Mi-cheliOpenCL Computing on FPGA Using Multi-ported Shared Me-moryTahsin Türker Mutlugün and Sheng-De WangAdaptive MRAM-Based CGRAsXiaobin Liu, Tedy Thomas, Alan Boguslawski and Russell Tes-sierReduction Calculator in an FPGA-based Switching Hub for High-performance ClustersTakuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa and Hide-haru AmanoSerial and Parallel Interleaved Modular Multipliers on FPGA PlatformKhalid Javeed, Xiaojun Wang and Mike ScottData Protection Using Recursive Inverse FunctionTeng Xu, Hongxiang Gu and Miodrag Potkonjak

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Technical sessionApplications 2: Computer Vision and Numerical Applica-tionsRoyal Institution Theatre, 10:40 – 12:00

A Deep Convolutional Neural Network using Nested Residue Number SystemHiroki Nakahara and Tsutomu SasaoA Fast Hierarchical Implementation of Sequential Tree-re-weighted Belief Propagation For Probabilistic InferenceSkand Hurkat, Jungwook Choi, Eriko Nurvitadhi, José Martí-nez and Rob RutenbarA Scalable Pipelined Architecture for Biomimetic Vision Sen-sorsDaniel Llamocca and Brian DeanFPGA Implementation to Estimate the Number of Endmem-bers in Hyperspectral ImagesCarlos Gonzalez, Sebastian Lopez, Daniel Mozos and Rober-to Sarmiento

Technical sessionArchitectures & Technology 2: Cryptography and Security ArchitecturesRoyal Institution Conversation Room, 10:40 – 12:00

Compact Dual-block AES core on FPGA for CCM ProtocolJoão Resende and Ricardo ChavesTowards Efficient Discrete Gaussian Sampling for Lattice-based CryptographyChaohui Du and Guoqiang BaiAn Efficient Many-core Architecture for Elliptic Curve Crypto-graphy Security AssessmentMarco Indaco, Fabio Lauri, Andrea Miele and Pascal TrottaHigh-speed ECC Implementation on FPGA over GF(2m)Zia Khan and Mohammed Benaissa

Conference Guide

Technical sessionDesign Methods & Tools 2: Accelerators and High-level SynthesisRoyal Institution Demo Room, 10:40 – 12:00

SPINE: From C Loop-nests to Highly Efficient Accelerators using Algorithmic SpeciesMark Wijtvliet, Shakith Fernando and Henk CorporaalOptimised OpenCL Workgroup Synthesis for Hybrid ARM-FP-GA DevicesMohammad Hosseinabady and Jose Nunez-YanezAn Interface and Mechanism Efficiently Supporting Key Memo-ry Access Patterns in FPGA ComputingGabriel Weisz and James HoeScavenger: Automating the Construction of Application-opti-mized Memory HierarchiesHsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winter-stein and Joel Emer

Technical sessionApplications 3: Pattern-matching and Search ApplicationsRoyal Institution Theatre, 14:00 – 15:00

Power-efficient Range Match-based Packet Classification on FPGAYun Qu and Viktor PrasannaA Variable-length Hash Method for Faster Short Read Mapping on FPGAYoko Sogabe and Tsutomu MaruyamaHybrid Breadth-first Search on a Single-chip FPGA-CPU He-terogeneous PlatformYaman Umuroglu, Donn Morrison and Magnus Jahre

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Technical sessionArchitectures & Technology 3: Reconfigurable Computing and ArchitecturesRoyal Institution Conversation Room, 14:00 – 15:00

A Fully Pipelined Kernel-normalised Least Mean Squares Pro-cessor For Accelerated Parameter OptimisationNicholas Fraser, Duncan Moss, Jun-Kyu Lee, Stephen Tridgell, Craig Jin and Philip LeongAn Efficient Reconfigurable Architecture by Characterizing Most Frequent Logic FunctionsIman Ahmadpour, Behnam Khaleghi and Hossein AsadiStatic Hardware Task Placement on Multi-context FPGA using Hybrid Genetic AlgorithmHao Liang, Sharad Sinha, Rakesh Warrier and Wei Zhang

Technical sessionDesign Methods & Tools 3: Simulation and EmulationRoyal Institution Demo Room, 14:00 – 15:00

Domain-specific Optimisation for the High-level Synthesis of Cell Simulation AcceleratorsJulian Oppermann, Andreas Koch, Ting Yu and Oliver SinnenSoftware-in-the-loop Simulation of Embedded Control Applica-tions based on Virtual PlatformsStephan Werner, Leonard Masing and Juergen BeckerUltra-fast NoC Emulation on a Single FPGAThiem Van Chu, Shimpei Sato and Kenji Kise

Conference Guide

Poster sessionDesign Methods & ToolsRoyal Institution Georgian Room, 15:00 – 15:40

In-field Vulnerability Analysis of FPGA-realized Computer Vi-sion ApplicationsIoannis Chadjiminas, Christos Kyrkou, Christos Ttofis, Theo-charis Theocharides and Maria MichaelA Rapid Prototyping Framework for Nano-photonic Accelera-torsAlberto Garcia-Ortiz, Wolfgang Büter, A. Ali, S. Mahmood, S. Arefin, V. Sreenivas and R. BergmanFast FPGA System for Microarchitecture Optimization on Syn-thesizable Modern Processor DesignLibo Huang, Yongwen Wang, Qiang Dou, Caixia Sun, Chengyi Zhang and Chao XuAn LZ77-style Bit-level Compression for Trace Data Compac-tionKai-Uwe Irrgang and Thomas PreußerMind The (Synthesis) Gap: Examining Where Academic FPGA Tools Lag Behind IndustryEddie HungRapid Evaluation of FPGA Architecture Routability Without BenchmarksOleg Petelin and Vaughn BetzTemperature-triggered Behavioral IPs Hardware Trojan Detec-tion Method with FPGAsXiaotong Li and Benjamin SchaferEstimating Circuit Delays in FPGAs after Technology MappingBerg Severens, Elias Vansteenkiste, Karel Heyse and Dirk Stroobandt

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Technical sessionApplications 4: High-level Synthesis and OptimisationRoyal Institution Theatre, 15:40 – 17:00

From Low-architectural Expertise Up to High-throughput Non-binary LDPC Decoders: Optimization Guidelines using High-level SynthesisJoao Andrade, Nithin George, Kimon Karras, David Novo, Vitor Silva, Paolo Ienne and Gabriel FalcaoA study of Data Partitioning on OpenCL-based FPGAsZeke Wang, Bingsheng He and Wei ZhangLimits of FPGA Acceleration of 3D Green‘s Function Computa-tion for Geophysical ApplicationsNachiket Kapre, Selvakumar Jayakrishnan, Parjanya Gupta, Sagar Masuti and Sylvain BarbotRecursive Pipelined Genetic Propagation for Bilevel Optimisa-tionShengjia Shao, Liucheng Guo, Ce Guo, Thomas Chau, Wayne Luk and Stephen Weston

Technical sessionArchitectures & Technology 4: Architectures and Synthe-sisRoyal Institution Conversation Room, 15:40 – 17:00

Synthesizable FPGA Fabrics Targetable by the Verilog-to-Rou-ting (VTR) CADJin Hee Kim and Jason AndersonHoplite: Building Austere Overlay NoCs for FPGAsNachiket Kapre and Jan GrayFPGA-based Low-overhead Speculative Addition for Signed OperandsAlessandro CilardoInter-procedural Resource-sharing in High-level Synthesis through Function ProxiesMarco Minutoli, Vito Giovanni Castellana, Antonino Tumeo and Fabrizio Ferrandi

Conference Guide

Technical sessionDesign Methods & Tools 4: Hybrid FPGA-based SystemsRoyal Institution Demo Room, 15:40 – 16:40

Enabling Seamless Execution on Hybrid CPU/FPGA Systems: Challenges & DirectionsMeena Belwal, Madhura Purnaprajna and Sudarshan TSBHybrid FPGA Debug ApproachZdravko PanjkovA High-performance Protocol for Exposing IP Cores as Func-tions in a Shared-bus SoCDavid Thomas, George Constantinides, Shane Fleming and Ivan Beretta

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Programme Detail forFriday 4 September 2015

Poster sessionSelf-aware & Adaptive SystemsRoyal Institution Georgian Room, 10:00 – 10:40

A Run-time Interpretation Approach For Creating Custom Ac-celeratorsSen Ma, Zeyad Aklah and David AndrewsData-triggered Breakpoint for In-circuit Debug without Re-im-plementationYutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba and Kaoru KawamuraCharacterisation of Feasibility Regions in FPGAs Under Ad-aptive DVFSNizar Dahir, Pedro Campos, Gianluca Tempesti, Martin Trefzer and Andrew TyrrellA Resilient, Flash-free Soft Error Mitigation Concept for the CBM-ToF Read-out Chain via GBT-SCAAndrei-Dumitru Oancea, Christian Stuellein, Jano Gebelein and Udo KebschullUniStream: A Unified Stream Architecture Combining Configu-ration and Data ProcessingJian Yan, Jifang Jin, Ying Wang, Xuegong Zhou, Philip Leong and Lingli WangPlacing Partially Reconfigurable Stream-processing Applica-tions on FPGAsNicolae Grigore and Dirk KochA Portable Open-source Controller for Safe Dynamic Partial Reconfiguration on Xilinx FPGAsJan Andersson, Stefano Di Carlo, Paolo Prinetto and Pascal Trotta

Conference Guide

WorkshopW4: RC4Masses – Workshop on Reconfigurable Compu-ting for the Masses, Really?Royal Institution Theatre, 10:40 – 12:15Paolo Ienne (École Polytechnique Fédérale de Lausanne, CH)David Andrews (University of Arkansas, US)Walid Najjar (University of California Riverside, US)

WorkshopW5: WCS-IoT 2015 – First International Workshop on Com-ponents and Services for IoT platformsRoyal Institution Conversation Room, 10:40 – 12:15Michael Hübner (Ruhr-Universität Bochum, DE)Nikolaos Voros (Technological Educational Institute of Western Greece, GR)Georgios Keramidas (Technological Educational Institute of Western Greece, GR)

Technical sessionArchitectures & Technology 5: Memory Management and Customised ArchitecturesRoyal Institution Demo Room, 10:40 – 12:00

SysAlloc: A Hardware Manager for Dynamic Memory Alloca-tion in Heterogeneous SystemsZeping Xue and David ThomasEfficient Data-Stream Management for Shared Memory Many-core SystemsNuno Neves, Pedro Tomás and Nuno RomaA Scalable Architecture for Multi-class Visual Object DetectionSiddharth Advani, Yasuki Tanabe, Kevin Irick, Jack Sampson and Vijaykrishnan NarayananEnhancing Stochastic Computations via Process VariationRui Duarte, Mário Véstias and Horácio Neto

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WorkshopW4: RC4Masses – Workshop on Reconfigurable Compu-ting for the Masses, Really?Imperial College London EE room 408, 13:30 – 17:00Paolo Ienne (École Polytechnique Fédérale de Lausanne, CH)David Andrews (University of Arkansas, US)Walid Najjar (University of California Riverside, US)

WorkshopW5: WCS-IoT 2015 – First International Workshop on Com-ponents and Services for IoT platformsImperial College London EE room 611, 13:30 – 17:00Michael Hübner (Ruhr-Universität Bochum, DE)Nikolaos Voros (Technological Educational Institute of Western Greece, GR)Georgios Keramidas (Technological Educational Institute of Western Greece, GR)

Conference Guide

Gateware Defined Networking®

• Deterministic and jitter-free processing• 10, 25, 40, and 100 Gbps Ethernet• Ultra-low-latency packet search (sub-µs)• Fully customizable cores and solutions

Algo-Logic delivers GDN solutions for software level programmability with ASIC-level performance.

Key Features:

GDN Solutions:

Low Latency Trading

Scalable Cloud Services

Key Value Store (KVS)

TCP Endpoint

Conference Guide

Special SessionSpecial sessionFPL – The Past 25 Years and Next 25 YearsRoyal Institution Theatre, 14:00 Wednesday 2 September

As this is the 25th edition of FPL, we are pleased to have a special session focussing on the past and especially on the next 25 years of field-programmable technology. The session will contain seven talks from key industrial players.

Reconfiguring the Datacenter: Building the Infrastructure for Enterprise-class FPGASalem Derisavi (Huawei)From Data to Information to FlowOskar Mencer (Maxeler)Early Reconfigurable Computing and the Changing Technolo-gical LandscapeMark Shand (Google)The Impact of System-on-Chips on Your Design MethodsRieny Rijnen (Topic Embedded Systems)The Future: Not What it Used to beJohn Watson (Micron)Gateware Defined Neworking (GDN) Goes Mainstream John Lockwood (Algo-Logic)The Golden Age of FPGAsKubilay Atasu (IBM)

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CommitteesOrganising Committee

General ChairsPeter Cheung (Imperial College London, UK)Wayne Luk (Imperial College London, UK)

Programme ChairCristina Silvano (Politecnico di Milano, IT)

Track ChairsArchitectures and TechnologyJason Anderson (University of Toronto, CA)Applications and BenchmarksDirk Koch (University of Manchester, UK)Design Methods and ToolsDirk Stroobandt (Universiteit Gent, BE)Self-aware and Adaptive SystemsMarco Platzner (Universität Paderborn, DE)Surveys, Trends and EducationWalid Najjar (University of California Riverside, US)

Workshop and Tutorial Chairs Guy Gogniat (Université de Bretagne Sud, FR)Bob Stewart (University of Strathclyde, UK)

Industrial Workshop ChairChristos Bouganis (Imperial College London, UK)

Panel ChairsMichael Hübner (Ruhr-Universität Bochum, DE)Simon Moore (University of Cambridge, UK)

PhD Forum ChairsDimitrios Soudris (National Technical University of Athens, GR)Andy Tyrell (University of York, UK)

Demo Night and Project Presentation ChairsKoen Bertels (Technische Universiteit Delft, NL)Jose Nunez-Yanez (University of Bristol, UK)

Conference Guide

Proceedings ChairWalter Stechele (Technische Universität München, DE)

Local Arrangement TeamWiesia Hsissen (Imperial College London, UK)Joshua Levine (Imperial College London, UK)Xinyu Niu (Imperial College London, UK)Edward Stott (Imperial College London, UK)

WebmasterJames Davis (Imperial College London, UK)

Submissions ChairDavid Boland (Monash University, AU)

Publicity ChairsEurope and AfricaKubilay Atasu (IBM, CH)Central and South AmericaClaudia Feregrino (Instituto Nacional de Astrofísica, Óptica y Electrónica, MX)North AmericaHenry Styles (Xilinx, US)AsiaTerence Mak (Chinese University of Hong Kong, HK)AustralasiaOlivier Diessel (University of New South Wales, AU)

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Steering Committee

Jürgen Becker (Karlsruher Institut für Technologie, DE)Koen Bertels (Technische Universiteit Delft, NL)Eduardo Boemo (Universidad Autónoma de Madrid, ES)João Cardoso (Universidade do Porto, PT)Peter Cheung (Imperial College London, UK)Martin Danek (Daiteq, CZ)Apostolos Dollas (Technical University of Crete, GR)Fabrizio Ferrandi (Politecnico di Milano, IT)Manfred Glesner (Technische Universität Darmstadt, DE)John Gray (Consultant, UK)Reiner Hartenstein (Technische Universität Kaiserslautern, DE)Andreas Herkersdorf (Technische Universität München, DE)Udo Kebschull (Goethe Universität Frankfurt, DE)Wayne Luk (Imperial College London, UK)Patrick Lysaght (Xilinx, US)Jari Nurmi (Tampereen Teknillinen Yliopisto, FI)Lionel Torres (Université de Montpellier 2, FR)Jim Tørresen (Universitetet i Oslo, NO)

Technical Programme Committee

Norbert Abel (Endace, NZ)Tanvir Ahmed (Tokyo Institute of Technology, JP)Hideharu Amano (Keio University, JP)David Andrews (University of Arkansas, US)Kubilay Atasu (IBM Research, CH)Peter Athanas (Virginia Tech, US)Jürgen Becker (Karlsruher Institut für Technologie, DE)Tobias Becker (Maxeler Technologies, UK)Pascal Benoit (Université Montpellier 2, FR)Mladen Berekovic (Technische Universität Braunschweig, DE)Neil Bergmann (University of Queensland, AU)Dustyn Blasig (National Instruments, US)Michaela Blott (Xilinx, IE)Christophe Bobda (University of Arkansas, US)Eduardo Boemo (Universidad Autónoma de Madrid, ES)Cristiana Bolchini (Politecnico di Milano, IT)

Conference Guide

Christos-Savvas Bouganis (Imperial College London, UK)Eli Bozorgzadeh (University of California Irvine, US)Gordon Brebner (Xilinx, IE)Philip Brisk (University of California Riverside, US)Steve Brown (Altera, CA)Oswaldo Cadenas (University of Reading, UK)João Cardoso (Universidade do Porto, PT)Benjamin Schafer (Hong Kong Polytechnic University, HK)Luigi Carro (Universidade Federal do Rio Grande do Sul, BR)Jerónimo Castrillón (Technische Universität Dresden, DE)Deming Chen (University of Illinois at Urbana-Champaign, US)Ray Cheung (City University of Hong Kong, HK)Kiyoung Choi (Seoul National University, KR)Paul Chow (University of Toronto, CA)Christopher Claus (Bosch, DE)Jason Cong (University of California Los Angeles, US)Philippe Coussy (Université de Bretagne Sud, FR)José Coutinho (Imperial College London, UK)René Cumplido (Instituto Nacional de Astrofisica, MX)Martin Danek (Daiteq, CZ)Anup Das (University of Southampton, UK)Eduardo De La Torre (Universidad Politécnica de Madrid, ES)Christian De Schryver (Universität Kaiserslautern, DE)Steven Derrien (Université de Rennes 1, FR)Oliver Diessel (University of New South Wales, AU)Giorgos Dimitrakopoulos (Democritus University of Thrace, GR)Pedro Diniz (University of Southern California, US)Apostolos Dollas (Technical University of Crete, GR)Adam Donlin (Xilinx, US)Carl Ebeling (Altera, US)Peeter Ellervee (Tallinna Tehnikaülikool, EE)Suhaib Fahmy (Nanyang Technological University, SG)Claudia Feregrino (Instituto Nacional de Astrofísica, Óptica y Electrónica, MX)Fabrizio Ferrandi (Politecnico di Milano, IT)William Fornaciari (Politecnico di Milano, IT)Blair Fort (Altera, US)Georgi Gaydadjiev (Maxeler Technologies, UK)Roberto Giorgi (Università di Siena, IT)

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Manfred Glesner (Technische Universität Darmstadt, DE)Diana Göehringer (Ruhr-Universität Bochum, DE)Guy Gogniat (Université de Bretagne Sud, FR)Maya Gokhale (Lawrence Livermore National Laboratory, US)Kees Goossens (Technische Universiteit Eindhoven, NL)Ann Gordon-Ross (University of Florida, US)Marcel Gort (Altera, CA)David Greaves (University of Cambridge, UK)Jonathan Greene (Microsemi, US)Yajun Ha (National University of Singapore, SG)Peter Hallschmid (University of British Columbia, CA)Ilker Hamzaoglu (Sabanci Üniversitesi, TR)Yuko Hara-Azumi (Tokyo Institute of Technology, JP)Reiner Hartenstein (Technische Universität Kaiserslautern, DE)Martin Herbordt (Boston University, US)Andreas Herkersdorf (Technische Universität München, DE)Michael Hübner (Ruhr-Universität Bochum, DE)Eddie Hung (Imperial College London, UK)Paolo Ienne (École Polytechnique Fédérale de Lausanne, CH)Arpith Jacob (IBM Research, US)Nachiket Kapre (Nanyang Technological University, SG)Sinan Kaptanoglu (Microsemi, US)Wolfgang Karl (Karlsruher Institut für Technologie, DE)Ryan Kastner (University of California San Diego, US)Alireza Kaviani (Xilinx, US)Tom Kean (Algotronix, UK)Udo Kebschull (Goethe Universität Frankfurt, DE)Andrew Kennings (University of Waterloo, CA)Kenneth Kent (University of New Brunswick, CA)Yoonjin Kim (Sookmyung Women‘s University, KR)Kenji Kise (Tokyo Institute of Technology, JP)Vipin Kizheppatt (Mahindra École Centrale, IN)Andreas Koch (Technische Universitát Darmstadt, DE)Jan Korenek (Brno University of Technology, CZ)Farinaz Koushanfar (Rice University, US)Yana Krasteva (Universitat Politècnica de València, ES)Wolfgang Kühn (Justus-Liebig-Universität Gießen, DE)Akash Kumar (National University of Singapore, SG)Jan Kuper (Universiteit Twente, NL)

Conference Guide

Georgi Kuzmanov (Electronic Components and Systems for European Leadership Joint Undertaking, BE)Martin Langhammer (Altera, US)Luciano Lavagno (Politecnico di Torino, IT)Jongeun Lee (Ulsan National Institute of Science and Techno-logy, KR)Miriam Leeser (Northeastern University, US)Guy Lemieux (University of British Columbia, CA)Philip Leong (University of Sydney, AU)Enno Lübbers (Intel Labs, DE)Mikel Luján (University of Manchester, UK)Patrick Lysaght (Xilinx, US)Roman Lysecky (University of Arizona, US)Wai-Kei Mak (National Tsing Hua University, TW)Terrence Mak (The Chinese University of Hong Kong, HK)Liam Marnane (University College Cork, IE)Andrea Marongiu (Eidgenössische Technische Hochschule Zürich, CH)Tsutomu Maruyama (University of Tsukuba, JP)Konstantinos Masselos (Imperial College London, UK)Cathal McCabe (Xilinx, IE)Nele Mentens (Katholieke Universiteit Leuven, BE)Antonio Miele (Politecnico di Milano, IT)Tulika Mitra (National University of Singapore, SG)Andrew Moore (University of Cambridge, UK)Carlos Morra (Siemens, DE)Brent Nelson (Brigham Young University, US)Smail Niar (Université de Valenciennes, FR)David Novo (École Polytechnique Fédérale de Lausanne, CH)Gianluca Palermo (Politecnico di Milano, IT)Ioannis Papaefstathiou (Technical University of Crete, GR)Sri Parameswaran (University of New South Wales, AU)Joonseok Park (Inha University, KR)Yongjun Park (Hongik University, KR)Cameron Patterson (Virginia Tech, US)Christian Pilato (Columbia University, US)Sébastien Pillement (Université de Nantes, FR)Thilo Pionteck (Universität zu Lübeck, DE)Christian Plessl (Universität Paderborn, DE)Dionisios Pnevmatikatos (Technical University of Crete, GR)

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Mario Pormann (Universität Bielefeld, DE)Dan Poznanovic (Cray, US)Viktor Prasanna (University of Southern California, US)Rodric Rabbah (IBM Research, US)Teresa Riesgo (Universidad Politécnica de Madrid, ES)Jonathan Rose (University of Toronto, CA)Kyle Rupnow (Advanced Digital Sciences Center, SG)Mazen Saghir (Texas A&M University at Qatar, QA)Chiara Sandionigi (Commissariat à l‘Énergie Atomique et aux Énergies Alternatives, FR)Kentaro Sano (Tohoku University, JP)Marco Santambrogio (Politecnico di Milano, IT)Ron Sass (University of North Carolina at Charlotte, US)Martin Schoeberl (Danmarks Tekniske Universitet, DK)Paul Schumacher (Xilinx, US)Donatella Sciuto (Politecnico di Milano, IT)Lukas Sekanina (Brno University of Technology, CZ)Olivier Sentieys (Université de Rennes 1, FR)Muhammad Shafique (Karlsruher Institut für Technologie, DE)Lesley Shannon (Simon Fraser University, CA)Nicolas Sklavos (University of Patras, GR)Ioannis Sourdis (Chalmers Tekniska Högskola, SE)Walter Stechele (Technische Universität München, DE)Henry Styles (Xilinx, US)Jürgen Teich (Friedrich-Alexander-Universität Erlangen-Nürn-berg, DE)Russell Tessier (University of Massachusetts Amherst, US)David Thomas (Imperial College London, UK)Tim Todman (Imperial College London, UK)Hiroyuki Tomiyama (Ritsumeikan University, JP)Lionel Torres (Université de Montpellier 2, FR)Jim Tørresen (Universitetet i Oslo, NO)Steve Trimberger (Xilinx, US)Tom VanCourt (Altera, US)Wim Vanderbauwhede (University of Glasgow, UK)Ana Lucia Varbanescu (Universiteit van Amsterdam, NL)Milan Vasilko (Aeon Ventures, UK)Tanya Vladimirova (University of Leicester, UK)Nikolaos Voros (Technological Educational Institute of Western Greece, GR)

Conference Guide

Qiang Wang (Huawei, US)John Wawrzynek (University of California Berkeley, US)Norbert Wehn (Technische Universität Kaiserslautern, DE)Markus Weinhardt (Hochschule Osnabrück, DE)Steve Wilton (University of British Columbia, CA)Mike Wirthlin (Brigham Young University, US)Stephan Wong (Technische Universiteit Delft, NL)Roger Woods (Queen‘s University Belfast, UK)Sotirios Xydis (National Technical University of Athens, GR)Yoshiki Yamaguchi (University of Tsukuba, JP)Wei Zhang (Hong Kong University of Science and Technology, HK)Daniel Ziener (Friedrich-Alexander-Universität Erlangen-Nürn-berg DE)Peter Zipf (Universität Kassel, DE)

www.xilinx.com/university

Conference Guide

City Map

Conference Guide

Underground Map

Conference Guide

About LondonLondon is the capital and most populous city of England and the United Kingdom. Standing on the River Thames, London has been a major settlement for two millennia, its history going back to its founding by the Romans, who named it Londinium. London’s ancient core, the City of London, largely retains its 1.12-square mile (2.9 km2) medieval boundaries and in 2011 had a resident population of 7,375, making it the smallest city in England. Since at least the 19th century, the term London has also referred to the metropolis developed around this core. The bulk of this conurbation forms Greater London, a region of England governed by the Mayor of London and the London Assembly. The conurbation also covers two English counties: the City of London and the county of Greater London.

Greater London consists of 33 districts: the 32 London bo-roughs and the City of London. The Greater London Authority is responsible for strategic local government across the region and consists of the Mayor of London and the London Assem-bly. Greater London is a ceremonial county of England. It was created on 1 April 1965 and it covers 607 square miles (1,572 km2) and had a population of 8,174,000 at the 2011 census.

“Sir, when a man is tired of London, he is tired of life; for there is in London all that life can afford.”

Samuel Johnson

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Elizabeth Tower (often incorrectly called Big Ben)Bridge StreetSW1A 0AA

Conference Guide

London SightsBritish Museum

Founded in 1753, the British Museum’s remarkable collection spans over two million years of human history. Enjoy a unique comparison of the treasures of world cultures under one roof, centred around the magnificent Great Court.

World-famous objects such as the Rosetta Stone, Parthenon sculptures and Egyptian mummies are visited by up to six mil-lion visitors per year. In addition to the vast permanent collec-tion, the museum’s special exhibitions, displays and events are all designed to advance understanding of the collection and cultures they represent.

The nearest Underground stations are Tottenham Court Road, Holborn and Russell Square.

Entrance is free.

National Gallery

The National Gallery displays over 2,000 Western European paintings from the middle ages to the 20th century. Discover in-spiring art by Botticelli, Leonardo da Vinci, Rembrandt, Gains-borough, Turner, Renoir and Van Gogh. There are special ex-hibitions, lectures, video and audio-visual programmes, guided tours and holiday events for children and adults.

The nearest Underground stations are Embankment, Charing Cross and Leicester Square.

Entrance is free.

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British MuseumGreat Russell StreetWC1B 3DG

National GalleryTrafalgar SquareWC2N 5DN

Conference Guide

Natural History Museum

See hundreds of exciting, interactive exhibits in one of Lon-don’s most beautiful landmark buildings. Highlights include the popular Dinosaurs Gallery, Mammals Display with the unfor-gettable model blue whale and the spectacular Central Hall.

Don’t miss the state-of-the-art Darwin Centre Cocoon where, on a self-guided tour, you can see hundreds of fascinating specimens and look into laboratories where scientists are at work.

The museum offers a wide-ranging programme of temporary exhibitions and events, including chances to join experts in the Darwin Centre’s high-tech Attenborough Studio in topical dis-cussions about science and nature.

The nearest Underground station is South Kensington.

Entrance is free.

Tate Modern

A visit to London isn’t complete without a trip to the Tate Mod-ern.

Britain’s national museum of modern and contemporary art from around the world is housed in the former Bankside Power Station on the banks of the Thames. The awe-inspiring Tur-bine Hall runs the length of the entire building and you can see amazing work by artists such as Cézanne, Bonnard, Matisse, Picasso, Rothko, Dalí, Pollock, Warhol and Bourgeois.

The nearest Underground stations are Southwark and Black-friars.

Entrance is free.

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Natural History MuseumCromwell RoadSW7 5BD

Tate ModernBanksideSE1 9TG

Conference Guide

London Eye

Standing at 135 metres, the London Eye is the world’s tallest cantilevered observation wheel. A feat of design and engineer-ing, it has become the modern symbol representing the capi-tal and a global icon. The experience showcases breathtaking 360-degree views of the capital and its famous landmarks.

The gradual rotation in one of the 32 high-tech glass capsules takes approximately 30 minutes and gives you an ever-chang-ing perspective of London. Within each capsule, interactive guides allow you to explore the capital’s iconic landmarks in several languages.

An experience on the London Eye will lift you high enough to see up to 40 kilometres on a clear day and keep you close enough to see the spectacular details of the city.

The nearest Underground stations are Westminster and Em-bankment.

Tickets start from £20.70.

Science Museum

The Science Museum is the most visited science and tech-nology museum in Europe. There are over 15,000 objects on display, including world-famous objects such as the Apollo 10 command capsule and Stephenson’s Rocket.

The interactive galleries bring to life first scientific principles and contemporary science debates. Plus, you can experience what it’s like to fly with the Red Arrows or blast off into space on an Apollo space mission in the stunning 3D and 4D simula-tors or watch a film on a screen taller than four double-decker buses in the IMAX 3D Cinema.

The nearest Underground station is South Kensington.

Entrance is free.

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London EyeSouth BankSE1 7PB

Science MuseumExhibition RoadSW7 2DD

Conference Guide

Tower of London

Despite the Tower of London’s grim reputation as a place of torture and death, within these walls you will also discover the history of a royal palace, an armoury and a powerful fortress. Don’t miss Royal Beasts and learn about the wild and wonder-ous animals that have inhabited the Tower, making it the first London Zoo.

Discover the priceless Crown Jewels newly displayed in 2012, join an iconic Beefeater on a tour and hear their bloody tales, stand where famous heads have rolled, learn the legend of the Tower’s ravens, storm the battlements and get to grips with swords and armour and much more!

The nearest Underground station is Tower Hill.

Tickets start from £22.00.

Tower of LondonMansell StreetEC3N 4AB

Conference Guide

About Imperial College LondonImperial College London is a public research university in the United Kingdom. Its royal patron and founder, Prince Albert, envisioned an area for public education composed of the Natu-ral History Museum, Victoria and Albert Museum, Science Mu-seum, Royal Albert Hall and the Imperial Institute. The Imperial Institute was opened by his wife, Queen Victoria, who laid the first brick. Continuing their parents’ and grandparents’ vision, Queen Elizabeth II and the Duke of York recently opened the Imperial College Business School. The university has grown through mergers including with St Mary’s Hospital Medical School, Charing Cross and Westminster Medical School, the Royal Postgraduate Medical School and the National Heart and Lung Institute. A former constituent college of the Univer-sity of London, Imperial became independent during its cen-tennial celebration.

Imperial is organised into four faculties of science, engineer-ing, medicine and business. The main campus is located in South Kensington. The university is a major biomedical re-search centre and formed the first academic health science centre in the United Kingdom. Imperial is a member of the Rus-sell Group, G5, Association of Commonwealth Universities, League of European Research Universities and the “Golden Triangle” of British universities along with the Universities of Cambridge and Oxford.

Imperial is consistently included among the top universities in the world. According to The New York Times, recruiters con-sider its students among the 10 most valued groups of gradu-ates in the world. Imperial faculty and alumni include 15 Nobel laureates, 2 Fields Medalists, 70 Fellows of the Royal Society, 82 Fellows of the Royal Academy of Engineering and 78 Fel-lows of the Academy of Medical Sciences.

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Imperial College London Royal School of MinesPrince Consort RoadSW7 2BP

Imperial College London Business SchoolExhibition RoadSW7 2AZ

Conference Guide

About the Royal InstitutionThe Royal Institution was founded in 1799 by the leading Brit-ish scientists of the age, including Henry Cavendish and its first president, George Finch, the 9th Earl of Winchilsea, for diffusing the knowledge, and facilitating the general introduc-tion, of useful mechanical inventions and improvements; and for teaching, by courses of philosophical lectures and experi-ments, the application of science to the common purposes of life.

Much of its initial funding and the initial proposal for its found-ing were given by the Society for Bettering the Conditions and Improving the Comforts of the Poor, under the guidance of philanthropist Sir Thomas Bernard and American-born British scientist Sir Benjamin Thompson, Count Rumford. Since its founding it has been based at 21 Albemarle Street in Mayfair. Its Royal Charter was granted in 1800.

Throughout its history, the Institution has supported public engagement with science through a programme of lectures, many of which continue today. The most famous of these are the annual Royal Institution Christmas Lectures, founded by Michael Faraday.

The Institution has had an instrumental role in the advance-ment of science since its founding. Notable scientists who have worked there include Sir Humphry Davy (who discovered sodium and potassium), Michael Faraday, James Dewar, Sir William Henry Bragg and Sir William Lawrence Bragg (who jointly won the Nobel Prize for their work on X-ray diffraction), Max Perutz, John Kendrew, Antony Hewish and George Por-ter. In the 19th century, Faraday carried out much of the re-search which laid the groundwork for the practical exploitation of electricity at the Royal Institution. In total, fifteen scientists attached to the Royal Institution have won Nobel Prizes. Ten chemical elements including sodium were discovered there, the electric generator was devised at the Institution, and much of the early work on the atomic structure of crystals was carried out within it.

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Royal Institution Albermarle Street W1S 4BS

Conference Guide - FPL 2015

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