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Algorithms and Implementation Platforms for Wireless Algorithms and Implementation Platforms for Wireless CommunicationsCommunicationsTLT-9706/ TKT-9636 (Seminar Course)TLT 9706/ TKT 9636 (Seminar Course)

BASICS OF FIELD PROGRAMMABLE BASICS OF FIELD PROGRAMMABLE GATE ARRAYSGATE ARRAYS

WaqarWaqar HussainHussainfirstname.lastname@tut.fifirstname.lastname@tut.fi

Department of Computer SystemsDepartment of Computer SystemsTampere University Tampere University of Technologyof Technology

LLecture Contentsecture Contents

1. Why there was a need for FPGA ?

2. What is the Scope of FPGA usability ?

3. How to Implement a Digital System ?

4. FPGA Architecture

5. The Unit of Structure of FPGA

6. Hardware Description Languages

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7. Synthesis / Place and Route

8. Timing, Area and Power Analysis

9. Future of FPGA Technology

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Why there was a need for FPGA ?Why there was a need for FPGA ?• Before Programmable Logic?

Fixed hardware = Fixed usability

Limited flexibility only possible by adding software support, forLimited flexibility only possible by adding software support, for example processors

Upgrade or alteration in hardware logic was not guaranteed

An upgrade meant a completely new system

• World’s First Programmable Logic Device (PLD) EP300: 320 Gates, 3-µm CMOS

10-MHz Performance, 20 I/O Pins

Desktop Programming

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Why there was a need for FPGA ?Why there was a need for FPGA ?

The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field programmable)

• World’s First FPGA with Embedded RAM in 1995• 100K Gates, 0.4 & 0.3 µm• >10M Transistors• 50-100 MHz Performance• First PCI Integration

World’s-FirstFPGA withEmbedded RAM

being programmed in batches in a factory or in the field (field programmable)

st C teg at o• First IP Partner Program

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Xilinx Co-Founders, Ross Freeman and Bernard Vonderschmitt, invented the first commercially available field programmable gate array in 1985 – the XC2064

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Why there was a need for FPGA ?Why there was a need for FPGA ?

• With FPGAso Reprogrammable Logic reusability

o Lower Non-Recurring Engineering (NRE) Cost

o Good for Prototyping

o Less Time to Market

o Can act as a testing device for other digital circuits

o Economical to be used for small volumes of products

o Students can understand digital design concepts in a better way by designing their custom logic

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What is the Scope of FPGA What is the Scope of FPGA usability ?usability ?

• Home Appliances

• Communication Systems• Communication Systems

• Control Systems and Automation

• Mechanical and Civil Engineering

• Test and Measurement Industry

• Medical Equipment

• Avionics and Aerospace Application

• Academia

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How to Implement a Digital How to Implement a Digital System ? System ?

orm

ance

SP Hardware

Per

fo

Flexibility

GPPDSP

HW/SW CO

ASP

SP Hardware

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Cos

ts

Design effort

GPPDSP

HW/SW

CO

ASP

FPGA ArchitectureFPGA Architecture• An Example of FPGA Prototyping Board

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FPGA FPGA InternalInternal ArchitectureArchitecture• The CLB exchange data using local

and global interconnects

• Local Interconnects >> GlobalInterconnects

• Other than CLBs the interconnects arealso programmable

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Basic Unit of FPGA Configurable Basic Unit of FPGA Configurable LogicLogic

The unit is“CLB” –Xilinx

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CLB Xilinx“LE” - Altera

(Example:Xilinx XC2000)

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Hardware Description Language Hardware Description Language • Can we use C as HDL?

Operations performed in a sequential order Help human's thinking process to develop anHelp human s thinking process to develop an

algorithm step by step Resemble the operation of a basic computer model

• Characteristics of digital hardware Connections of parts Concurrent operations Concurrent operations Concept of propagation delay and timing Characteristics cannot be captured by traditional PLs Require new languages: HDL

Modern HDLModern HDL• Capture Characteristics of a Digital Circuit

Entity & Connectivity

Concurrency & Timing

• Cover Description

In Gate Level and RT Level

In structural view and behavioral view

o Behavioral View Describe functionalities and I/O behavior

Treat the system as a black box

Corresponds to a sequential PLCorresponds to a sequential PL

o Structural View Describe the internal implementation (components and

interconnections)

Essentially block diagram

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Synthesis, Synthesis, PlacePlace and and RouteRoute• Accepts HDL description of a system (VHDL, Verilog)

• Quartus II (A Synthesis Tool) Flow Phases

1. Setup

2. Perform RTL Synthesis

3. Map basic gates into FPGA logic

4. Place the logic into specific location in chip

5. Route (connect) the logic elements together

6. Provide statistics and analysis results

7. Create a programming file and upload it into the FPGA

Synthesis, Synthesis, PlacePlace and and RouteRouteQuartusQuartus II design flow after simulated and verified II design flow after simulated and verified designdesign

Generic gate-level representation

Places and routes the logic into a device

Converts the post-fit netlist into a FPGA programming file

Analyzes and validates the timing performance of all logic in a design.

Run on FPGA

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Synthesis, Synthesis, PlacePlace and and RouteRouteRTL Synthesis StepRTL Synthesis Step

• Synthesis

user_logic.vhd

Creates basic gates and DFFs from HDL

o Result is so called netlist A full description of logical ports

and their connections

• Synthesis results can be

synth

viewed with RTL Viewer Tool

netlist (in RTL viewer)

Synthesis, Synthesis, PlacePlace and and RouteRouteTechnologyTechnology MappingMapping

gate-level netlist

x0

m1xx2

1

• Transforms the basic gates into technology specific components

• i.e. into logic elements (LE) with Altera FPGAs

• LE contains look-up table and DFF

same function with FPGA’s logic elements

x1

0

x2

x1m2

m6

z x0

map

DFF

LE

LE

LE

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Synthesis, Synthesis, PlacePlace and and RouteRoutePlacementPlacement

• Select which physical LE implement the user function

user function with FPGA’s logic elements

LE LE

• Selected LE should be close

to each other

to physical IO pins that they use

• Other logic may complicate placement

place

LE

FPGA

placement

other functions17

Synthesis, Synthesis, PlacePlace and and RouteRouteRoutingRouting

• Connects used LEs

together

to input/output pins

FPGA

• FPGAs have programmable routing switches

• Sometimes detours are needed

• Algorithmically complex operation

M t k hil ith bi May take a while with bigger systems

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Timing, Area and Power AnalysisTiming, Area and Power Analysis

• After placement and routing, Critical Path is determined

• Critical Path is the one which is offering longest propagationdelay on FPGA floory

comb logic

tclk period

tp,dff tsu,dfftp, comb

comb. logic

clk

Q D

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Timing, Area and Power AnalysisTiming, Area and Power AnalysisModelSimModelSim -- WaveformWaveform

multibit

high-freq signal

Monitored signals

Values at cursor Cursor line

Analog view of bus

multibit bus

1-bit signal

Time axis

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Timing, Area and Power AnalysisTiming, Area and Power Analysis

• It is important to analyze area utilization summary.

Design resources should not exceed FPGA resources

o Design can be synthesized optimally w.r.t area utilization if does not fit by normal synthesis

• More exchange of data between memory and processing elements means more switching between the transistor states therefore more power dissipation

Two Important factors for obtaining power estimate

o Accurate signal activityo Accurate signal activity

o Accurate power models Provided by the FPGA Vendor

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FutureFuture of FPGA of FPGA DevicesDevices

• FPGA device densities are increasing in millions of gates

• Altera’s latest device is Stratix-V

• Xilinx’s latest device is Virtex-7

• Higher density devices are expected with higher number of hard macros

FPGA are expected to stay in market for the next 50 years

• Research interests are growing more towards Coarse-grain

Reconfigurable Array (CGRA)

The unit of structure in FPGA is a LE whereas in CGRA, it is the ALU

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