A Novel Pipeline Architecture of Replacing Ink Drop Spread

Mohsen Firouzi, Saeed Bagheri Shouraki Electrical Engineering School, Artificial Creature Lab

Sharif University of Technology Tehran, Iran

mfirouzi@ee.sharif.edu, begheri-s@sharif.edu

Mahmoud Tabandeh1, Hamid Reza Mousavi2 Electrical Engineering School, DIS Lab1, ACL Lab2

Sharif University of Technology Tehran, Iran

tabandeh@sharif.edu, hamidreza@ee.sharif.edu

Abstract—Human Brain is one of the most wonderful and complex systems which is designed for ever; A huge complex network composed of neurons as tiny biological and chemical processors which are distributed and work together as a super parallel system to do control and vital activities of human body. Brain learning simulation and hardware implementation is one of the most interesting research areas in order to make artificial brain. One of the researches in this area is Active Learning Method in brief ALM. ALM is an adaptive recursive fuzzy learning algorithm based on brain functionality and specification which models a complex Multi Input Multi Output System as a fuzzy combination of Single Input Single Output Systems. ALM has a basic operator which is called Ink Drop Spread in brief IDS; this operator has a learning granularity concept to knowledge resolution tuning through learning process. Also IDS serves as processing engine for ALM which extracts main features of system subjected to modeling. Because of matrix like architecture of IDS, it is memory hungry and makes ALM slow. So an arithmetical form of IDS called Replacing IDS is presented in this paper with same functionality and better performance. Also in this paper we present a novel pipeline digital architecture of RIDS with high throughput and high speed learning process and simple hardware structure with more flexibility and scalability in comparison with another architectures. Finally an application benchmark is used for validation process.

Keywords- Pipeline Replacing Ink Drop Spread; Active Learning Method; Brain Learning Simulation; FPGA;

I. INTRODUCTION Thanks to continuous growth of fabrication technology

and digital system design techniques and architectures, today we can design high density digital systems on a single chip such as high speed Microprocessors, Digital Signal Processors, high density Neuro-Processors and etc with high performance truly following the Moor’s rule [1]. So today we can design and implement many algorithms as a digital system. Despite the enormous power of today computers and digital systems, we are encountering much limitation to model some real world intelligence such as brain functionality because of its unfamiliarity and rigorous complexity.

A lot of researches has already been done in the field of AI in order to brain learning simulation and functionality specification. but when looking closer there is no major breakthrough which has been accomplished yet in creating an Artificial Brain. One of the famous researches which has been done in Artificial Brain is CAM Brain Machine

developed by Hugo de Garis [2]. CBM comprises genetic algorithm as a powerful evolutionary computing tool and artificial neural networks as a computing system which imitates brain structure. It contains very large numbers of little artificial neural network structures which are connected together. Information is passed through ANN structures. ANNs is evolved in accordance with specified fitness criteria. To map a certain problem to CBM, it needs to cast this problem as a fitness function and CBM evolve a new ANN structure to solve the problem.

The main limitation of CBM seems to be the artificial way that an external observer has to set up the fitness criterion [3]. In other word, an external observer has to map the problem into a fitness function in order to evolve neural structures regarding to varying input. So not all learning problems are easily cast in this way. Also this approach is so expensive and just four of them have been built. In spite of limitation of the CBM, it is truly a good glance to AI researchers and a powerful reminder of the need for imagination of the mainstream AI community [3].

Tadashi Shibata tried to develop a novel multi-input single output analog element called neuron-MOSFET (neuMOS) in order to model single neuron. He developed a fabricated system by use of neuMOS to realize some brain functionality and associability [4]. This approach needs a complex fabrication process. Besides neuMOS has been developed just on base of classical neural model with analog input value and not compatible with real neural models which in form of spike time temporal dependency. So spike neural models cannot be implemented by this methodology.

ALM is another research which models some brain functionality on the base of some behavioral specification of brain. It appears that human brain confronts with real world complex problem with some hypotheses [5]:

a) Human extract system features by complex system breaking down into simpler and more comprehensible concepts.

b) Information obtained is of an outline nature and it is in form of image. It seems we process information through image data in our mind.

c) We human link multiple images of data together and try to obtain knowledge with a specified resolution.

d) If information not to be sufficient we try to acquire additional information and adjust our resolution granularly by breaking down overall systems in simpler concepts, either thickening most important

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concepts or thinning less important ones [6]; finally if condition is not mitted backward to step c.

The ALM was developed by Shouraki based on this set of hypotheses as a purpose of human brain learning simulation [7]; it has inherently a parallel structure and a granular learning concept which is served by IDS operator and input domain partitioning mechanism. In past decade many researches is accomplished to improve and modify this algorithm and to apply ALM in many applications such as control and system identification [8-11], robotic [9,12], soft computing and artificial intelligence [13-15], Genetic IDS [16], IDS Reinforcement Learning [17] and finally hardware implementation of this algorithm [18-22].

As purpose of brain hardware simulation Shouraki first offered a qualitative structure for ALM; it consists of several grid planes as IDS data planes which is covered by parallel structure of PCR photo resistors and LEDs [18]. Then he presented a quantitative digital structure; this digital approach is resource and memory hungry with time consuming learning process which make it inconvenient for real time applications especially for robotic applications. Therefore he offered an improved structure by use of analogue merged digital technology [19]. Major problem of analogue merged digital approach is in fabrication process; in spite of learning time improvement in analogue merged digital design; it is hard to design and implement.

Murakami developed a dedicated Digital hardware which is called “High Speed IDS, HIDS” in order to realize the real-time capability, noise robustness and fault tolerance of ALM. He has concerned about speed constraint of IDS for real time application so this approach is Memory hungry; moreover because of dedicated digital IDS plug in card structure which works as slave for a Host PC, it suffers from huge installation [20-21].

Tarkhan developed a novel structure for IDS by use of analog memory cells with one order of magnitude faster than Murakami’s digital structure but this methodology is hard to fabricate and has less flexibility and scalability in contrast with digital approach [22].

Here in this work we develop an effective pipeline digital architecture of arithmetical form of IDS operator (RIDS) with high throughput and high speed learning process in contrast with Murakami and Tarkhan’s architecture in order to knowledge expertness and system identification application. This novel architecture is easy to design and

evaluate and more flexible in contrast with Tarkhan’s analog design with faster learning time. In next section we will discuss about ALM precisely. In section III proposed approach is discussed in more detail and finally in section IV evaluation results of hardware resource and learning time for pipeline RIDS is presented.

II. ACTIVE LEARNING METHOD (ALM)

As we discussed before ALM is a Fuzzy recursive algorithm which tries to express a Multi-Input Multi-Output system as a Fuzzy combination of some simpler Single-Input Single-Output systems. This implies that a complex system is broken down into simpler concepts to acquire information in more comprehensible form. Each SISO systems are interpreted as xi-y grid planes which is called IDS unit consists of projected data points corresponding to interval domains of another input variables. In IDS units the points of xi-y data are shaded with IDS operator; it is like an Ink Drop which Spreads around each data point or in Fuzzy point of view the presence of data as a knowledge which is experienced, has a radial base membership function around the point of crisp data and provides none-precise information representation (Fig.6).

In Fig.1 a simple two-input single-output system is shown. If we segment each input domain in two regular Fuzzy intervals with membership function which is shown in Fig.2, there is overall four IDS units; x11: projected experienced data on x1-y plane corresponding to x2�[0,10], x12: projected experienced data on x1-y plane corresponding to x2�[10,20], x21: x2-y data plane corresponding to x1�[0,10] and finally x22: data plane of x2-y in accordance with x1�[10,20]. General structure of ALM is shown in Fig.3. In Fig.4 and Fig.5 data points of IDS units of x11 and x22 are shown; as we can see in some intervals of x1, x2 , data points is thinly scattered from elsewhere; it means correlation between output and corresponding input in those intervals which has large spread is less than intervals with small spread. So there is a knowledge in each IDS data plane which indicates how much output depends on input. This parameter is called Spread in ALM (σ parameter and β parameter as normalized spread in Fig.3) which is extracted by IDS operator and use in Fuzzy inference unit to extract system expertness. Large Spread in some intervals can become small with partitioning of other variables. This partitioning enlarges overall number of IDS units and fuzzy rules and enables system granularity concept beside IDS.

Figure 1. A simple two-input single-output system

Figure 2. Partitioning of input Domain

A21 A22

x2

A11 A12

x1

a11(x1)< a12(x1)

x2

x1

y

x1

x2

y

�

11 σ11�

12 σ12 �

21 σ21 �

22 σ22

x1-y Plane

x1-y Plane

x2-y Plane

x2-y Plane

a21(x2)> a22(x2)

a11(x1), a12(x1), a21(x1), a22(x1)

β11 � 11 or β12 �

12 or β21 �

21 or

β22 �

22

IDS Units Inference Layer

Learning

Input Layer Modeling Layer

Figure.3 Structure of 2-input 1-output ALM

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In the sequel, to achieve more accurate modeling, each input domain must be partitioned sufficiently which causes thin Spread area in IDS units. But if partitioning increased with no consideration on system error, it can make larger error especially when the number of data samples not to be enough. Murakami offers a constructive optimization algorithm to find optimum number of IDS regular partitioning structure [23]. In this algorithm a discrete boundary value has been defined for each variable and a constructive search algorithm are used to seek best result. Sagha offers an evolutionary algorithm for IDS optimized partitioning which has better performance than Murakami’s constructive algorithm [16]. In next subsection we will describe IDS operator functionality.

A. Ink Drop Spread Operator IDS is a curve fitting technique which can interpolate

data trajectory on a sparse experienced data plane; besides it is a knowledge extraction engine. When IDS is applied on each data point like an Ink Drop with radius R which spreads around each point, it generates two important features of data space, Narrow path and Spread. Narrow is interpolated data trajectory which is calculated by averaging operation on y values of each xi or Center of Gravity Defuzzification on each x (� in Fig.3). As discussed before Spread is a parameter that means dispersion around narrow and indicates effect of corresponding input in overall system output; this effect is related with reverse value of spread.

Murakami’s IDS Narrow and Spread implementation is as follow [14]:

Let’s , , , be the point on plane and , denotes darkness in , when IDS is applied at , , the darkness of its neighboring area increases. We can define this increase in darkness as bellow; also R denotes radius of ink through IDS operation: 1 , , (1)

, 00 (2)

Narrow path and spread are described as follows respectively: ∑ , ∑ , , (3)

| , 0 | , 0 (4) | , 0 : (5) ,

In Fig.6 IDS unit after applying IDS with calculated spread and narrow trajectory is shown. It is considerable that the size of Ink Drop pattern affects the model accuracy depending on training set size of ALM which indicates a knowledge granularity tuning concept [15]. It seems when number of experienced input data points are small, Ink Drop radius should be large to have a better interpolation on IDS plane and vice versa. In another word in some area which have less knowledge, large Ink Drop implies more imprecise of information.

From learning point of view ALM algorithm is a supervised online learning process whose the most time consuming section is applying IDS on a matrix mapped memory structure and average calculation for narrow path; also because of IDS matrix structure, memory cost increases when partition number increases too; so an alternative operator was developed called RIDS with same functionality and better performance and less memory usage [19]. In continue we will discuss about RIDS mechanism precisely.

B. Replacing Ink Drop Spread, RIDS RIDS is an arithmetical form of IDS with same

functionality and more accuracy in sparse data planes. Also instead matrix memory mapped structure, RIDS provides an effective memory digital structure. In RIDS all calculation could be done in two column memory structure for each coordinate in each data plane. There are two memory types for each IDS unit in this algorithm: main memory and image memory for intermediate calculation. Both main memory and image memory are equipped with averaging and resolution reduction Block; Fig.7 presents general structure of RIDS operation. Shouraki demonstrated that this structure reduces necessary memory resource seven times in comparison with classical IDS digital structure. Also running speed on similar data sets had shown that RIDS is faster than IDS in more than one order of magnitude algorithmically [19].

In Replacing algorithm two Euclidian adjacent values are replaced by mean value of both of them. Geometrically

Figure 4. Projected Data on IDS planes, - plane with 0,10

Figure 5. Projected Data on IDS planes, - plane with 10,20

Figure 6. IDS planes, after applying IDS

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1 1.5 2 2.5 3

1

1.5

2

2.5

3

3.5

4

4.5

5

experienced data1th iteration2th iteration3th iteration4th iteration10th iteration

Centerof

Gravity

1 2 3 4 5 6 7 8 9 100.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

Pattern Data4th Iteration of RIDSInterpolated

Region SpreadInformation

we prove here that RIDS converges on Center Of Gravity of experimental data patterns; in Fig.8 RIDS is applied on three adjacent points which are on each corner of triangle and we can see center of gravity of data points after 10 iteration. RIDS has not only ability of COG convergence but also it involves Spread feature of data patterns inside. Also in sparse data planes where knowledge extraction seems hard with IDS, RIDS can interpolate more data and model is more accurate in comparison with IDS. It is addressed in this paper that RIDS has more accurate results than IDS especially when IDS unit contains sparse data patterns. In addition proposed pipeline structure for RIDS unit makes learning time faster than other architectures for ALM and gives more flexibility and scalability.

As we can see in Fig.9 after four iteration of RIDS operation, data points are increased about 16 times and has converged to COG of data pattern; moreover in sparser region more data is interpolated and spread information is saved with illustrative accordion like shape which is shown in Fig.9. in another word when spread increases in some area, accordion like shape is made.

In the sequel RIDS has good ability of converging to COG of data pattern with spread component without matrix mapped memory structure and IDS operation; but with m iteration in RIDS data points increases 2m times where accuracy and memory resource can be affected. So a resolution reduction is applied as a stop condition. Resolution reduction in direction is done by replacing two LSB bits of coordinate values with 01 for main memory and 10 for image memory; in direction values those are related to a unique are averaged (Fig.7) [19].

After resolution reduction, mean of Y values in image memory corresponding to each x value presents Narrow trajectory for x and maximum of y values minus minimum of y values presents Spread value around Narrow. This formulation is similar to Murakami’s IDS operation and with same functionality [13]. In next section we can see that we add a neighborhood parameter to classic RIDS which enables better trajectory extraction for RIDS.

In inference layer of ALM, a Fuzzy inference unit applies narrow and spread values to generate a rule base to extract knowledge expertness exists in data samples of system. In the case of two-input single-output system with two partition as shown in Fig.2, the combination rule is written as follows:

R11: If x2 is A21, then y is Ψ11 R12: If x2 is A22, then y is Ψ12 R21: If x1 is A11, then y is Ψ21 R22: If x1 is A12, then y is Ψ22

(6)

y is β11Ψ11 or β12Ψ12 or β21Ψ21 or β22Ψ22 (7)

Where or is a union operator, and denotes the weight of th approximated narrow path for the th input variable. Also value of β is related to reverse value of spread and the degree of truth of the antecedent part of fuzzy rules.

III. PIPELINE REPLACING INK DROP SPREAD As we can see in Fig.7 in classical form of RIDS, one

replacing operation on source register bank or main memory could be done just in one clock cycle. Both main and image memory are equipped with averaging block. This averaging operation is most time consuming part of RIDS [18]. Shouraki offered an capacitive averaging circuit layer to overcome this drawback but this analogue structure is hard to fabricate and has no flexibility [18]. By consideration on independency of averaging operation on source registers, pipelining mechanism can increase total throughput and learning speed of ALM with RIDS operator without hardware resource increase and capacitive layer cost of IDS.

In Fig.10 system block of PRIDS for one coordination is shown. Tow column structure of memory: register bank A and B, are used as opposed to matrix map memory structure of IDS. Each averaging and replacing iteration is done between these register banks from a register bank to another one. A Finite State Machine controls the flow of PRIDS data path. In Fig.11 FSM control flow is shown. There are four states for PRIDS unit: Replacing from source registers A to destination registers B which is done as a pipeline operation; Replacing from B registers to A registers; Narrow and Spread calculation and Idle state. Each iteration is defined as a completion of averaging and replacing operation to the end of source register bank. At start of new iteration, position of destination register bank and source register bank is changed from A to B or vice versa.

Finally when replacing is accomplished, PRIDS is transferred to Narrow and Spread calculation state where the unit is awaiting for an enable signal to start finding spread

RAM X Main

Memory (Register)

RAM Y Main

Memory (Register)

RAM X’ Image

Memory (Register)

RAM Y’ Image

Memory (Register)

Mean for X of Consequent

Points

Mean for Y of Consequent

Points

Data Point Number > Threshold

Resolution Reduction

Yes

No No

Figure 7. General structure of RIDS Figure 8. Geometrical proof of Center Of Gravity convergence on RIDS

Figure 9. Data plane which is four iterated with RIDS operation

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and narrow information for specific input. On the base of IDS Narrow and Spread calculation mechanism, spread and narrow is calculated by same process in PRIDS. Spread is calculated by maximum and minimum difference of y values corresponding to a range of neighborhood area (parameter e in Fig.12) from input and Narrow can be calculated by averaging on same neighborhood of input too. Fig.12 shows a general RTL scheme of an efficient digital circuit for Narrow and Spread calculation unit. In this circuit if DFF3 reset to maximum value of y and DFF4 reset to minimum of y, these two flip flips hold down and up points of neighborhood area respectively to calculate spread. DFF1 enables an accumulator to calculate sum of y values which are in specified range of neighboring area of input x in order to narrow calculation.

In next section evaluation of proposed approach in comparison with another structures will be discussed.

IV. EVALUATION AND RESULTS For evaluation of proposed approach we implement

PRIDS design on ALTERA Cyclone II 2C35F672C6 FPGA device. This device is used in ALTERA DE2 board which provides some useful computer peripheral interface to develop many advanced digital designs using ALTERA Cyclone II device in order to evaluate digital designs [24]. In addition this board enables possibility of import data into device or read data from registers.

In learning phase, 10 uniform random set of input patterns are generated using (8). Each set contains specified number of data which is called training set size. System subjected to modeling is as bellow. Graph of this system is shown in Fig.13 [15]. , 2 3 , 1 , 10

(8)

First, we examined the processing speed and design resource usage of the single PRIDS unit with different level of pipeline. In Table I speed and resource parameters of PRIDS and classical RIDS are shown. Data width and address width of memory registers are set to 5 and 8 respectively and iteration is set to 3. Experimental results has shown that optimal value for iteration is three or four in some simulation in accordance with error. Mean learning time is calculated for random 10 different set of single IDS unit data points from an ALM modeling system of function (8) with 550 training set size and 8 regular partitions [15].

According to Table I when level of pipeline become larger, total resource such as number of logic elements and registers are used is enlarged and mean learning time become small; in other word concerning on time constraint expenses resource parameters. The optimal parameter for level of pipeline is about 5, the point where resource and timing diagram are met.

As we can see in table I the mean learning time per each data pattern for PRIDS with level of pipeline 5 is about 0.025 µs whereas learning time for each data pattern in

RST

~REPLACE_END_FLAG

IDLE

REPLACE A_to_B

REPLACE B_to_A

NARROW SPRAED Calculate

RST

RST

RST

~RST & EN

~REPLACE END FLAG

REPLACE_END_FLAG & END_FLAG

REPLACE_END_FLAG & END_FLAG

REPLACE_END_FLAG & ~END_FLAG

~RST

Figure 11. FSM Control Flow of PRIDS Digital System Block

+0

1Yk

0

X_IN-e < Xk < X_IN+e

1

0

1

0

IN < =DOWN_Y

IN OUT SUM

IN > =UP_Y

EN

DOWN_Y

+

UP_Y

1

-

/

COUNT

NARROW

SPREAD

Figure 12. General RTL scheme of Narrow and Spread calculation unit

DFF1

DFF2

DFF3

DFF4

MUX1

MUX2

MUX3

FSM Control Flow

RESET REPLACE_EN CLOCK END_FLAG

Figure 10. Proposed pipelined digital structure of RIDS, PRIDS

Narrow and Spread Calculation Unit

Source Register Address

Replacing Operation

STATUS NR_SP_EN

X_IN SP NR OUT_VALID

RST CLK

Register Bank A Register Bank B

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Murakami’s HIDS is about 5 µs [15] and in Tarkhans’s IDS analog structure is about 0.5 µs [22]. Also in Murakami’s structure with resolution of 256 for IDS units it is necessary to have 64Kbyte dedicated memory space [15] whereas because of column like structure for memory space in PRIDS it needs just about 7Kbyte memory space to have 8 bit resolution data width.

It is considerable that this design is more flexible and scalable in contrast with Plug In PCI-base HIDS and analog structure of Tarkhan’s approach. Scalability is an important characteristic for a system which can be used for different applications. In some applications maybe timing is more important like real time problems and in some, memory space limits system design.

As we discussed in this section the learning time of PRIDS can be more than one order of magnitude faster than Tarkhan’s structure and more than two order of magnitude faster than HIDS with less memory usage.

In order to verify the model accuracy, the error between the target function and the constructed model was measured using the fraction of variance unexplained (FVU) [15] which is defined as follow:

∑ ∑ (9)

Where xl is lth (l =1,2,..,L) input vector, denotes the output of a constructed model and 1/ ∑ .

The FVU is proportional to the mean squared error. As the model accuracy increases, the FVU approaches zero. The FVU values was calculated from 10000 points at regular intervals over the input domain. Let T1 and T2 be the sets of x1 and x2 coordinates respectively. The input vectors of the test set are described by the Cartesian product of T1 and T2, which are obtained from: . , 1,2,3, … ,100 , 1,2

(10)

Where c1 = 9 and c2 = 1 for the domain of (8). In Table II FVU error for proposed pipeline approach and

IDS are shown; iteration of PRIDS is 3 with pipeline level 5; Data width and address width are set to 5 and 8; also resolution of IDS units is set to 256 and Ink Drop is set to medium size equal to 9 [15].

It is illustrated from table II that if partitioning be enough even in small training set size, FVU in PRIDS is significantly less than IDS. Also it is clear that PRIDS has good ability to model subjected system especially in small training set size. Figure 14 shows the output surface of system for test set data which is modeled by PRIDS.

V. CONCLUTION In this paper we propose a novel pipeline digital structure

for RIDS, PRIDS. Through this approach learning time decreased more than one order of magnitude in contrast with former structures. It is addressed in this paper that, proposed approach has good ability to extract Spread and Narrow especially in sparse data planes with more flexibility and scalability and with less memory than IDS.

ACKNOWLEDGMENT With highest thanks of Mr. Dr Mahdi Shabani, Electrical

Engineering School, Sharif University of Technology who has encouraged first author to explore in Digital Design world with no fear and with high self confidence.

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TABLE II. FVU Error of system modeling for PRIDS approach in comparison with IDS with medium Ink Drop size (9) and different

training set number and different partitions

Number of Partitions

IDS vs. PRIDS

Training Set Size100 250 400 550

5 IDS 0.302 0.13 0.058 0.053

PRIDS 0.216 0.102 0.097 0.089

8 IDS 0.221 0.063 0.032 0.0276

PRIDS 0.207 0.071 0.0409 0.0228

12 IDS 0.421 0.066 0.0445 0.0201

PRIDS 0.089 0.0394 0.0318 0.016

TABLE I. PRIDS and Classical RIDS Resource and Timing Parameters

Level of Pipeline Classic RIDS 3 5 10

Total Logic Elements 795 2442 4024 6805

Total Registers 553 432 442 466

Max Frequency (MHz) 130.13 64.14 53.71 43.48

Worth Case delay (ns) 7.68 15.6 18.62 23

Mean Learning Time (µs) 5.79 1.82 1.33 0.805

Mean Learning Time per data pattern (ns)

115.8 37 25.57 14.48

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[21] M. Murakami and N. Honda, “Hardware for a new fuzzy-based modeling system and its redundancy,” Proceedings of the 23rd International Conference of NAFIPS, the North American Fuzzy Information Processing Society (NAFIPS’04), June 2004, pp. 599–604.

[22] Mahdi Tarkhan, Saeed Bagheri Shouraki, Seyed Hosein Khasteh, “A novel hardware implementation of IDS method”, Journal of IEICI Electronics Express, Vol.6, No.23, Dec 2009, pp 1626-1630.

[23] M. Murakami and N. Honda, “A fast structural optimization technique for IDS modeling,” Proceedings of the 26th International Conference of NAFIPS, the North American Fuzzy Information Processing Society (NAFIPS’07), June 2007, pp 204–20.

[24] ALTERA DE2 Board Reference Manual also Availabe on : http://ee.sharif.edu/~asic/Docs/DE2 Reference Manual.pdf

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Figure 13. Surface of (8) as system subjected to modeling

Figure 14. PRIDS model for 12 partition and 3 iteration, data width 5, address width 8 and 550

training data points, FVU = 0.016

Proceedings of the World Congress on Nature and Biologically Inspired Computing (NaBIC2010)

978-1-4244-7375-5/10/$26.00 2010 IEEE 133