Post on 16-May-2023
Department of Electronic Engineering
FINAL YEAR PROJECT REPORT
BEngECE-2006/07-<CHC>-<CHC-01-BEECE>
<Design of Radio Frequency Integrated
Circuit (RFIC)> Student Name: Chen Jiashu Student ID: Supervisor: Prof. Chi-Hou Chan Assessor: Dr. Xue Quan
Bachelor of Engineering (Honours) in Electronic and Communication Engineering (Full-time)
Student Final Year Project Declaration I have read the student handbook and I understand the meaning of academic dishonesty, in particular plagiarism and collusion. I declare that the work submitted for the final year project does not involve academic dishonesty. I give permission for my final year project work to be electronically scanned and if found to involve academic dishonesty, I am aware of the consequences as stated in the Student Handbook. Project Title : Design of Radio Frequency Integrated Circuit
Student Name : Chen Jiashu
Student ID:
Signature Chen Jiashu
Date : April 24, 2007
No part of this report may be reproduced, stored in a retrieval system, or transcribed in any form or by any means – electronic, mechanical, photocopying, recording or otherwise – without the prior written permission of City University of Hong Kong. _
Abstract
Design of Radio Frequency Integrated Circuit
Gilbert Mixer Design in 0.6μm BiCMOS Process
by
Chen Jiashu
Bachelor of Engineering ---- Department of Electronic Engineering
City University of Hong Kong
Recent years have seen a growing market demand for RFID (Radio Frequency
Identification) products. In order to provide compact hardware solution, RF front-ends
need to be implemented in integrated circuits or so called RFIC. One of the most
important components of the RF front-end architecture is the mixer, which is used for
frequency translation. Since RFID products must cope with signals of various power
levels, mixers must exhibit high linearity and wide dynamic range.
In this project, design of highly linear Gilbert cell active mixer is investigated. In
particular, a modified differential active bias is proposed to improve mixer linearity as
well as dynamic range. Effects of active bias technique are examined by comparing
performance of mixers using active bias with that of mixers using conventional bias.
I
Simulation results show a maximum 12dB improvement in input referred 1dB gain
compression point and a maximum 6.3dB improvement in output referred 1dB gain
compression point. Besides, the linearity and dynamic range improvement does not
incur significantly degraded noise performance. In addition, the active bias requires
no additional DC power while consumes little chip area.
II
TABLE OF CONTENTS
Abstract I List of Figures V List of Tables VII
Chapter 1 Introduction 1
1.1 Motivation 2 2.2 Organization of the report 2
Chapter 2 Mixer Fundamentals 3
2.1 Introduction 3 2.2 Mixer principles 5 2.3 Mixer performance criteria 6 2.3.1 Conversion gain 6 2.3.2 Linearity 7 2.3.3 Noise figure 9 2.3.4 Port-to-port isolation 10 2.4 Single-balanced mixers 10 2.5 Double-balanced mixers 15
Chapter 3 BiCMOS Gilbert Mixer Design 18
3.1 Introduction 18 3.2 Basic design issues 19 3.2.1 Gilbert mixer circuit 19 3.2.2 Design guidelines 20 3.2.3 Matching network 23 3.3 Mixer I 23 3.4 Active bias 28 3.5 Mixer II 30 3.6 Performance comparison between Mixer and Mixer II 33 3.7 Modification to conventional mixer design 38 3.8 Mixer III 39 3.9 Mixer IV 43 3.10 Performance comparison of the four designs 47 3.11 Summary 51
III
Chapter 4 Mixer Layout 53
4.1 Introduction 53 4.2 Resistor layout 54 4.3 Capacitor layout 55 4.4 Bipolar transistor layout 56 4.5 CMOS layout 58 4.6 RF pad layout 61 4.7 Layout of the four mixers 62 4.8 Physical verification 64 4.9 Conclusion 65
Chapter 5 Mixer Testing 66
5.1 Introduction 66 5.2 Testing board 66 5.3 Wire bonding 68 5.4 Testing results 69
Chapter 6 Conclusion 70
Reference 72
Acknowledgement 75
IV
LIST OF FIGURES
Figure 2.1 Illustration of the mixer function 2 Figure 2.2 Structure of conventional superheterodyne radio receiver 4 Figure 2.3 Illustration of P1dB and OIP3 8 Figure 2.4 Single-Side Band mixing 9 Figure 2.5 Double-Side Band mixing 10 Figure 2.6 Single-balanced mixer I 11 Figure 2.7 Single-balanced mixer II 12 Figure 2.8 Source degeneration 14 Figure 2.9 Double-balanced mixer (Gilbert cell mixer) 15 Figure 2.10 Degenerated Gilbert cell mixer 16 Figure 3.1 Basic configuration of a Gilbert mixer 20 Figure 3.2 Mixer core 22 Figure 3.3 Schematic diagram of Mixer I 24 Figure 3.4 Matching network of Mixer I 25 Figure 3.5 IF load termination 25 Figure 3.6 S parameters of Mixer I 26 Figure 3.7 Power conversion gain and input P1dB of Mixer I 26 Figure 3.8 Noise figure of Mixer I 27 Figure 3.9 Active bias 28 Figure 3.10 Modified active bias for double-balanced mixers 29 Figure 3.11 Schematic diagram of Mixer II 30 Figure 3.12 Matching network of Mixer II 31 Figure 3.13 S parameters of Mixer II 32 Figure 3.14 Power conversion gain and input P1dB of Mixer II 32 Figure 3.15 Noise figure of Mixer II 33 Figure 3.16 Gain compression versus RF input power 34 Figure 3.17 Gain compression versus IF output power 34 Figure 3.18 Vbe versus IF output power 37 Figure 3.19 Ic versus IF output power 37 Figure 3.20 Schematic diagram of Mixer III 40 Figure 3.21 Matching network of Mixer III 41 Figure 3.22 S parameters of Mixer III 42 Figure 3.23 Power conversion gain and input P1dB of Mixer III 42 Figure 3.24 Noise figure of Mixer III 42 Figure 3.25 Schematic diagram of Mixer IV 44 Figure 3.26 Matching network of Mixer IV 45 Figure 3.27 S parameters of Mixer IV 45 Figure 3.28 Power conversion gain and input P1dB of Mixer IV 46 Figure 3.29 Noise figure of Mixer IV 46 Figure 3.30 Gain compression versus RF input power (4 mixers) 49
V
Figure 3.31 Gain compression versus IF output power (4 mixers) 49 Figure 3.32 Vbe versus IF output power (4 mixers) 50 Figure 3.33 Ic versus IF output power (4 mixers) 50 Figure 4.1 Layout of a rpoly resistor 54 Figure 4.2 Layout of a rxbase resistor 55 Figure 4.3 Layout of a mimc capacitor 56 Figure 4.4 Layout of a qnb4sa transistor with emitter length unit 2 57 Figure 4.5 Layout of a qnb4sa transistor with emitter length unit 16 58 Figure 4.6 Layout of a noms4 MOSFET with single gate 59 Figure 4.7 Layout of a noms4 MOSFET with 10 gates 60 Figure 4.8 Layout of a current mirror formed by two nmos4 MOSFETs 60 Figure 4.9 Layout of a RF signal pad 61 Figure 4.10 Layout of Mixer I 62 Figure 4.11 Layout of Mixer II 62 Figure 4.12 Layout of Mixer III 63 Figure 4.13 Layout of Mixer IV 63 Figure 5.1 Testing board layout 67 Figure 5.2 Testing board 67 Figure 5.3 Wedge bonding and ball bonding 68 Figure 5.4 KNS wedge bonder 69
VI
LIST OF TABLES
Table 3.1 Key components summary of Mixer I 24 Table 3.2 Performance summary of Mixer I 27 Table 3.3 Performance summary of Mixer II 33 Table 3.4 Performance comparison of Mixer I and Mixer II 38 Table 3.5 Performance summary of Mixer III 43 Table 3.6 Performance summary of Mixer IV 47 Table 3.7 Performance comparison of the four mixers 51
VII
Chapter 1
Introduction
1.1 Motivation
Recent years have seen a growing market demand for Radio Frequency Identification
(RFID) products. Researches aimed to provide reliable RFID techniques are widely
carried out. One of such project is CityU’s development of a total RFID solution
encompassing both hardware and software R&D supported by a large grant from the
Hong Kong government. In order to achieve efficient and reliable signal transmission,
a highly linear and low noise RF receiver front-end is required. One of the key
components is the mixer which converts incoming radio frequency signals into
intermediate frequency signals that can be processed by the DSP chip. In order to
translate incoming signals of very different power levels, the mixer must be designed
to exhibit wide dynamic range and high linearity. Besides, low power consumption
and low noise is also important concerns of the design. To meet the market demand of
high integrity and small size, mixers are implemented in RFICs based on 0.6μm
1
BiCMOS process.
1.2 Organization of the report
In this report, basic techniques of designing a Gilbert cell mixer using 0.6μm
BiCMOS technology are addressed. Besides, an active bias technique [1] which was
originally used in power amplifier designs is modified and incorporated in Gilbert cell
mixers in order to improve the mixer linearity. Chapter 2 presents the fundamental
mixing theories, including various types of active mixers that are commonly used.
Chapter 3 presents the major design work of this project. First, the basic design
process is addressed and a prototype mixer is demonstrated. Next, the active bias
technique is explained and modified for Gilbert cell mixers. Simulation results and
improvement are discussed. Then, current mirror is removed from the conventional
Gilbert cell so as to optimize the effect of active bias. Subsequently, two more mixers
are designed, one using conventional bias while the other using active bias. Again,
simulation results and further improvement are discussed. Chapter 4 presents the
layout design procedures and physical verification processes which comprises DRC
and LVS. Chapter 5 talks about testing issues such as testing board design and wire
bonding technique. The final chapter, Chapter 6, concludes the whole projects with
possible future work.
2
Chapter 2
Mixer Fundamentals
2.1 Introduction
In RF front-end structures, mixer is the building block that accepts two different input
frequencies and presents a mixture of signals at several frequencies, among which, the
sum and the difference of the two input frequencies are the desired outputs in upper
conversion and down conversion processes respectively. As a result, mixers translate
intermediate frequency signal into radio frequency signal are called up converters
while mixers translate radio frequency signals into intermediate frequency signals are
called down converters. Figure 2.1 illustrates the input-output relation of up
converters and down converters. Although linearity and time invariance are the usual
assumption and the desired condition during circuit analysis, the performance of RF
front-ends actually depends on the mixer, a critical component that fails to obey the
above LTI assumption. [2]
3
Figure 2.1 Illustration of the mixer function
One of the oldest mixer applications is the superheterodyne receiver where mixers
shift all the incoming signals down to intermediate frequencies which are in turned
passed on by tuned circuits, amplified, and then demodulated to recover the original
signal. Thus instead of changing a number of component values in order to locate the
desired input frequency, one only needs to change the local oscillator frequency. This
architecture presents a number of advantages in terms of selectivity and simplicity
which is the reason why such structure are still active nearly 70 years after its birth. A
structure of the superheterodyne radio is shown in Figure 2.2.
Figure 2.2 Structure of conventional superheterodyne radio receiver
4
2.2 Mixer principles
Presently, almost all mixers operate on the principle of signal multiplication in time
domain. Mathematically, it can be expressed as follows:
1 2 1 2 1cos( ) cos( ) [cos( ) cos( ) ]2
AB2A t B t t tω ω ω ω ω ω= − + + (2.1)
Multiplication results in two different frequency signals: the sum and the difference of
the input frequencies. For a down converter, the output signal can be expressed as
follows:
( ) cos( ( )) cos( )( ) {cos[( ) ( )] cos[( ) ( )]}2
out RF RF LO LO
RF LORF LO RF LO
V A t t t A tA t A t t t t
ω ϕ ω
ω ω ϕ ω ω ϕ
= + ×
= + + + − +
(2.2)
By filtering the undesired frequency signal, which is the sum signal in this case, the
intermediate frequency signal can be extracted. Usually, the LO signal is kept constant,
therefore, the variation of RF signal which carries certain modulation is proportionally
translated into the IF output. However, undesired frequency translation will also occur
based on the same multiplication principle, resulting in inter-modulation products
which interfere with the actual signal and in turn deteriorate the linearity. This will be
further discussed later.
5
2.3 Mixer performance criteria
2.3.1 Conversion gain
Conversion gain can refer to either voltage conversion gain or power conversion.
Voltage conversion gain is defined as the ratio of the output IF voltage to the input RF
voltage whereas power conversion gain is defined as the ratio of the output IF signal
power to the input RF signal power.
Active mixers can achieve power conversion gain greater than unity, i.e. greater than
0 dB, since they convert DC power into IF power. Passive mixers, on the other hand,
can hardly achieve power conversion since they do not require any DC power supply.
An exception is the parametric mixer which converts LO power into IF power through
reactive nonlinear process. Yet voltage conversion gain are usually much easier to
obtain.
Conversion gain greater than 0 dB is usually desirable for active mixers, for mixers
then not only performs frequency translation, but also provide certain degree of
amplification.
6
2.3.2 Linearity
Linearity means the output signals increases proportionally as the input signal
increases. Similar to power amplifiers, large RF input signal will results in significant
nonlinear effects so that the IF signal is no longer proportional to the RF signal.
Several criteria are dedicated to interpret linearity. One of the most important criterion
is the 1 dB gain compression point, where the output IF value is 1 dB less than it
should have been if the mixer is ideally linear. Usually, P1dB refers to the output IF
power at which level gain compression reaches 1 dB. It can also be denoted as output
referred P1dB. Similarly, input referred P1dB refers to the input RF power at which
level gain compression reaches 1 dB.
Another commonly used criterion to measure the mixer linearity is the two-tone third
order intercept. It is based on the idea that the device non-linearity can be modeled by
a low order polynomial, derived by means of Taylor series expansion. The third order
intercept point relates nonlinear products caused by the 3rd order term in the
non-linearity to the linearly amplified and mixed signal. The two-tone test mimic the
real receiver environment where both a desired signal and a potential interferer with
very close frequency are fed into the mixer. Ideally, the signal and the interferer
should be frequency converted separately, resulting in separate IF output. Yet this
never happens. The intermodulation effect will result in IM products with frequencies
7
of 12 RF RF 2ω ω± and 22 RF RF1ω ω± . If it happens that the two frequencies are very
close to each other, the difference products will fall in the range of IF passband and
cannot be distinguished.
In order to obtain the third order intercept point, we plot the output power versus the
input power on the dB scale. Two curves are drawn, one for the fundamental signal at
an input tone frequency, one for the third order intermodulation product. As a result of
logarithmic plot, the fundamental signal will exhibit a slope of 1 while the third order
intermodulation product will exhibit a slope of 3. A theoretical intercept point can be
found by extending the two curves.
P1dB and third order intercept point are illustrated in Figure 2.3.
Figure 2.3 Illustration of P1dB and OIP3
8
2.3.3 Noise figure
Noise Figure (NF) measures how much the signal to noise ratio (SNR) degrades when
the signal pass through the mixer. It is defined as the ratio of the input SNR to the
output SNR.
Noise Figure = 10log( )in
out
SNRSNR
Since the mixer generates both sum and difference of the input frequencies, two input
frequencies can contribute to the same IF frequency. One is LO RFω ω+ and the other
is LO RFω ω− and they are commonly referred to as sidebands. Under the usual
circumstances where the desired RF signal exists in only one of the bands, the noise
figure measured is called Single-Side Band (SSB) NF. Under other circumstances
where the desired RF signal exists in both upper and lower sidebands, the noise figure
is called Double-Side Band (DSB) NF. SSB NF is usually 3 dB larger than DSB NF
since the SSB signal power is one half of the DSB signal power while the IF noise
outputs are the same. The concepts of SSB and DSB are illustrated in Figure 2.4 and
Figure 2.5.
Figure 2.4 Single-Side Band mixing
9
Figure 2.5 Double-Side Band mixing
2.3.4 Port-to-port isolation
Isolation is defined as the amount of feed-through of RF and LO signals to the desired
output IF band. Forward feed-through is generally undesirable since the large LO
power will cause problems to signal processing in the later stages. Reverse isolation is
also important so as to prevent the LO power from entering the RF port, otherwise,
the strong LO signal will be radiated by the antenna and causes interference. In a
word, it is generally desirable to achieve good isolation among all three ports of the
mixer. Isolation of 30-50 dB is considered as adequate for most of the communication
systems.
2.4 Single-balanced mixers
Generally, mixers can be categorized as passive and active mixers. Active mixers,
which requires internal dc power supply, can in turn be classified as single-balanced
mixers or double-balanced mixers, according to circuit configurations.
10
As one of the common families of multiplication based mixers, single balanced
mixers are constructed by three stages. As shown in Figure 2.6, the first stage is called
the RF transconductance stage which converts the incoming RF voltage signal into
current signal. This can be achieved by a common-source or an emitter-follower
amplifier configuration. The second stage is the switch stage. It comprises two
identical transistors which are connected to the different LO signals respectively. The
last stage is the output stage. Switching transistors are terminated with a resistive load,
or sometimes a tunable RLC tank and output voltages are taken across the load.
Figure 2.6 Single-balanced mixer I
In order to derive the output IF voltage, we replace the transconductance stage with a
current source as shown in Figure 2.7. The value of the current source is
( )BIAS m RFI g V t+ . LO signals are chosen large enough (usually about 0 dBm) to ensure
the rapid switch. As a result, the current commute from one side to the other at the LO
frequency. Thus the output current is equal to:
11
sgn[cos( )][ ( )]out LO BIAS m RFI t I g V tω= + (2.3)
Expanding the sgn[] function with Fourier decomposition,
1
sin( )4 2( ) [ cos( )][ ( )]
4 1[cos( ) cos(3 ) ][ ( )]3
out LO BIAS m RFk
LO LO BIAS m RF
kI t k t I
k
t t I g V
g V t
t
π
ωπ
ω ωπ
∞
=
= +
= − + +
∑ (2.4)
Then the output IF voltage can be determined,
1
( ) ( )
sin( )4 2[ cos( )] [ ( )]
4 1[cos( ) cos(3 ) ][ ( )]3
out out L
LO L BIAS m RFk
LO LO BIAS m RF L
V t I t R
kk t R I g V t
k
t t I g V
π
ωπ
ω ω t Rπ
∞
=
= ×
= +
= − + +
∑ (2.5)
Expanding the first cosine term we get,
4 cos( ) [ ( )]
2 4{cos[( ) ] cos[( ) ]} cos( )
LO L BIAS m RF
m L RF LO RF LO LO L BIAS
t R I g V t
g R t t t R I
ωπ
ω ω ω ω ωπ π
× +
= + + − + (2.6)
Figure 2.7 Single-balanced mixer II
12
Apart from the sum and difference terms, odd harmonics of the LO mixing with the
RF signal are also present in the output frequency spectrum. In addition, odd
harmonics of LO are also generated as a direct result of multiplying the DC bias
current and the LO harmonics. Although single-balanced mixers offer advantages of
simple configuration and low noise, its inefficient frequency translation is undesired.
This led to the invention of double-balanced mixers which are carefully designed to
remove the LO harmonics at the output.
It is important to note that during the derivation of output voltage, assumption was
made that the transconductance stage provides a perfect voltage to current conversion.
However, it never happens. As a consequence, an important task of mixer designs is to
linearize the transconductance stage. Conventionally, source degeneration methods
are adopted to improve the mixer linearity. Figure 2.8 shows two most commonly
used source degeneration: resistive degeneration and inductive degeneration.
13
Figure 2.8 Source degeneration
Of the two degeneration methods, inductive approach is more preferable. One reason
is that unlike resistors which contribute large thermal noise to the mixer, perfect
inductors do not add any thermal noise. Besides, there is no DC voltage drop over
inductors and therefore voltage headroom can be maximized. In addition, it can be
seen from the Volterra analysis that the inductive degeneration will result in a negative
reactance which partially cancels out the imaginary part of the IMD3 product, leading
to better linearity. [3] However, the most significant drawback of the inductive
approach is the fact that inductors usually occupy huge chip area. This is not desirable
since IC designers nowadays are trying hard to reduce cost by minimizing the chip
area. Apart from the above two degeneration methods, capacitive degeneration was
also attempted. Yet due to its inferior performance in terms of linearity and noise, it is
rarely found in mixer designs.
14
2.5 Double-balanced mixers
In order to remove the undesired LO harmonics at the output, two single-balanced
mixers can be combined to produce a double-balanced mixer as shown in Figure 2.9.
This type of mixers is commonly referred to as Gilbert cell mixer or Gilbert type
mixer.
Figure 2.9 Double-balanced mixer (Gilbert cell mixer)
It can be noted from the circuit configuration that the two single-balanced mixers are
connected in anti-parallel as far as the LO different input is concerned but in parallel
as far as the RF input is concerned. The output stages of the two single-balanced
mixers are connected in a manner that the DC bias current is effectively cancelled out.
The output voltage can be derived as follows,
15
sgn[cos( )] [ ( )] sgn[cos( )] [ ( )]2sgn[cos( )] ( )
out LO L BIAS m RF LO L BIAS m RF
LO L m RF
V t R I g V t t R I g V tt R g V tω ω
ω= + −
=−
(2.7)
Expanding the sgn[] function with Fourier decomposition,
1
sin( )4 2( ) [ cos( )]2 ( )
4 1[cos( ) cos(3 ) ]2 ( )3
out LO L m RFk
LO LO L m RF
kV t k t R g V t
k
t t R g V t
π
ωπ
ω ωπ
∞
=
=
= − +
∑ (2.8)
Expanding the first cosine term we get,
4 cos( ) 2 ( )
4 4cos[( ) ( )] cos[( ) ( )]
LO L m RF
L m RF LO L m RF LO
t R g V t
R g t t R g
ωπ
ω ω ϕ ω ω ϕπ π
×
= + + + − t t+ (2.9)
Similar to single-balanced mixers, the linearity of double-balanced mixers is also
determined by the RF transconductance stage and source degeneration methods also
apply. Figure 2.10 shows a degenerated Gilbert cell mixer.
Figure 2.10 Degenerated Gilbert cell mixer
16
The noise figure of active mixers is usually very large when compared to other RF
front-end components. Several factors contribute the large noise figure. First, the
imperfect switching causes attenuation of the signal. Second, noise is generated when
both switching transistors are ON. Third, ignoring either the sum or the difference IF
signal at the output results in an unavoidable 3 dB loss. Hence, mixer noise figures are
in the range of 7-15 dB.
17
Chapter 3
BiCMOS Gilbert Mixer Design
3.1 Introduction
In this chapter, a total of four different down conversion mixer designs are to be
presented. Mixers are expected to convert RF frequency of 900MHz to IF frequency
of 100MHz, with the mixing of 1GHz LO signal. All four mixers are designed based
on 0.6μm BiCMOS process provided by X-FAB Foundry. First, the basic Gilbert cell
mixer design procedure is explained and a basic mixer is designed according to the
guidelines. Next, a modified active bias technique is proposed to improve the mixer
linearity. Then, current mirror is removed from the conventional Gilbert cell so as to
optimize the effect of active bias. Subsequently, two more mixers are designed, one
using conventional bias while the other using active bias. Further linearity
improvement is observed and results are discussed.
18
3.2 Basic design issues
3.2.1 Gilbert mixer circuit
As shown in Figure 3.1, a typical Gilbert mixer circuit consists of three major parts:
the Gilbert cell or equivalently the mixer core, the bias network and the current mirror.
As explained in Chapter 2, the mixer core performs the major function of frequency
conversion [4]. Here two resistors are added as source degeneration in order to
achieve reasonable dynamic range and linearity. However, as a result of adding
resistors, we can expect that the noise figure will increase. The bias network provides
the DC voltage bias for RF transcondutance transistors as well as LO switching
transistors. In addition, it controls the reference current of the current mirror.
Conventional Gilbert mixer designs usually incorporate current mirrors, which can
easily control the total current consumption by simply adjusting the transistor pair size
ratio. For example, if the reference current Ids1=0.1mA and the transistor gate width
ratio is w2/w1= 10:1, the Ids2 is equal to 10Ids1=1mA. Besides, the current mirror can
effectively balance the two differential branches of the mixer core.
19
Figure 3.1 Basic configuration of a Gilbert mixer
3.2.2 Design guidelines
As shown in Figure 3.2, the mixer core comprises 2 transconductance transistors
TxRF, 4 switching transistors TxLO, 4 bias resistors Rtx, 2 degeneration resistors Rs
and 2 load resistors RL. The choice of these components is of great importance as
they largely determine the whole mixer performance.
In order to achieve high linearity, transistors with small base-emitter resistance should
20
be chosen for TxRF. Meanwhile it is found that increasing the emitter unit area
improves the linearity and noise [5]. Meanwhile, the four switches should be small
transistors in order to ensure fast switching. Otherwise, the interval during which both
transistors are ON introduces flicker noise [6].
From Equation 2.9, we notice that the voltage conversion gain is directly proportional
to RL. Therefore we should maximize RL as far as voltage conversion gain is
concerned. However, there must be an upper limit for the value of RL, since large RL
consumes all the voltage headroom and drives switching transistors TxLO into the
saturation region.
The value of the degeneration resistors is designed to achieve a trade-off between
dynamic range and noise. Too large resistance significantly increases the noise figure,
yet too small resistance does not improve much the input 1 dB gain compression point.
The reason of not using inductive degeneration is that the inductors are so large in
size that one inductor is already bigger than a complete mixer.
Bias resistors Rtx should be large enough to prevent high frequency signals from
entering into the bias network. Alternatively, they can be viewed as RF chokes.
21
Figure 3.2 Mixer core
In general, mixers should not consume too large power. Bias currents are often found
in the range of 1mA to 7mA for down conversion mixers. The total bias current can be
controlled by the current mirror.
Moreover, power consumption in bias network is generally undesirable. Hence we try
to minimize the current in the bias network by choosing large bias resistors. The ratio
between the current consumed in the mixer core and that consumed in the bias
network is around 20:1.
22
3.2.3 Matching network
In order to achieve maximum power transfer, especially at RF input port and IF output
port, impedance matching networks are indispensable. However, as far as 900 MHz
circuits are concerned, matching networks are impractical to be implemented on chip.
This is because either very limited L component values can be found in the foundry
library and inductors are extremely large if we use LC components as matching
networks or quarter-wave transmission lines for 900MHz are way too lengthy if we
use transmission lines as matching networks. As a result, all the matching networks
are implemented off chip. In fact, a testing board will be designed at a later stage for
the purpose of testing where lumped matching components can be mounted.
3.3 Mixer I
Here we propose the first design, Mixer I, which is optimized according to the above
design rule of thumb. Figure 3.3 shows the schematic diagram of Mixer I.
23
The components properties are summarized in Table 3.1
On chip component Property (Value) TxRF Qnb4sa (Emitter Unit: 16) TxLO Qnb4sa (Emitter Unit: 2) RL 500 ohm Rs 100 ohm Rtx 5k ohm
Table 3.1 Key components summary of Mixer I
Figure 3.3 Schematic diagram of Mixer I
Figure 3.4 shows the matching network for RF and LO ports of Mixer I. As for the IF
port, only a resistor is needed since the output impedance is almost pure real at
100MHz. Hence, LC matching is not necessary. Figure 3.5 shows the load termination
24
of the two IF ports. Each of them is terminated by a matched load of 560 ohm and the
total output power is the sum of the two.
Figure 3.6 shows the S11, S22 and S33 for the three ports. The return losses of all
three ports are less than –10dB, which indicates good matching condition.
Figure 3.4 Matching network of Mixer I
Figure 3.5 IF load termination
25
Figure 3.6 S parameters of Mixer I
Next, we present the simulation results of Mixer I. Figure 3.7 shows the power
conversion gain versus RF input power plot and the gain compression versus RF input
power plot while Figure 3.8 shows the noise figure of Mixer I at different noise
frequencies. Finally, the complete performance summary of Mixer I is presented in
Table 3.2.
Figure 3.7 Power conversion gain and input P1dB of Mixer I
26
Figure 3.8 Noise figure of Mixer I
Mixer I Power conversion gain (dB) 10.8 Input P1dB (dBm) -13.8 Output P1dB (dBm) -4 Noise figure @ 100MHz (dB) 7.9 RF-LO Isolation (dB) <-300 LO-IF Isolation (dB) <-300 Mixer core bias current (mA) 5.8 Total current (mA) 6 DC supply (V) 5 Power consumption (mW) 30
Table 3.2 Performance summary of Mixer I
27
3.4 Active bias
Active bias network or sometimes so-called Linearizer was originally proposed for
power amplifier linearization.[7][8][9] In contrast to conventional passive bias
network which only uses resistors, active bias network uses transistors and capacitors
as voltage and current compensation elements. Figure 3.9 shows several
configurations of active bias.
Figure 3.9 Active bias
It is well known that the transconductance stage causes non-linearity during large
signal amplification. [10] The base-emitter voltage drops when the RF input power
increases, leading to decreased collector current. The active bias transistor, however,
stabilizes the base-emitter voltage and supplies additional current into the
amplification transistor. Several advantages are offered by this technique:
1. Effective improvement of gain compression and phase distortion
2. No additional power consumption
3. Little increase in chip area
28
As mixer transconductance stages are very similar to amplifiers, we here propose a
modified version of active bias (b) which serves to provide bias for the
transconductance transistors TxRF as well as to linearize the mixer input-output
characteristics. The proposed active bias for double-balanced mixers is shown in
Figure 3.10
Figure 3.10 Modified active bias for double-balanced mixers
The modified active bias network consists of two transistor-capacitor pairs and 5 large
resistors which provide the voltage bias for compensation transistors Txc as well as
LO switches. When the RF input power increases, a portion of the RF power will leak
into the bias branch, causing base-emitter voltage of Txc to drop. As most of the RF
power are shunted to ground by Cb, point A is kept at a relatively constant voltage. As
a result, the Vbe drop of Txc compensates the Vbe drop of TxRF and the latter will not
decrease significantly.
29
3.5 Mixer II
Based on the above technique, we design a new mixer, Mixer II, which uses active
bias network. The schematic diagram of Mixer II is shown in Figure 3.11.
Figure 3.11 Schematic diagram of Mixer II
In order to make performance comparison between Mixer I and Mixer II so as to
examine the effect of the newly proposed active bias network, all the rest components
are kept the same as Mixer I. Compensation transistors are chosen to be identical to
the transconducatance transistors but with a multiplier of 2. Capacitance is optimized
to be 6pF.
Figure 3.12 shows the matching network of Mixer II.
30
Figure 3.12 Matching network of Mixer II
Figure 3.13 shows S11, S22, S33 of Mixer II. The return losses of all three ports are
less than –10dB.
31
Figure 3.13 S parameters of Mixer II
Next, the simulation results are plotted below. Figure 3.12 shows the power
conversion gain versus RF input power curve and the gain compression versus RF
input power curve. Figure 3.13 shows the noise figure of Mixer II.
Figure 3.14 Power conversion gain and input P1dB of Mixer II
32
Figure 3.15 Noise Figure of Mixer II
The complete performance is summarized in Table 3.3
Mixer II Power conversion gain (dB) 3.3 Input P1dB (dBm) -3 Output P1dB (dBm) -0.7 Noise figure @ 100MHz (dB) 7.5 RF-LO Isolation (dB) <-300 LO-IF Isolation (dB) <-300 Mixer core bias current (mA) 5.7 Total current (mA) 6 DC supply (V) 5 Power consumption (mW) 30
Table 3.3 Performance summary of Mixer II
3.6 Performance comparison between Mixer I and Mixer II
33
Figure 3.16 Gain compression versus RF input power
Figure 3.17 Gain compression versus IF output power
34
Figure 3.16 plots the gain compression curves of Mixer I and Mixer II versus the RF
input power. The active bias technique effectively improves the input referred 1dB
gain compression point by 10.8dB. As input P1dB is a direct indicator of the mixer
dynamic range, the proposed active bias significantly improves the mixer dynamic
range. However, it is important to note that the active bias introduces certain amount
of insertion loss and gain is reduced by 7.5dB. Taking into of the gain reduction, we
now plot the gain compression curve against the mixer output power in Figure 3.17,
from which we conclude that the active bias improves the output referred 1dB
compression point by 3.3 dB.
A common misconception is that improvement of input referred P1dB means
improvement of linearity. This is fallacious in that it does not take into account of the
power conversion gain. Improvement of input P1dB of any system can be a direct
result of reducing the system gain. For instance, if the maximum output power of a
transistor is 10dBm and the gain is 10dB, the input P1dB is 0dB. However, if we
somehow reduce the gain to only 5dB, the input P1dB point will be pushed to 5dBm,
leading to spurious linearity improvement of 5dB. But the transistor output saturation
point is still 10dBm, which means you can still only use the transistor up to 10dBm
and linearity is not improved at all. In fact, reducing gain can be easily achieved by an
attenuator which is almost costless. Hence, a proper indicator of linearity should be
the output referred P1dB.
35
In light of the above statement, we conclude that the active bias can improve the
mixer linearity by 3.3 dB up to this moment.
Moreover, it is found that the active bias provides several benefits:
First, it provides a period of gain expansion as the RF input power increases. This can
be observed from Figure 3.17. Instead of compressing, the gain starts to increase
when the input power reaches about –28dBm. It does not drop until it passes a peak at
the input power of –10dBm. This phenomenon directly contributes to the
improvement of gain compression point.
Second, it stabilizes the base-emitter junction voltage (Vbe) of the transconductance
transistor. Figure 3.18 plots the Vbe against the output IF power. Two curves are very
close together except when the output power reaches saturation. It can be seen that the
Vbe of Mixer II does not drop as fast as that of Mixer I, although the stabilization
effect is not very significant.
Third, it injects additional bias current into the transconductance transistor. Figure
3.19 plots the collector current of TxRF against the output IF power. It is easily
observed that the collector current of Mixer II increases as the RF input power
increases.
36
The increase of collector current pulls up the transistor bias point and release more
current swing room when RF input power increases.
The complete performance of Mixer I and Mixer II are summarized and compared in
Table 3.4.
Mixer I Mixer II Power conversion gain (dB) 10.8 3.3 Input P1dB (dBm) -13.8 -3 Output P1dB (dBm) -4 -0.7 Noise figure @ 100MHz (dB) 7.9 7.5 RF-LO Isolation (dB) <-300 <-300 LO-IF Isolation (dB) <-300 <-300 Mixer core bias current (mA) 5.8 5.7 Total current (mA) 6 6 DC supply (V) 5 5 Power consumption (mW) 30 30
Table 3.4 Performance comparison of Mixer I and Mixer II
3.7 Modification to conventional mixer design
In spite of significant improvement of dynamic range as indicated by the input P1dB
point, the output power handling ability is not significantly improved. Output P1dB is
only improved from –4dB to –0.7dB. In order to achieve larger improvement, we
once again examine the original circuit.
38
It is important to note that conventional Gilbert mixer designs always incorporate
current mirrors as current control devices. But current mirrors may prohibit the effect
of active bias. As explained before, active bias injects additional bias current to the
transconductance transistors, a phenomenon that retards the gain compression and
contributes to the linearity improvement. However, as the total current of the two
transconductance transistors is controlled by the current mirror, it is impossible to
obtain a large current injection from the active bias. Therefore, a possible way of
getting rid of this limit is to remove the current mirror.
The following two designs Mixer III and Mixer IV are a pair of mixers without
current mirrors. Mixer III still uses conventional bias while Mixer IV uses active bias.
A detailed analysis and performance comparison is to be presented in the following
sections.
3.8 Mixer III
In order to examine the effect of active bias in an environment absent of current
mirrors, two mixers are designs. Mixer III uses conventional bias circuit and is
designed to set the reference for Mixer IV.
Figure 3.20 shows the schematic diagram of Mixer III. Instead of connecting the
39
emitters of TxRFs to the current mirror, they are directly connected to ground.
Figure 3.20 Schematic diagram of Mixer III
Figure 3.21 shows the matching network of Mixer III. The matching condition is
shown in Figure 3.22.Again return losses of three ports are less than –10dB.
40
Figure 3.21 Matching network of Mixer III
Next, simulation results are presented below. Figure 3.23 shows the gain compression
curve while Figure 3.24 shows the noise figure curve.
41
Figure 3.22 S parameters of Mixer III
Figure 3.23 Power conversion gain and input P1dB of Mixer III
Figure 3.24 Noise figure of Mixer III
42
The complete performance of Mixer III is summarized in Table 3.5
Mixer III Power conversion gain (dB) 10.8 Input P1dB (dBm) -13.2 Output P1dB (dBm) -3.4 Noise Figure @ 100MHz (dB) 7.7 RF-LO Isolation (dB) <-300 LO-IF Isolation (dB) <-300 Mixer core bias current (mA) 5.3 Total current (mA) 5.5 DC supply (V) 5 Power consumption (mW) 27.5
Table 3.5 Performance summary of Mixer III
3.9 Mixer IV
Mixer IV uses active bias. Except for the bias network, all the other components are
exactly the same as those in Mixer III. In addition, DC power consumptions of Mixer
III and Mixer IV are kept at the same level. Thus comparison can be made so as to
determine the effect of the active bias technique in mixers without current mirrors.
The active bias network is exactly the same as those used in Mixer II. It comprises
two pairs of transistor and capacitor. Each pair is responsible for the linearization of
one transconductance transistors TxRF in the mixer core.
43
Figure 3.25 shows the schematic diagram of Mixer IV and Figure 3.26 shows the
matching network of Mixer IV.
Next, simulation results are plotted in Figure 3.27 to Figure 3.29.
Figure 3.25 Schematic diagram of Mixer IV
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Figure 3.28 Power conversion gain and input P1dB of Mixer IV
Figure 3.29 Noise figure of Mixer IV
46
The complete performance of Mixer IV is summarized in Table 3.6
Mixer IV Power conversion gain (dB) 5.1 Input P1dB (dBm) -1.2 Output P1dB (dBm) 2.9 Noise Figure @ 100MHz (dB) 7.8 RF-LO Isolation (dB) <-300 LO-IF Isolation (dB) <-300 Mixer core bias current (mA) 5.2 Total current (mA) 5.5 DC supply (V) 5 Power consumption (mW) 27.5
Table 3.6 Performance summary of Mixer IV
3.10 Performance comparison of the four designs
Figure 3.30 plots the gain compression curves of the four mixers against the RF input
power. By comparing curves of Mixer III and Mixer IV, we conclude that in mixers
without current mirrors, the active bias can improve the input referred P1dB by 12dB.
Recall that the improvement from Mixer II as compared to Mixer I is 10.8dB. In fact,
Mixer IV has the largest input referred P1dB of the four designs.
Figure 3.31 plots the gain compression curves of the four mixers against the IF output
power. Again, by comparing curves of Mixer III and Mixer IV, we conclude that the
active bias can improve the output referred P1dB by 6.3dB. Recall that this
improvement from Mixer II as compared to Mixer I is only 3.3 dB. Once more, Mixer
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IV has the largest output referred P1dB. As a consequence, the active bias technique
works much more effectively in mixers without current mirrors.
The further linearity and dynamic range improvement can be attributed to the
stabilization of base-emitter voltage of TxRF and the large bias current injection to
TxRF as output power increases. Figure 3.32 plots the Vbe against the IF output power.
It is readily observed that Mixer IV has very stable Vbe as compared to the other 3
mixers. The change of Vbe is only about 0.03 volts. On the other hand, large injection
bias current can be observed in Figure 3.33. The bias current of Mixer IV has
increased over 50% when the output power level increases. Such large current
injection pulls up the DC bias point of the TxRF transistors, leading to larger current
swing room which directly retards the gain compression.
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Figure 3.30 Gain compression versus RF input power (4 mixers)
Figure 3.31 Gain compression versus IF output power (4 mixers)
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Figure 3.32 Vbe versus IF output power (4 mixers)
Figure 3.33 Ic versus IF output power (4 mixers)
50
A complete summary of the four mixers performance is presented in Table 3.7.
Mixer I Mixer II Mixer III Mixer IV Power conversion gain (dB)
10.8 3.3 10.8 5.1
Input P1dB (dBm) -13.8 -3 -13.2 -1.2 Output P1dB (dBm) -4 -0.7 -3.4 2.9 Noise figure @ 100MHz (dB)
7.9 7.5 7.7 7.8
RF-LO Isolation (dB)
<-300 <-300 <-300 <-300
LO-IF Isolation (dB)
<-300 <-300 <-300 <-300
Mixer core bias current (mA)
5.8 5.7 5.3 5.2
Total current (mA) 6 6 5.5 5.5 DC supply (V) 5 5 5 5 Power consumption (mW)
30 30 27.5 27.5
Table 3.7 Performance comparison of the four mixers
3.11 Summary
In this chapter, the design of four Gilbert mixers is presented. First, a simple Gilbert
mixer is designed with acceptable performance. Next, active bias technique is used in
Mixer II to improve the mixer dynamic range (input P1dB) and linearity (output
P1dB). However, it is observed that current mirrors that are used in Mixer I and Mixer
II may limit the current injection from active bias, prohibiting larger linearity
improvement. As a result, two more mixers are designed without current mirrors.
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Mixer III serves as a reference and was designed using conventional bias network
while Mixer IV uses active bias network. Simulation results show that the proposed
active bias technique is much more effective once current mirrors are removed from
the Gilbert cell and Mixer IV exhibits the largest input P1dB as well as the largest
output P1dB. Moreover, it is important to note that the improvement of linearity does
not incur the degradation of noise performance. The noise figures of mixers with
active bias are very close to those of mixers without active bias.
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Chapter 4
Mixer Layout
4.1 Introduction
Integrated circuit layout is the representation of an integrated circuit in terms of planar
geometric shapes which correspond to the patterns of metals, oxide and
semiconductor layers that constitute the components of the integrated circuit. IC
layout design is a relatively new field. Until recently it has been considered as a
profession which is now attracting more and more people. [11]
In this chapter, the layouts of basic BiCMOS integrated circuit component (resistors,
transistors) are introduced. Then the layouts of the four mixers are presented. Finally,
the concept of physical verification is explained.
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4.2 Resistor layout
Two types of resistors are used in the mixer layout design: rpoly and rxbase. The
rpoly resistor has advantages of low flicker noise [12] while the rxbase resistor is used
for large resistance applications.
Figure 4.1 shows the layout of a rpoly resistor. The rpoly resistor is made of materials
called polysilicon and is simple in layout. A rpoly resistor can be connected by the
metal strips on the two sides of the resistor. The sheet resistance of rpoly1 is 34
ohms/square and the sheet resistance of rpoly2 is 72 ohms/square. This type of
resistors is used for load resistors RL and degeneration resistors Rs.
Figure 4.1 Layout of a rpoly resistor
Figure 4.2 shows the layout of a rxbase resistor. The rxbase resistor is usually used as
bias resistor, since its square resistance is very large. The sheet resistance is 4000
ohms per square. The accuracy is within 15%. However, its layout is a little more
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complicated. As we can see from Figure 4.2, a rxbase resistor must be placed upon a
nwell region which must be connected to positive voltage through contacts. The long
metal strip stretching out of the nwell region connects the nwell to a positive voltage.
Figure 4.2 Layout of a rxbase resistor
4.3 Capacitor layout
Various types of capacitors are offered by the X-FAB foundry. The mimc capacitor is
formed by two layers of metals with a thick insulator layer inside. They are mainly
used as signal capacitors because the voltage dependency of the capacitance is
relatively small. Yet they usually consume large chip area. Another major category of
capacitors is PN junction capacitors. Although they are small in size, their voltage
dependency is quite large. Hence, mimc capacitors are used as current-shunting
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capacitors Cb in the active bias network.
Figure 4.3 shows the layout of a mimc capacitors.
Figure 4.3 Layout of a mimc capacitor
4.4 Bipolar transistor layout
The qnb4sa bipolar transistors have the smallest emitter and collector resistance as
compared to other bipolar transistors offered by the X-FAB foundry. The qnb4sa is a
snake shaped vertical NPN bipolar transistor with nwell and with quadruple base /
triple emitter / double collector.
56
The layout of qnb4sa is predefined. Only emitter length unit can be changed. Figure
4.4 shows the layout of a qnb4sa bipolar transistor with emitter length unit of 2.
Figure 4.4 Layout of a qnb4sa transistor with emitter length unit 2
Figure 4.5 shows the layout of a qnb4sa transistor with emitter length unit 16.
Comparing Figure 4.4 and Figure 4.5, we note that the transistor with emitter length
unit 16 is much longer than the one with emitter length unit 2.
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Figure 4.5 Layout of a qnb4sa transistor with emitter length unit 16
4.5 CMOS layout
NMOSFET is used to constitute the current mirrors in Mixer I and Mixer II, because
the total gate width of NMOSFET can be easily adjusted. Figure 4.6 shows the layout
of a noms4 MOSFET with single gate. The central poly layer is connected to metal
line above through contacts. Source and drain are interchangeable as they are exactly
the same in layout. Figure 4.7 shows the layout of a noms4 MOSFET with 16 gates.
58
All the gates, drains and sources are connected together. Again gate is connected to
metal through contacts while drains and sources can be directly accessed by metal
connection.
The basic layout of nmos4 MOSFET can be extended to the layout of a simple current
mirror which is shown in Figure 4.8. The current mirror is formed by two nmos4
MOSFETs. The gate width ratio is 1:33, as a result, the current ration is around 1:33.
Figure 4.6 Layout of a noms4 MOSFET with single gate
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Figure 4.7 Layout of a noms4 MOSFET with 10 gates
Figure 4.8 Layout of a current mirror formed by two nmos4 MOSFETs
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4.6 RF pad layout
RF signal pads are used to connect on-chip signal paths to off-chip signal paths. The
major body of the pad is a big unmasked metal area, where wires can be bonded in
order to lead signal come into or go out from the integrated circuit. Figure 4.9 shows
the layout of RF signal pad.
Figure 4.9 Layout of a RF signal pad
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4.8 Physical verification
Physical verification is a necessary step after initial layout design in order to ensure
that the IC chip is able to function according to our desire. Physical verification
involves several steps including DRC (Design Rule Check) and LVS (Layout Versus
Schematic) Check.
Design Rule Checking or DRC determines whether a particular chip design satisfies a
set of recommended parameters called Design Rules provided by the semiconductor
foundry.
Layout Vs. Schematic check or LVS determines whether a particular chip layout
corresponds to the original schematic or circuit diagram of the design. A successful
DRC only ensures that the layout obeys certain rules so that fabrication can be carried
out without problems. However, it does not guarantee if it really represents the circuit
you desire to fabricate.
In a word, DRC and LVS are indispensable checks after a chip layout is finished.
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4.9 Conclusion
In this chapter, basic BiCMOS component layout techniques are addressed. Four
mixer layout designs are presented. All of the layouts have already gone through
physical verification process. It is important to note that IC layout design is rather
complicated and a good layout design makes a big difference in achieving good
circuit performance.
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Chapter 5
Mixer Testing
5.1 Introduction
In this chapter, we introduce basic issues related to IC testing, including testing board
design, wire bonding and result measurement.
5.2 Testing board
In order to test the mixer chips, we first design a testing PCB board. Figure 5.1 shows
the testing board layout. The mixer chips, each occupying an area of 1600mm x
800mm, will be mounted at the center of the testing board. Matching components will
also be mounted at the reserved spaces on the testing board. Besides, All the signal
transmission lines, i.e. RF, LO and IF signal lines are designed to have a characteristic
impedance of 50 ohms. Figure 5.2 shows a fabricated testing board.
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5.3 Wire bonding
Wire bonding is a method to connect the IC chip to the outside world. In the bonding
process, a wire is attached from one connection pad to another. One connection pad is
on the semiconductor chip while the other pad is on the interconnection substrate (the
metal leads on the testing board).
In general, there are two categories of wire bonding, ball bonding and wedge bonding.
Most of semiconductor packaging and assembly are done with ball bonding while
some others are done with wedge bonding. As ball bonds can be used in very tight
spaces, it is a dominant method as the bond pads and pad spacing are becoming
smaller. Gold wires can be used for both methods while aluminum wires can be only
used in wedge bonding. In our laboratory, a kns wedge bonder is provided.
Wedge Bonding Ball Bonding
Figure 5.3 Wedge bonding and ball bonding
68
Figure 5.4 KNS wedge bonder
5.4 Testing results
Due to the IC foundry schedule delay, the designed chips still had not returned from
the Germany foundry at the moment when this report was submitted. Yet testing will
be conducted immediately after the chips return.
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Chapter 6
Conclusion
In this project, the design, layout and testing of Gilbert cell mixers in 0.6μm BiCMOS
technology was shown. First, a simple Gilbert cell mixer was designed using
conventional bias, the performance of which is acceptable but not satisfactory. Then a
modified active bias technique was proposed and incorporated to the design of Mixer
II. The proposed active bias can improve the mixer dynamic range which is indicated
by the input referred P1dB as well as the mixer linearity which is indicated by output
referred P1dB. Yet the improvement was still not enough. In an effort to optimize the
performance of the active bias technique, current mirrors were removed from the
conventional Gilbert cell so as to release the current control. The next two mixers
were designed without current mirror. In order to set up a reference, Mixer III was
still designed with conventional bias while Mixer IV was designed with active bias. It
is shown that once current mirrors are removed, the active bias technique is more
effective. The linearity improvement was almost doubled. The reason behind such
70
improvement is that the active bias can stabilize the base-emitter junction voltage of
the RF transconductance transistors in the mixer core and inject large bias current
when the output power level increases.
There is still much to be done in the area of high linearity Gilbert mixer design. One
possible future task is to reduce the large insertion loss introduced by the active bias
technique proposed in this project. If the large insertion loss can be reduced
significantly, the linearity would be further improved.
71
Reference
[1]. Youn Sub Noh, Chul Soon Park, “PCS/W-CDMA Dual-Band MMIC Power
Amplifier With a Newly Proposed Linearizing Bias Circuit”, IEEE journal of
solid-state circuits, vol. 37, No. 9, September 2002.
[2]. Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits.
Cambridge University Press, New York, 1998
[3]. Q. Li, J.S. Yuan, “Linearity analysis and design optimization 0.18μm CMOS RF
mixer”, IEE Proc.-Circuits Device7 Syst., Vol. 149, No. 2, April 2002
[4]. Barrie Gilbert, “A precise four-quadrant multiplier with subnanosecond response”,
IEEE journal of solid-state circuits, December 1968
[5]. N. Rodríguez, E. Hernández, G. Bistué, I. Gutiérrez, J. Presa and R. Berenguer,
“Comparing active Gilbert mixers integrated in standard SiGe process”,
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[6]. Manolis T. Terrovitis, Robert G. Meyer, “Noise in Current-Commutating CMOS
Mixers”, IEEE journal of solid-state circuits, vol. 34, No. 6, June 1999.
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[7]. Toshihiko Yoshimas, Masanori Akagi, Noriyuki Tanba, and Shinji Hara, “An
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[9]. Kazuhisa Yamauchi, Masatoshi Nakayama, Yukio Ikeda, Hiromasa Nakaguro,
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[12]. Hooman Darabi, Janice Chiu, “A Noise Cancellation Technique in Active
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Acknowledgement
Here I would like to express my gratitude to a number of people who have helped me
in the project. First of all, I would like to thank my supervisor, Prof. Chi-Hou Chan,
for his continuous support and guidance, no matter on my project, or on my graduate
study matters. Without his advice and help, I could not have won the Fulbright
fellowship and have received the admission to the University of California, Berkeley.
I am also truly benefited from the biweekly meetings where I learned presentation
skills and working attitudes. I would also like to thank my co-supervisor, Dr. Xue
Quan. Although officially I am not his project student, he still guided me through the
important stages of the project, making sure that I am on the right track.
I want to extend my gratitude to my mentor, Roy Lau, who has been providing me
with numerous technical advices and suggestions since I came to know him. When I
was depressed with a major mistake made during the design, he came to my rescue
and helped me to solve the problem. I’d also like to thank my first mentor, Liu Yan
Fan, who introduced me into the world of RFIC design. Although, we only worked
together for less than a week, I am grateful to his patience at the early stages of the
project. My thanks also go to Yang Tan and You Yu for teaching me IC related skills.
Being an expert on IC layout and wire bonding skills, Yang Tan is always ready to
help others. I would also like to thank all my FYP fellow students working on the 7th
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floor. We together made the final year a fruitful time.
Finally and for most, I would like to thank my parents and grandparents, who have
always been the greatest support for me throughout the last 22 years. Words are never
enough to express my gratitude. Without the warm love from family, I could not
imagine where I would be.
Chen, Jiashu
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