Gate Level Minimization

Nugroho Adi P, S.Si, M.Sc nugnux@gmail.com, aravir@me.com

http://aravir-rose.blogspot.com

untuk mendapatkan jumlah gerbang yang optimal

Map Method

lebih tersturktur dari metode aljabar

Karnaugh Map

K-map

Karnaugh Map

Karnaugh Map

Karnaugh Map

m1 +m2 +m3 =x’y+xy’+xy

=x+y

xy

x+y

K-map 3 variabel

K-map 3 variabel

m5+m7

m5 +m7 =xy’z+xyz =xz(y’+y)

=xz

F(x,y,z) = ∑(2,3,4,5)

F(x,y,z) = (2, 3, 4, 5)

F = x’y + xy’

m0 dan m2

m0 +m2 =x’y’z’+x’yz’ =x’z’(y’+y)

=x’z’

m4 dan m6

m4 + m6 = xy’z’ + xyz’ = xz’+(y’ + y)

=xz’

F (x, y, z) = (3, 4, 6, 7)

F(x,y,z) = ( 3, 4, 6, 7)

F = yz + xz’

m0 +m2 +m4 +m6 F(x,y,z) = ∑(0,2,4,5,6)

F = A’C + A’B + AB’C + BC f=xy+xz’+yz+x’y’z’

!

!

K-map 4 variabel

K-map 4 variabel

F(w,x,y,z) = ∑(0,1,2,4,5,6,8,9,12,13,14)

F(w,x,y,z) = ∑(0,1,2,4,5,6,8,9,12,13,14)

F = y’ + w’z’ + xz’

F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’

F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’

F = B’D’ + B’C’ + A’CD’

Don’t Care

minterm yang tidak penting

Don’t Care

F(w,x,y,z) = ∑(1,3,7,11,15) d(w,x,y,z) = ∑(0,2,5)

F(w,x,y,z) = ∑(1,3,7,11,15) d(w,x,y,z) = ∑(0,2,5)

F(w,x,y,z) = ∑(1,3,7,11,15) d(w,x,y,z) = ∑(0,2,5)

!

F = yz + w’x’ F = yz + w’z F’ = z’ + wy’

1. F(x,y,z) = ∑(0,1,4,5,6); d = ∑(2,3,7) 2. F(A,B,C,D) = ∑(0,6,8,13,14); d = ∑(2,4,10) 3. F(A,B,C,D) = ∑(5,6,7,12,14,15); d = ∑(3,9,11,15) 4. F(A,B,C,D) = ∑(4,12,7,2,10); d = ∑(0,6,8)

Build Your Own Gate

–John Crisp

Along with the law of nature that decrees that buttered toast always lands butter-side down, there is one that states 'However many logic

gates we have, the one we want is not amongst them'.

4-input AND gate from two 3-input AND gates.

3-input OR gate as a 2-input gate

3-input OR gate as a 2-input gate

3-input AND gate as a 2-input gate

3-input AND gate as a 2-input gate

NAND dan NOR

the basic gates used in al l IC digital logic families

NAND

Gerbang Universal

Gerbang Universal

NAND

Gerbang Apa ini?

Two Level Implementation

F = AB + CD

F = AB + CD

F = AB + CD

F = AB + CD

F(x,y,z) = (1,2,3,4,5,7)

Step 1

Simplify the function and express it in sum-of-products form.

Step 2

Draw a NAND gate for each product term of the expression that has at least two

literals. The inputs to each NAND gate are the literals of

the term. This procedure produces a group of first-level

gates.

Step 3

Draw a single gate using the AND-invert or the invert-OR graphic symbol in the second level, with

inputs coming from outputs of first-level gates.

Step 4

A term with a single literal requires an inverter in the first level.

However, if the single literal is complemented, it can be connected directly to an input of the

second- level NAND gate.

Tugas

1. F(A,B,C,D)=AC’D’+A’C+ABC+AB’C+A’C’D’ 2. F(A,B,C,D)=A’B’C’D+CD+AC’D 3. F(A,B,C)=(A’+C’+D’)(A’+C’)(C’+D’) 4. F(A,B,C,D)=A’+B+D’+B’C

Selesai

“Dan dia hidup bahagia selama-lamanya…”