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Page 1
Universidad de Huánuco
Facultad de Ingeniería de Sistemas e Informática
Page 2
Agenda
• Base del Conocimiento
– Diagramas de Bode
– Diseño de Filtros Analógicos
– Diseño de un Electrocardiograma
– Microcontrolador PIC con Labview
• Motor de Inferencia
– Técnicas de Diagnóstico de un ECG
• Medios de Comunicación
– Prototipo de un ECG
Page 3
Acerca del ECG-UDH
Page 4
Modelando un PIC
PIC
Procesador
Memoria
Temporizador
ADC USB
GLCD
Oscilador
Page 5
Modelando un PIC
Input Variables
Output
(User Interface)
Variables
(Link to other Systems)
Embedded Computer
Software
Hardware
Sig
nal
Co
ndit
ion
ing
Dat
a
Co
nve
rsio
n
Out
put
Dri
ve
(display, keypad etc.)
Page 6
Microcontrolador PIC
• Como sabemos los micro
controladores de 8 bits de
Microchip se dividen en 3
gamas: – PIC10 y PIC12: Gama baja
– PIC16: Gama media
– PIC18: Gama alta
Page 7
Estructura Interna de un PIC
Page 8
Estructura Externa de un PIC
Page 9
Organización de las Memorias de un PIC
a) Enfoque de Von Neumann b) Enfoque de Harvard
Data
Memory
Program
Memory
Address
Data
Central Processing
Unit (CPU)
Input/
Output
Central
Processing
Unit (CPU)
Data
Memory
Input/
Output
Program
Memory
Address
Data
Address
Data
Address
Data
Page 10
Arquitectura RISC-PIC A CISC machine is generally
recognised by:
• Many instructions (say over one
hundred), some with considerable
sophistication;
• Instruction words are of different
length;
• Instructions take different
lengths of time to execute.
A RISC machine is generally
recognised by:
• Few instructions (say well below
one hundred),
• Each performs a very simple
action;
• All instructions are single word;
• All, or almost all instructions
take the same length of time to
execute.
Digital
Program
I/0Microprocessor
DataMemory
Memory
CoreAnalog
I/0
& TimersCounters
Reset
Power
Clock
Address Buses
Internal Data &
FurtherPeripheral
FurtherPeripheral
Interrupt(s)
A microcontroller = microprocessor core + memory + peripherals
Page 11
Diagrama de Bloques del PIC
The CPU
Address for Program Memory
Data from
Program
Memory,
carrying
instruction
word
Address for
Data Memory
Data bus for
Data Memory
and
peripherals
Program Memory
Data
Memory
Extra “non-
volatile” Data
Memory
Counter/Timer
Peripheral
Digital Input/
Output Ports
It is easy to see the
Program memory, which
uses Flash memory
technology. Alongside this
comes the Stack, which
we meet later. Microchip
call the main data
memory “File Registers”.
There is another section
of data memory which
uses EEPROM
technology.
Page 12
Registro de Estado de un PIC
Condition
Code Flags
Page 13
Memoria de Programa y Stack
Program
Counter
16 Series
instructions which
invoke the Stack
Unimplemented memory
space, still addressable
by the 13-bit 16F84A
program address bus.
Program Counter
points to locations
in program memory
The program
must start here
The Interrupt
Service Routine
must start here
Page 14
Mapa de Memoria de Datos y (SFR) Registro de Funciones Especiales
msb is “bank select bit”
(Status register).
These are the Special Function
Registers, which allow the CPU to
interact with the peripherals
General purpose memory
Page 15
Interface con Periféricos vía el Registro de Funciones Especiales
Control SFR(s)
Peripheral
Data Transfer SFR(s)
Microcontroller
Core
"Outside
World"
Interrupt(s)
Microcontroller Interaction with its Peripherals, via Special Function Register (SFR) and Interrupt
microcontroller peripherals can be configured in software to operate in a number of different modes,
to do this certain control data must be sent to them to set them up in the desired way
once in use, there will be data flow between core and peripheral,
there may still be need for further control data,
these needs are commonly met by means of dedicated, memory - mapped registers, sometimes
called Special Function Registers,
this approach gives the microcontroller manufacturer great flexibility to extend a microcontroller
family – SFRs for new peripherals can easily be located in gaps in the memory map.
Page 16
Configuraciones Globales del PIC
The configuration word determines certain operating features
of the microcontroller. It is in program memory, but cannot be
accessed in normal operation. It is written to during the
programming process. You set its value either by response to
a dialogue box in MPLAB, or by use of Assembler
Directives, at the head of your programme.
The 16F84A
Configuration
Word
Page 17
Tipos de Memorias de un PIC
Page 18
Características de los Osciladores
Oscilador Primario
Oscilador Secundario
Oscilador Interno
Frecuencias de Oscilación Altas (XT, HS)
Frecuencias de Oscilación Medias (LP)
Frecuencias de Oscilación Bajas (RC)
Con PLL
Sin PLL
Con Pre Escala
Sin Pre Escala
Con Pre Escala
Sin Pre Escala
Multiplica Frecuencia
de Oscilación
Divide Frecuencia de Oscilación
Divide Frecuencia de Oscilación
Page 19
Modos del Oscilador
The 16F84A can be configured to operate in four different oscillator modes, using R-C,
crystal or ceramic oscillators. It can also accept an external clock source. The user selects
which mode is to be used by setting bits in the Configuration Word.
XT – Crystal
The standard crystal configuration, intended for crystals or ceramics in the range 1MHz to
4MHz.
HS – High Speed
A higher drive version of the XT configuration, for higher frequency crystals and ceramic
resonators. Intended for frequencies in the region of 4MHz or greater. It leads to the highest
current consumption of all the oscillator modes.
LP – Low Power
Intended for low frequency crystal applications, and gives the lowest power consumption
possible. Will however operate at any frequency below around 200kHz.
RC - Resistor-Capacitor
Requires connection of an external resistor and capacitor. The lowest cost way of getting an
oscillator, but should not be used when any timing accuracy is required.
Page 20
Modos del Oscilador
b) Resistor-Capacitor c) Externally Supplied Clock
a) Crystal or Ceramic, HS, XT, or LP
RA2
RA3
RA4/T0CKI
MCLR
V
RB0/INT
RB1
RB2
RB3 RB4
RB5
RB6
RB7
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDDSS Supply voltage
Oscillator connections
Port A, Bit 0
Port A, Bit 1Port A, Bit 2
Port A, Bit 3
*Port A, Bit 4
Ground
**Port B, Bit 0
Port B, Bit 1
Port B, Bit 2
Port B, Bit 3
Port B, Bit 7
Port B, Bit 6
Port B, Bit 5
Port B, Bit 4
*also Counter/Timer clock input
**also external Interrupt input
Reset
1
9 10
18
The Oscillator Pins
Page 21
Diagramas de un Oscilador Primario
Page 22
Acerca del Conversor Analógico a Digital ADC del PIC
Page 23
Acerca del ADC del PIC
Page 24
Agenda
• Base del Conocimiento
– Diagramas de Bode
– Diseño de Filtros Analógicos
– Diseño de un Electrocardiograma
– Microcontrolador PIC con Labview
• Motor de Inferencia
– Técnicas de Diagnóstico de un ECG
• Medios de Comunicación
– Prototipo de un ECG
ADC
Page 25
Acerca del ECG-UDH
Page 26
Características ADC del DSPIC
• Conversión vía aproximación sucesiva SAR.
• Velocidad de conversión de hasta 500 ksps.
• Hasta 16 pines de entrada analógica.
• Pines de referencia de Voltaje Externo.
• Modo Automático de Escaneo de Canal .
• Fuente seleccionable de activación de conversión.
• Buffer de resultado de conversión de 16 word
• Modos seleccionables de llenado de Buffers.
• Cuatro opciones de alineamiento de resultado.
• Modos de operación durante el estado Sleep e Idle.
Page 27
Acerca del ADC del PIC
Page 28
Flujo grama de operación del ADC
Page 29
Estructura Módulo A/D del PIC24F
VREF+
VREF-
A/D converter
Conversion Control
Bu
s I
nte
rfa
ce
Data Format
Sample Sequence Control
AN0
AN1
S/H
AN15
CH0 8/16 Level Results Buffer
VR+
VR-
VR
Sele
ct
AVDD
AVSS
Page 30
Eje y: Tiempo de Conversión A/D = Tiempo de Adquisición más Conversión
Tiempo de
Adquisición
Tiempo de
Conversión
Inicio del
Tiempo de
Adquisición
Fin de
Conversión
Entrada
Analógica
Tiempo de Conversión A/D
Clock A/D
TAD
Page 31
Registro de Control ADC
Page 32
Eje x: Tiempo de Muestreo
AD1CON3<ADCS7:ADCS0>
TCY to 256*TCY
RCAD
FCY = FOSC/2
TAD
AD1CON3<ADRC>
1
0
AD Clock
Postscaler † by
1 to 256
Page 33
Proceso de Operación del ADC
Page 34
Configuración del Clock del ADC
Page 35
Aspectos de Precisión Digital
Page 36
Diagrama de Bloques del ADC 10bits
AVDD
AVSS
VREF+
VREF-
VR+
VR-
VR
Sele
ct
AD1CON2<VCFG2:VCFG0>
AVSS AVDD 1xx
VREF- VREF+ 011
VREF- AVDD 010
AVSS VREF+ 001
AVSS AVDD 000
VR- VR+ VCFG2:VCFG0
AD1CON2 Register
bit15
CSSL13=0 CSSL14=0 CSSL15=0
BUFM
bit0
ALTS
CSNA VCFG2 VCFG1 VCFG0
bit8
SMPI1 SMPI 0 SMPI3 SMPI2 BUFS bit7
--- --- --- ---
---
Page 37
Diagrama de Bloques del ADC 10bits
AN0
AN1
AN15
Mux A
VR-
AN1
AD1CHS<CH0SA3:CH0SA0>
AD1CHS<CH0NA>
VINH
VINL
(0)
(1)
AD1PCFG Register bit15
CSSL10=0 CSSL13=0 CSSL14=0 CSSL8=0 PCFG1
bit0
PCFG0 PCFG2 PCFG15 PCFG14 PCFG13 …………
bit8
AD1CON2 Register bit15
CSSL13=0 CSSL14=0
BUFM
bit0
ALTS
CSNA VCFG2 VCFG1 VCFG0
SMPI1 SMPI 0 SMPI3 SMPI2 BUFS
bit7
--- --- --- ---
---
bit8
AD1CHS Register bit15
CH0SA1
bit0
CH0SA0 CH0SA2 CH0NA bit7
CH0SA3
CH0SB1 CH0SB0 CH0SB2 CH0NB CH0SB3 --- --- ---
--- --- ---
AD1CSSL Register bit15
CSSL13=0 CSSL14=0 CSSL1
bit0
CSSL0 CSSL2 CSSL15 CSSL14 CSSL13 …………
Page 38
Escaneo de Canales del ADC
ADCBUF Buffer
+
-
CH 0
AN15
AN14
….
AN5
AN4
AN3
AN2
AN1
AN0
+B
- B
+A
- A
VREF-
AN1
AN0
AN2
AN13
AN14
INT
ADCBUF0
AD1CSSL Register bit15
CSSL13=0 CSSL14=0 CSSL1
bit0
CSSL0 CSSL2 CSSL15 CSSL14 CSSL13
AN13
…………
bit8
AD1CON2 Register bit15
CSSL13=0 CSSL14=0
BUFM bit0
ALTS
CSNA VCFG2 VCFG1 VCFG0
SMPI1 SMPI 0 SMPI3 SMPI2 BUFS bit7
--- --- --- ---
---
Page 39
Diagrama de Bloques del ADC 10 bits
VINH
VINL
S/H
Mux A
M
ux B
AD1CON1<ASAM>
AD1CON1<SAMP> Señal de
Conversion
completa
0 1
bit8
AD1CON2 Register bit15
CSSL13=0
BUFM
bit0
ALTS
CSNA VCFG2 VCFG1 VCFG0
SMPI1 SMPI 0 SMPI3 SMPI2 BUFS bit7
--- --- --- ---
---
Page 40
Diagrama de Bloques del ADC 10 bits
VINH
VINL
S/
H
AD1CON1<ASAM>
AD1CON1<SAMP>
Conversion
complete Signal ADC1BUF0
:
ADC1BUF15
RESULT
VR+ VR-
AD1CON1<DONE>
AD1CON3<SAMC4:SAMC0> (7) 0 TAD to 31 TAD
AD1CON1
<SSRC2:SSRC0>
Clearing AD1CON1<SAMP> (0)
Active Transition on INT0 pin (1)
Timer4 Compare ends (2)
Evitar 0 TAD
A/D converter
VR- VR+
Page 41
Diagrama de Bloques del ADC 10 bits
0000 00dd dddd dddd
ssss sssd dddd dddd
dddd dddd dd00 0000
sddd dddd dd00 0000
RESULT
FORMAT
AD1CON1<FORM1:FORM0>
AD1CON2<BUFM> = „0‟
AD1CON2<BUFS>
AD1CON2<SMPI3:SMPI0>
ADC1BUF0
:
:
:
:
:
:
ADC1BUF15
AD1CON2<BUFM> = „1‟
ADC1BUF0
:
:
ADC1BUF7
ADC1BUF8
:
:
ADC1BUF15
0
1
Page 42
Ejercicio N1: Digitalizar la Señal Analógica ECG
• Tareas a realizar:
– Programar el PIC con MPLAB en C18.
– Realizar la conversión digital de una señal
analógica en Proteus con PIC usando
Potenciómetro.
• Resultado esperado:
– Digitalización de una señal analógica y su
visualización usando LCD.
Page 43
Objetivos del Laboratorio
• Configurar el ADC
• Configurar los puertos de E/S
• Leer el ADC y mostrarlos en LEDs
VDD
Vss
PIC24
AN5
POT R6
RA7-RA0
LEDs D10-D3
Page 44
Pasos a Realizar
• Open the project
– C:\RTC\203_PRC\Lab5\Lab5.mcp
• Open the file
– C:\RTC\203_PRC\Lab5\Lab5.c
• Look for ADCInit() function and configure ADC by initializing the registers AD1CON1, AD1CON2, and AD1CON3 looking into the Register details on the next few pages.
– STEP 1: AD1CON1 • Select Integer Format Result
• Auto Conversion Start
• Sample after conversion
– STEP 2: AD1CON2 • Select AVDD and AVSS as references
• Disable Scan mode
• Interrupt at 16th sample/Convert sequence
• 16*1 level buffer
• Always use Mux A
– STEP 3: AD1CON3 • Select Sample Time = 13TAD
• Conversion Time is always 12TAD
• Select AD Clock Source such that you get 16 samples in around 1 mSec (16 ksps)
• Assume 1TCY =.25 uS (FCY = 4 MHz)
Page 45
Pasos a Realizar
• Continue to configure ADC by initializing the registers AD1CHS, AD1PCFG, and AD1CSSL looking into the Register details on the next few pages.
STEP 4: AD1CHS Set the positive sample input channel for MUX A to use AN5
Set the negative input channel for MUX A to use VR-
STEP 5: AD1PCFG Set AD1PCFG so that the only pin using analog functionality is AN5
STEP 6: AD1CSSL Channel scanning is not enabled, so no input channels should be selected for scanning
• Build the project and program the device
• Procedure to Test
– Vary the POT and observe LEDs
Page 46
Configurando el Registro ADC
AD1CON1: A/D CONTROL REGISTER 1
ADON -- ADSIL -- -- -- FORM1 FORM0
Bit:8 Bit:15
ADC Module
enable bit
ADC Module
enable/disable
in IDLE mode
Result Format 00: Intiger (0000 00dd dddd dddd)
01: Signed Intiger (ssss sssd dddd dddd)
10: Fractional (dddd dddd dd00 0000)
11: Signed Fractional (sddd dddd dd00 0000)
SSRC2 SSRC1 SSRC0 -- -- ASAM SAMP DONE
Start Sampling,
If ASAM is „0‟
Conversion
Status bit
Bit:0 Bit:7
Conversion Trigger Source Selection Bits 000: Manual Conversion Trigger
001: Active transition on INT0 pin triggers conversion
010: Timer3 compare triggers conversion
111: Auto conversion
Auto Sample Selection bit 1: Sample immediately after completion of last conversion.
0: Sample on setting of „SAMP‟
Page 47
Configurando el Registro AD1CON2
VCFG2:VCFG0 VR+ VR-
000 AVDD AVSS
001 VREF+ AVSS
010 AVDD VREF-
011 VREF+ VREF-
1xx AVDD AVSS
VCFG2 VCFG2 VCFG0 -- -- CSCNA -- --
BUFS -- SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS
VR
Sele
ct
AVDD
AVSS
VREF+
VREF-
VR+
VR-
VCFG2:VCFG0
Bit:8 Bit:15
Scan CH0 Mux A Input
Bit:0 Bit:7
SMPI3:SMPI0 Interrupt Event
(Sample/convert sequence)
0000 each
0001 alternate
.... ….
1110 Every 15th
1111 Every 16th
Buffer Status bit, is valid only when BUFM = „1‟
1: Buffer 8-F is being filled,
can access Buffer 0-7 0: Buffer 0-7 is being filled,
can access Buffer 8-F
Buffer Mode Select bit 1: Buffer configured as two 8-words buffers
0: Buffer configured as one 16-words
buffers
Sample alternatively
MUX-A & MUX-B
Page 48
Configurando el Registro AD1CON3
SAMC4:SAMC0 Sampling Time
00000 0 TAD
00001 1 TAD
.... ….
11110 30 TAD
11111 31 TAD
ADRC -- -- SAMC4 SAMC3 SAMC2 SAMC1 SAMC0
ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0
ADCS7:ADCS0 Conversion Clock
00000000 TCY ( FCY )
00000001 2*TCY ( FCY / 2 )
.... ….
11111110 255*TCY ( FCY / 255 )
11111111 256*TCY ( FCY / 256 )
Bit:8 Bit:15
A/D conversion Clock
Source
1: ADRC is used
0: System clock is used
Bit:0 Bit:7
A/D Sample Time Selection bits
A/D Conversion Clock Selection bits
ADCS = (TAD/TCY) - 1
Page 49
Configurando el Registro AD1CHS
CH0SB3:CH0SB0 CH0 Positive Input for MUX B
0000 AN0
0001 AN1
.... ….
1110 AN14
1111 AN15
CH0NB -- -- -- CH0SB3 CH0SB2 CH0SB1 CH0SB0
Bit:8 Bit:15
CH0 Negative input for
MUX A 1: AN1
0: VR-
CH0NA -- -- -- CH0SA3 CH0SA2 CH0SA1 CH0SA0
Bit:0 Bit:7
CH0SA3:CH0SA0 CH0 Positive Input for MUX A
0000 AN0
0001 AN1
.... ….
1110 AN14
1111 AN15
CH0 Negative input for
MUX B 1: AN1
0: VR-
VREF-
AN15
AN0
ANxx
+B
- B
+
A - A
AN15
AN0
ANxx
VREF-
AN1
+
-
CH 0
AN1
CH0SB3:CH0SB0
CH0SA3:CH0SA0
CH0NB
CH0NA
Page 50
Configurando el AD1PCFG: Registro de Configuración de Puertos
PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
Bit:8 Bit:15
Bit:0 Bit:7
PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
Analog Input Pin Configuration Control bits 0 to 15
1: Pin for corresponding analog channel (ANxx) is in digital mode
0: Pin for corresponding analog channel (ANxx) is in analog mode
AD1CSSL : A/D Input Scan Select Regsiter
CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8
Bit:8 Bit:15
Bit:0 Bit:7
CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0
A/D Input Channel Scan Selection bits 0 to 15
1: Corresponding analog channel (ANxx) is selected for sequential
scanning
0: Corresponding analog channel (ANxx) is ignored for sequential
scanning
Page 51
Resultado Esperado
• El valor del POT es promediado cada 16
muestras en 1 ms.
• El valor del POT es mostrado en los LEDs
como un valor binario desde 0 hasta 255
• El Pin RB2 cambia de valor cada 16
muestras (con una frecuencia de 500 Hz)
Page 52
Agenda
• Base del Conocimiento
– Diagramas de Bode
– Diseño de Filtros Analógicos
– Diseño de un Electrocardiograma
– Microcontrolador PIC con Labview
• Motor de Inferencia
– Técnicas de Diagnóstico de un ECG
• Medios de Comunicación
– Prototipo de un ECG
USB
Page 53
Acerca del ECG-UDH
Page 54
Interfaces USB
USB
• Creado por Intel en el año 1994, versión 1.0.
• En el año 1998 se lanza la versión 1.1 con una velocidad de
transferencia baja de 1.5 Mbps y a full capacidad de 12 Mbps.
• En el año 2000, se lanza la versión 2.0 de alta capacidad con 480 Mbps.
Page 55
USB: Bus Serial Universal
• Auto détección & configuraóion (Plug&Play)
• Energía en el Bus
• 3 velocidades: Low- 1.5 Mbps, Full- 12 Mbps,
High- 480 Megabits/second
RS232
Paralelo
PS/2
Tipos de
Aplicación
Extend the functionality of
your computer!
Data Analysis,
Data Logging,
Firmware Updates,
Diagnostics,
Embedded Applications!
Page 56
Características del USB
NRZI Data Encoding
Half duplex – data transmission can go in only one direction at a time
Bus Power to each device:
4.40 - 5.25 V
Guaranteed 100 mA
500 mA maximum through negotiation
~ 5.0 V
~ 3.3 V
VBUS
D+
D-
GND
VBUS
D+
D-
GND
4-wire
connection
Differential
Signaling
Page 57
Características del USB
“mini-B” Plug
FS, HS Peripheral “B” Plug
FS, HS Peripheral
“A” Plug
USB Host
Page 58
Características del USB
Guaranteed Latency Guaranteed Data
Integrity
Interrupt
Bulk
Isochronous
PIC18F4550 family supports all these transfer types.
Page 59
USB Pipes
HOST PC
Big USB Pipe 12Mb/s
Small Pipe to each USB device (up to 127)
Tiny Pipes (endpoints)
Page 60
Client Software <-> Function
Client
Software
Interface
USB Device
Host
Endpoints
Data Flows
Buffers
Pipes
Page 61
El Dispositivo Lógico
Device (Manufacturer: Microchip Technology)
(Product: Mouse in a Circle Demo)
Configuration
Interface
IN (Endpoint 0) USB System Software
(default control pipes)
USB Device-Specific Pipe(s)
(Human Interface Device)
HID TX/RX Functions
(MCHPFSUSB FW)
Analog/Digital I/O
OUT (Endpoint 0)
IN (Endpoint x)
OUT (Endpoint x)
These settings are represented by a Device Descriptor Table, stored in firmware.
Page 62
Trama USB
BULK
BULK
BULK
BULK
BULK
BULK
BULK
BULK
Tx
Vo
ice
Tx
Lin
e
Inte
rru
pt,
Co
ntr
ol,
Lo
w
Sp
ee
d
Trame = 1ms
Stereo Audio
Stereo Audio
Stereo Audio
Stereo Audio
Stereo Audio
Stereo Audio
Stereo Audio
Stereo Audio
Stereo Audio
Stereo Audio R
x V
oic
e
Rx
Lin
e
Slot
SO
F
Low Speed
Low Speed
BULK
BULK
Sc
an
ne
r
Page 63
Periféricos USB
63
Joystick
Mouse SD Card
Reader
MCHP
RS-232
Data
Logger UPS
Keyboar
d
Generic
Human Interface Device
Class (HID)
Mass Storage
Device Class (MSD)
Communication
Device Class (CDC)
Digitizer
WinUSB LibUSB
Custom Class
(Vendor Class)
Audio
Class
MIDI
Speaker
Page 64
El Proceso de Enumeración
DETACHED
POWERED Power
(self/bus)
DEFAULT
Bus
reset
ADDRESS
Get Device
Descriptor
CONFIGURED
Get
Descriptors
ATTACHED
Cable
Connected SUSPENDED
Page 65
Auto Detección: Full Velocidad
+5V
D+
D-
GND
Transceiver
USB
Connector
Peripheral Device
VUSB 3.3 V Full Speed Identification
D+ line pull-up
1.5 k±5%
USB PIC® MCU
Page 66
Auto Detección: Baja Velocidad
+5V
D+
D-
GND
Transceiver
USB
Connector
Peripheral Device
VUSB 3.3 V Low Speed Identification
D- line pull-up
1.5 k±5%
USB PIC® MCU
Page 67
On-chip Pull-up Resistors
+5V
D+
D-
GND
Transceiver
USB
Connector
Peripheral Device
VUSB 3.3 V
On-chip pull-up resistors
available!
USB PIC® MCU
Page 68
Address and Configuration: EP0
See Chapter 9 in USB 2.0 Spec for more info.
Other Endpoints
Endpoint 0 IN (Control Data)
Endpoint 0 OUT (Control Data)
Dual Port/Access RAM
Descriptors
Control Transfers
USB PIC® MCU
Page 69
Descriptores
Device
Configuration 1
Interface 0
Endpoint
Interface 1
Endpoint Endpoint Endpoint
To other Configurations if any
To other Interfaces
if any
String 0
String 1
String N
Descriptors are typically stored in non-volatile/Flash memory
Page 70
Ejemplo de Descriptores
PICDEM™ USB
Microchip
Device
Configuration 1
Interface 0
Endpoint
Manu. String
Prod. String
USB 2.0, VID = 0x04D8,
PID = 0x0007, Num. Configurations,
Strings?
Configuration #1: Bus-Powered,
Remote Wakeup, 500mA, Num.
Interfaces
Interface #0: HID Class, Num. Endpoints
Endpoint 1 IN, Interrupt Transfer Type,
64-byte buffer, Poll every 3 ms Unicode
Characters
Go USB!
Other String
Page 71
MCHPFSUSB Software Framework - Device Descriptor Table -
usb_descriptors.c
Descriptors VID & PID
Class Specific /* Device Descriptor */
ROM USB_DEVICE_DESCRIPTOR device_dsc=
{ 0x12, // Size of this descriptor in bytes
USB_DESCRIPTOR_DEVICE, // DEVICE descriptor type
0x0200, // USB Spec Release Number
CDC_DEVICE, // Class Code
0x00, // Subclass code
0x00, // Protocol code
EP0_BUFF_SIZE, // Max packet size for EP0,
0x04D8, // Microchip Vendor ID
0x000C, // Product ID ID
…
Page 72
CDC – RS-232 Emulation
PC Computer PIC® Microcontroller
USB Cable
Hyper Terminal CDC
INF File Required (Supplied in MCHPSUSB)
Standard Windows Drivers
Design Considerations:
• ~80 KB/s max
• Bulk Transfers
• PC applications can access the device as though it
is connected to a serial COM port
Page 73
MCHPFSUSB Framework - Polled Program Flow -
Reset main() InitializeSystem()
while(1)
Your application
code
USBDeviceTasks()
ProcessIO()
USB Stack
Cooperative
Multitasking!!
No blocking
functions.
Use state
machine.
You edit UserInit()
Function
Services
CDCTxService()
MSDTasks()
Re-arm OUT Endpoint
(HID & Generic)
Page 74
MCHPFSUSB Framework - Interrupt Program Flow -
Reset main() InitializeSystem()
while(1)
Your application
code ProcessIO()
You edit
UserInit()
USB Interrupt
Context
USBDeviceTasks()
USBDeviceAttach()
Function
Services
Notifies the stack
when the device is
attached
CDCTxService()
MSDTasks()
Re-arm OUT Endpoint
(HID & Generic)
Page 75
Código de Ejemplo
#include “Compiler.h”
#include “USB\usb.h”
#include “USB\usb_function_cdc.h”
#include “HardwareProfile.h”
void UserInit(void){
…
…
}
void ProcessIO(void){
if((USBDeviceState < CONFIGURED_STATE)||(USBSuspendControl==1)) return;
…
…
CDCTxService();
}
static void InitializeSystem(void){
#if define …
#endif
UserInit();
USBDeviceInit();
}
int main(void){
InitializeSystem();
USBDeviceAttach();
while(1){
ProcessIO();
}
}
Main.c
Needed (usb_config.h is called by usb.h)
Put your initialization code here
Put your application code (state machine) here
No need to change
Conditional compiling
(no need to change)
USBDeviceTasks()
is executed in an ISR
(High Priority PIC18, _USB1Interrupt()
PIC24 & PIC32)
Page 76
Agenda
• Base del Conocimiento
– Diagramas de Bode
– Diseño de Filtros Analógicos
– Diseño de un Electrocardiograma
– Microcontrolador PIC con Labview
• Motor de Inferencia
– Técnicas de Diagnóstico de un ECG
• Medios de Comunicación
– Prototipo de un ECG
GLCD
Page 77
Acerca del ECG-UDH
Page 78
Pantallas Gráficas LCD (GLCD)
RA0/AN02
RA1/AN13
RA2/AN2/VREF-/CVREF4
RA3/AN3/VREF+5
RA4/T0CKI/C1OUT/RCV6
RA5/AN4/SS/LVDIN/C2OUT7
RA6/OSC2/CLKO14
OSC1/CLKI13
RB0/AN12/INT0/FLT0/SDI/SDA33
RB1/AN10/INT1/SCK/SCL34
RB2/AN8/INT2/VMO35
RB3/AN9/CCP2/VPO36
RB4/AN11/KBI0/CSSPP37
RB5/KBI1/PGM38
RB6/KBI2/PGC39
RB7/KBI3/PGD40
RC0/T1OSO/T1CKI15
RC1/T1OSI/CCP2/UOE16
RC2/CCP1/P1A17
VUSB18
RC4/D-/VM23
RC5/D+/VP24
RC6/TX/CK25
RC7/RX/DT/SDO26
RD0/SPP019
RD1/SPP120
RD2/SPP221
RD3/SPP322
RD4/SPP427
RD5/SPP5/P1B28
RD6/SPP6/P1C29
RD7/SPP7/P1D30
RE0/AN5/CK1SPP8
RE1/AN6/CK2SPP9
RE2/AN7/OESPP10
RE3/MCLR/VPP1
U2
PIC18F4550
X1CRYSTAL
C1
22pF
C2
22pF
1
2
3
4
5
ICSP 1-5
CONN-SIL5
MCLR
PGD
PGC
MCLR
PGC
PGD
1
2
3
4
AN 4-3-ECG
CONN-H4
CS
11
CS
22
GN
D3
VC
C4
V0
5R
S6
R/W
7E
8D
B0
9D
B1
10
DB
211
DB
312
DB
413
DB
514
DB
615
DB
716
RS
T17
-Vo
ut
18
LCD2AMPIRE128X64
CS1
CS2
CS
1
CS
2
DI
DI
RW
E
RST
RWE
RS
T
1 2
3
RV410k
1 2 3 4 5
J2CONN-SIL5
U2(RC0/T1OSO/T1CKI)
R410k
1
2
6
5
Pasa Bajas
60dB/dec
60dB/dec
R23
20k
R24
10k
R25
10k
R26
25K
R27
25k
R28
25k
R29
25k
R30
25K
R31
25k
R32
10K
R33
390K
R34
390K R35
249
R36
249
U9
OPAMP
U10
OPAMP
INA114J4(1)
J4(2)
U11
OPAMP
V-
V+V+
V-
V+
V+
V-
V-
3
2
1
411
U6:A
TL084
5
6
7
411
U6:B
TL084
R2
80k
R6
80k
R7160k
C6100nF
C724nF
R580k
C847nF
R8
80k
V-
V+
V+
V-
R9160k
R10636k
R11636k
C9
10uF
C10
10uF
C11
10uF
R12318k
R13
318k
Pasa Altas
V-
V+
V-
V+
1
2
3
J4
TBLOCK-I3
C31uF
R1
10k
D1
1N5817
TR1
TRAN-2P3S
BR1
W005G
C41000uF
25V
C51000uF
25V
VI2
VO3
GN
D1
U37909
VI1
VO3
GN
D2
U57809
C12100nF
C13100nF
C14100uF
16V
C15100uF
16V
C16100nF
C17100nF
VI1
VO3
GN
D2
U77805
VD
D
C18100uF
16V
C19100nF
V1VSINE
V+
V-
10
9
8
411
U6:C
TL084
12
13
14
411
U6:D
TL084
VD
D
V-
V+
VCC1
D+3
D-2
GND4
J3
USBCONN
3
2
1
84
U4:A
LF353
5
6
7
84
U4:B
LF353
A
B
C
D
FUENTE DE ALIMENTACION +/- 9V y 5V
3
2
6
74 8
1
U1
OP07V+
3
2
6
74 8
1
U8
OP07
V-
R3
10k
R14
10k
SUMADOR
Page 79
Características de los GLCD
Page 80
Controladores GLCD para Escribir Byte 0xAB
Page 81
Instrucciones del Controlador GLCD
Page 82
Diagrama de Bloque del Controlador GLCD
Page 83
Código del Proyecto ECG
Page 84
Agenda: UDH Rumbo a la Acreditación Internacional