BT/BP AB/CO/MI 5th February 2008
Safe Machine ParametersRealisation & Status
Safe Machine Parameters System 2 of 42 [email protected]
Realising the SMP
2. Evolution to the Proposal- Basic Architecture- Enhanced Architecture
3. Electrical Realisation- CISP Back Panel- CISX Base Board
1. Safe Machine Parameters Overview- Basics- Piggy-Back on GMT
4. Partition of workload- January 2008
Safe Machine Parameters System 3 of 42 [email protected]
Realising the SMP
2. Evolution to the Proposal- Basic Architecture- Enhanced Architecture
3. Electrical Realisation- CISP Back Panel- CISX Base Board
1. Safe Machine Parameters Overview- Basics- Piggy-Back on GMT
4. Partition of workload- January 2008
Safe Machine Parameters System 4 of 42 [email protected]
Safe Machine Parameters
Several Safety Critical flags and values are needed around the LHC (see Bruno)
-Initially a dedicated high-dependability communications system was proposed
-it became clear that this would be a huge system having lots of infrastructure to maintain
-finally it was decided to send these signals through the CERN General Machine Timing (GMT)
The signals are generated externally and pushed into the GMT generator (CTG) …
They are queued…
They are sent…
They are received all around the machine… (in a CTRV or CTRP)
Safe Machine Parameters System 5 of 42 [email protected]
Good motivation for GMT
Comms Errors
Transmission System(GMT)
Data to be sent by the Safe Machine Parameters
Data at Front Ends
Use the Transmission System as a black box
Data given to GMT could be wrong
GMT could corrupt data
Front-End could corrupt data
Safe Machine Parameters System 6 of 42 [email protected]
Good motivation for GMT
Comms Errors
Data given to GMT could be wrong
GMT could corrupt data
Front-End could corrupt data
Make a dependable source
Read-back and compare to source
Bit Error Rate of GMT can be calculated
Mean Time to Fail estimated
Failure Mode estimated
Safe Machine Parameters System 7 of 42 [email protected]
Realising the SMP
2. Evolution to the Proposal- Basic Architecture- Enhanced Architecture
3. Electrical Realisation- CISP Back Panel- CISX Base Board
1. Safe Machine Parameters Overview- Basics- Piggy-Back on GMT
4. Partition of workload- January 2008
Safe Machine Parameters System 8 of 42 [email protected]
The basic function of the SMP…
Intensity
Energy
FLAG GENERATOR
Flags
Energy FRAMETRANSMITTER
Frames
Intensity
DATA RECEIVER
Intensity
Energy
Mode
Direct Flags
n
Safe Machine Parameters System 9 of 42 [email protected]
The first step is to accommodate multiple data sources to increase dependability…
DATA RECEIVERDATA
RECEIVERDATA RECEIVER
Intensity
Energy
FLAG GENERATOR
Flags
Energy FRAMETRANSMITTER
Frames
IntensityDATA
RECEIVERAIntensity
Energy
Mode
n
n
n
n
Direct Flags
n
Safe Machine Parameters System 10 of 42 [email protected]
Then duplicate the critical processes
FLAG GENERATOR
DATA RECEIVERDATA
RECEIVERDATA RECEIVER
Intensity
Energy
FRAMETRANSMITTER
FramesDATA
RECEIVERIntensity
Energy
Mode
n
n
FLAG GENERATOR
A
Direct Flagsa
n
Direct Flagsb
n
Flagsb
Flagsa
Energya
Intensitya
Energyb
Intensitybn
n
Safe Machine Parameters System 11 of 42 [email protected]
The transmitter must then arbitrate the data from the two sources
FLAG GENERATOR
DATA RECEIVERDATA
RECEIVERDATA RECEIVER
Intensity
EnergyFLAG
GENERATORA
ARBITER FramesDATA
RECEIVERIntensity
Energy
Mode
n
n
Direct Flagsa
n
Direct Flagsb
n
Flagsb
Flagsa
Energya
Intensitya
Energyb
Intensityb
n
n
Safe Machine Parameters System 12 of 42 [email protected]
Finally the output GMT must be cross-checked with the original data
FLAG GENERATOR
DATA RECEIVERDATA
RECEIVERDATA RECEIVER
Intensity
EnergyFLAG
GENERATORA
ARBITER FramesDATA
RECEIVERIntensity
Energy
Mode
n
n
Direct Flagsa
n
Direct Flagsb
n
Flagsb
Flagsa
Energya
Intensitya
Energyb
Intensityb
GMT
DATA RECEIVERDATA
RECEIVERDATA RECEIVER Intensity
Energy
DATA RECEIVER
Flags
FramesCROSS
CHECKER
Direct Flag
n
n
Safe Machine Parameters System 13 of 42 [email protected]
Finally the output GMT must be cross-checked with the original data
FLAG GENERATOR
DATA RECEIVERDATA
RECEIVERDATA RECEIVER
Intensity
EnergyFLAG
GENERATORA
ARBITER FramesDATA
RECEIVERIntensity
Energy
Mode
n
n
Direct Flagsa
n
Direct Flagsb
n
Flagsb
Flagsa
Energya
Intensitya
Energyb
Intensityb
GMT
DATA RECEIVERDATA
RECEIVERDATA RECEIVER Intensity
Energy
DATA RECEIVER
Flags
FramesCROSS
CHECKER
Direct Flag
n
n
Safe Machine Parameters System 14 of 42 [email protected]
Realising the SMP
2. Evolution to the Proposal- Basic Architecture- Enhanced Architecture
3. Electrical Realisation- CISP Back Panel- CISX Base Board
1. Safe Machine Parameters Overview- Basics- Piggy-Back on GMT
4. Partition of workload- January 2008
Safe Machine Parameters System 15 of 42 [email protected]
Flag Generation
FLAG GENERATOR
DATA RECEIVERDATA
RECEIVERDATA RECEIVER
Intensity
EnergyFLAG
GENERATORA
ARBITER FramesDATA
RECEIVERIntensity
Energy
Mode
n
n
Direct Flagsa
n
Direct Flagsb
n
Flagsb
Flagsa
Energya
Intensitya
Energyb
Intensityb
GMT
n
n
Frame Receiver – CISR
Flag Generator – CISG
Generator Arbiter – CISA
Safe Machine Parameters System 16 of 42 [email protected]
Flag Cross-Checking
GMT
DATA RECEIVERDATA
RECEIVERDATA RECEIVER Intensity
Energy
DATA RECEIVER
Flags
FramesCROSS
CHECKER
Direct Flag
SMP Transmission Cross-Checker – CISC
Timing Receiver - CTRV
Safe Machine Parameters System 17 of 42 [email protected]
A Standard VME Chassis
Has 21 Slots!
A summary of those devices shown on the previous slides
Frame Receiver – CISRFlag Generator – CISG
Generator Arbiter – CISAGenerator Arbiter B - CISB
SMP Transmission Cross-Checker – CISCChassis Debugger – CISDTiming Receiver - CTRV
Safe Machine Parameters System 18 of 42 [email protected]
A Standard VME Chassis
Has 21 Slots!
A summary of those devices shown on the previous slides
Frame Receiver – CISRFlag Generator – CISG
Generator Arbiter – CISAGenerator Arbiter B - CISB
SMP Transmission Cross-Checker – CISCChassis Debugger – CISDTiming Receiver - CTRV
Generator Arbiter B – CISBCan link SPS SMP System to the LHC GMT
Can link the LHC SMP System to the SPS GMT
SMP
Phase IV
Safe Machine Parameters System 19 of 42 [email protected]
A Standard VME Chassis
Has 21 Slots!
Frame Receiver – CISRFlag Generator – CISG
Generator Arbiter – CISAGenerator Arbiter B - CISB
SMP Transmission Cross-Checker – CISCChassis Debugger – CISDTiming Receiver - CTRV
X4 (side by side)X2 (after CISR)X1 (after CISG)X1 (after CISG)X1 (after CTRV)
X2 (gen and check)X3
14 slots used
Safe Machine Parameters System 20 of 42 [email protected]
The rules of engagement
Several PCBs will be needed
1. rely on existing technology and ideas. Don’t reinvent the wheel!2. See 1.
3. Diagnosis and Monitoring needed4. Test modes needed
5. System will be in one location, no need for remote update6. System will be built twice (plus spares) manufacturability NOT hugely critical
7. CPLD / FPGA technology = good8. VHDL/Schematic Entry = good
9. Displays / debugging access = good10.Elegant design, robust and ergonomic = good
11.PCAD = good12.Design office = not so good
12b. Documentation is very very good.
Safe Machine Parameters System 21 of 42 [email protected]
CISP - Backplane
Everything fits into a single VME Chassis
1. Is the P2 backplane idea a necessity?
2. Is it possible to reduce the complexity of the system by integration?
3. Is it possible to use a single board for the base of the system?
YES!
YES!
YES!
Safe Machine Parameters System 22 of 42 [email protected]
Fram
e R
ecei
ver –
CIS
RSL
OT 2
Fram
e R
ecei
ver –
CIS
RSL
OT 3
Fram
e R
ecei
ver –
CIS
RSL
OT 4
Fram
e R
ecei
ver –
CIS
RSL
OT 5
SLO
T 6
SLO
T 7
SLO
T 8
SLO
T 9
Flag
Gen
erat
or –
CIS
G
Flag
Gen
erat
or –
CIS
G
Gen
erat
or A
rbiter
– C
ISA
SLO
T 1
0
SMP B
IC Int
erfa
ce –
CIS
B
SLO
T 1
1
SLO
T 1
4
SLO
T 1
5
SLO
T 1
8
SLO
T 1
9
SMP T
rans
mis
sion
Cro
ss-C
heck
er –
CIS
C
A B
2
B C D
SLO
T 1
Pow
er P
C
Cha
ssis
Deb
ugge
r –
CIS
D
Tim
ing
Rec
eive
r –
CTR
V (I
NTEN
SITY
1)
SLO
T 1
4
Tim
ing
Rec
eive
r –
CTR
V (I
NTEN
SITY
2)
SLO
T 1
5
SLO
T 1
6
SLO
T 1
7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
SLO
T 1
2
SLO
T 1
3
SLO
T 2
0
SLO
T 2
1
Cha
ssis
Deb
ugge
r –
CIS
D
Tim
ing
Rec
eive
r –
CTR
V (E
NER
GY
)SL
OT 1
41 3 4 5 6 7 8 9 1110 12 13 14
A
14B9B
CISP Front View
Safe Machine Parameters System 23 of 42 [email protected]
Fram
e R
ecei
ver –
CIS
RSL
OT 2
Fram
e R
ecei
ver –
CIS
RSL
OT 3
Fram
e R
ecei
ver –
CIS
RSL
OT 4
Fram
e R
ecei
ver –
CIS
RSL
OT 5
SLO
T 6
SLO
T 7
SLO
T 8
SLO
T 9
Flag
Gen
erat
or –
CIS
G
Flag
Gen
erat
or –
CIS
G
Gen
erat
or A
rbiter
– C
ISA
SLO
T 1
0
SMP B
IC Int
erfa
ce –
CIS
B
SLO
T 1
1
SLO
T 1
4
SLO
T 1
5
SLO
T 1
8
SLO
T 1
9
SMP T
rans
mis
sion
Cro
ss-C
heck
er –
CIS
C
A B
2
B C D
SLO
T 1
Pow
er P
C
Cha
ssis
Deb
ugge
r –
CIS
D
Tim
ing
Rec
eive
r –
CTR
V (I
NTEN
SITY
1)
SLO
T 1
4
Tim
ing
Rec
eive
r –
CTR
V (I
NTEN
SITY
2)
SLO
T 1
5
SLO
T 1
6
SLO
T 1
7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
SLO
T 1
2
SLO
T 1
3
SLO
T 2
0
SLO
T 2
1
Cha
ssis
Deb
ugge
r –
CIS
D
Tim
ing
Rec
eive
r –
CTR
V (E
NER
GY
)SL
OT 1
41 3 4 5 6 7 8 9 1110 12 13 14
A
14B9B
CISP – P2 Connectors
Safe Machine Parameters System 24 of 42 [email protected]
CISP – Burndy Connectors
Safe Machine Parameters System 25 of 42 [email protected]
CISP – Burndy ConnectorsLocal Flags
(for connections to the Beam Interlock System)
8 flags from the Generators Internal Flags for Failure
Safe Machine Parameters System 26 of 42 [email protected]
P2 to CISP with CIBEACIBEA is the basis for the design!
5x32 (VME P2)
3x32 (Panel)
8
8
9
9
10
10
2 11
11
2 12
12
3 13
13
3 14
14
4 15
15
4 16
16
5 17
17
5 18
18
6 19
19
6 20
20
21
21
7 22
22
23
23
7
1
41
41
42
42
43
43
44
44
45
45
46
46
40
1 40
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
3
3
3
Z A B C D24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
3
3
3
A B C
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
2
2
3
3
4
4
5
5
6
6
7
7
1
1
41
41
42
42
43
43
44
44
45
45
46
46
40
40
23
23
39
39
92 signals = 46 differentials
Safe Machine Parameters System 27 of 42 [email protected]
CISX – A Standard PCB
The requirements can be accommodated on a single PCB…
1. We must determine the topology of the Programming Chain
2. We must determine the use of PROM/FLASH/CPLD for Thresholds-How is it accessed-How is it checked
-How is it updated in the field-How do we guard against Single Event Upsets
(Grey Counters or Hardware etc)
3. Non-Volatile storage of History Buffer done at the same time
4. Nice display option for EVERY card.
Good for debug
Safe Machine Parameters System 28 of 42 [email protected]
CISX
VME 64x P15x32 Connector
VME 64x P25x32 Connector
Standard 160, 6U board
Safe Machine Parameters System 29 of 42 [email protected]
CISX
VME Electrical Interface & Power Supply
VME 64x P15x32 Connector
VME 64x P25x32 Connector
1v2 1v8
2v5
5V 3V3
Standard Power Supply Circuits
Standard VME Interface ICs
Safe Machine Parameters System 30 of 42 [email protected]
CISX
FPGA and PROM, JTAG and Display
VME 64x P15x32 Connector
VME 64x P25x32 Connector
1v2 1v8
2v5
5V 3V3
Standard Power Supply Circuits
Standard VME Interface ICs
Address IndicatorsSlot IndicatorsCard Name etcLEDs
& LEMOs 00
JTAG and Display
Jumpers
PROM
FPGAHigh-end
Configuration PROM
FPGA
JTAG ForwardTerminations& LS14 Buffer
Local or Loop JTAG Configuration Jumpers
Safe Machine Parameters System 31 of 42 [email protected]
CISX
RS422 / Clocks/ Remote Update
VME 64x P15x32 Connector
VME 64x P25x32 Connector
1v2 1v8
2v5
5V 3V3
Standard Power Supply Circuits
29 ConfigurableDifferential Rx/Tx
PossibleTerminations
CPLD
Standard VME Interface ICs
Remote UpdateCPLD
Address IndicatorsSlot IndicatorsCard Name etcLEDs
& LEMOs 00
JTAG and Display
Jumpers
PROM
FPGAHigh-end
Configuration PROM
FPGA
JTAG ForwardTerminations& LS14 Buffer
Local or Loop JTAG Configuration Jumpers
4 High Speed Configurable
Differential Clock Buffers
Safe Machine Parameters System 32 of 42 [email protected]
CISX
Current Loops and terminations
VME 64x P15x32 Connector
VME 64x P25x32 Connector
1v2 1v8
2v5
5V 3V3
Standard Power Supply Circuits
29 ConfigurableDifferential Rx/Tx
PossibleTerminations
CPLD
Standard VME Interface ICs
Remote UpdateCPLD
Address IndicatorsSlot IndicatorsCard Name etcLEDs
& LEMOs 00
JTAG and Display
8 Current Loops= 4 User Interfaces
Jumpers
PROM
FPGAHigh-end
Configuration PROM
FPGA
Single Ended Input
Terminations
JTAG ForwardTerminations& LS14 Buffer
Local or Loop JTAG Configuration Jumpers
4 High Speed Configurable
Differential Clock Buffers
Configuration Terminations
Safe Machine Parameters System 33 of 42 [email protected]
CISX
FLASH
VME 64x P15x32 Connector
VME 64x P25x32 Connector
1v2 1v8
2v5
5V 3V3
Standard Power Supply Circuits
29 ConfigurableDifferential Rx/Tx
PossibleTerminations
CPLD
Standard VME Interface ICs
Remote UpdateCPLD
Address IndicatorsSlot IndicatorsCard Name etcLEDs
& LEMOs 00
JTAG and Display
8 Current Loops= 4 User Interfaces
Jumpers
PROM
FPGAHigh-end
FLASH/CPLD(ROM)
Configuration PROM
FLASH / CPLD
FPGA
Single Ended Input
Terminations
JTAG ForwardTerminations& LS14 Buffer
Local or Loop JTAG Configuration Jumpers
4 High Speed Configurable
Differential Clock Buffers
Configuration Terminations
Safe Machine Parameters System 34 of 42 [email protected]
CISX
Display
VME 64x P15x32 Connector
VME 64x P25x32 Connector
1v2 1v8
2v5
5V 3V3
Standard Power Supply Circuits
29 ConfigurableDifferential Rx/Tx
PossibleTerminations
CPLD
Standard VME Interface ICs
Remote UpdateCPLD
Address IndicatorsSlot IndicatorsCard Name etcLEDs
& LEMOs 00
JTAG and Display
8 Current Loops= 4 User Interfaces
Jumpers
PROM
150 pin CIBSD connector
FPGAHigh-end
FLASH/CPLD(ROM)
Configuration PROM
FLASH / CPLD
FPGA
Single Ended Input
Terminations
JTAG ForwardTerminations& LS14 Buffer
Local or Loop JTAG Configuration Jumpers
4 High Speed Configurable
Differential Clock Buffers
Configuration Terminations
Safe Machine Parameters System 35 of 42 [email protected]
CISX
50-Ohm Inputs
VME 64x P15x32 Connector
VME 64x P25x32 Connector
1v2 1v8
2v5
5V 3V3
Standard Power Supply Circuits
29 ConfigurableDifferential Rx/Tx
PossibleTerminations
CPLD
Standard VME Interface ICs
Remote UpdateCPLD
Address IndicatorsSlot IndicatorsCard Name etcLEDs
& LEMOs 00
JTAG and Display
8 Current Loops= 4 User Interfaces
Jumpers
16 LEMO 0016 LED availableInstead of CIBO
On PCB
PROM
150 pin CIBSD connector
FPGAHigh-end
FLASH/CPLD(ROM)
Configuration PROM
FLASH / CPLD
FPGA
Single Ended Input
Terminations
JTAG ForwardTerminations& LS14 Buffer
Local or Loop JTAG Configuration Jumpers
4 High Speed Configurable
Differential Clock Buffers
Configuration Terminations
Safe Machine Parameters System 36 of 42 [email protected]
CISX
CIBO
VME 64x P15x32 Connector
VME 64x P25x32 Connector
1v2 1v8
2v5
5V 3V3
Standard Power Supply Circuits
29 ConfigurableDifferential Rx/Tx
PossibleTerminations
CPLD
Standard VME Interface ICs
Remote UpdateCPLD
Address IndicatorsSlot IndicatorsCard Name etcLEDs
& LEMOs 00
JTAG and Display
8 Current Loops= 4 User Interfaces
4 CIBO
Jumpers
16 LEMO 0016 LED availableInstead of CIBO
On PCB
PROM
150 pin CIBSD connector
FPGAHigh-end
FLASH/CPLD(ROM)
Configuration PROM
FLASH / CPLD
FPGA
Single Ended Input
Terminations
JTAG ForwardTerminations& LS14 Buffer
Local or Loop JTAG Configuration Jumpers
4 High Speed Configurable
Differential Clock Buffers
Configuration Terminations
Safe Machine Parameters System 37 of 42 [email protected]
CISX – A Standard PCB
Three Different Assemblies
CISR – Safe Machine Parameter Receiver CISG – Parameter GeneratorCISA – SMP Arbiter
CISC – Cross-CheckerCISD – Debugger Card
1v2 1v8
2v5
5V 3V3
PROM
FPGAHigh-end
1v2 1v8
2v5
5V 3V3
CPLD
PROM
FPGAHigh-end
FLASH/CPLD(ROM)
1v2 1v8
2v5
5V 3V3
CPLD
PROM
FPGAHigh-end
FLASH/CPLD(ROM)
FLASH/CPLD(ROM)
CISB – Beam Interlock Interface
Safe Machine Parameters System 38 of 42 [email protected]
Time-Scale
Phase I – Deadline October / November 2007Specify I/O of ChassisSpecify Internal Layout of ChassisSpecify Electrical Level Architecture for Whole ChassisBuild simple Prototype based in the LAB
Phase II – Deadline February / March 2008Expand Prototype to include redundancyDevelop Fail-safe, Monitoring and Test Mode in the LAB and SPS
Phase III – Deadline Summer 2008Include all Safety AspectsInclude all FESA type MonitoringIn the LAB, SPS and when completed roll out to LHC
Phase IV – Deadline Summer 2009Include revisions for operations.Already know we have to connect SPS -> LHC and vice-versa
SMP 1v0
SMP 2v0
SMP 3v0
Safe Machine Parameters System 39 of 42 [email protected]
Time-Scale
Phase I – Deadline October / November 2007Specify I/O of ChassisSpecify Internal Layout of ChassisSpecify Electrical Level Architecture for Whole ChassisBuild simple Prototype based in the LAB
Phase II – Deadline February / March 2008Expand Prototype to include redundancyDevelop Fail-safe, Monitoring and Test Mode in the LAB and SPS
Phase III – Deadline Summer 2008Include all Safety AspectsInclude all FESA type MonitoringIn the LAB, SPS and when completed roll out to LHC
Phase IV – Deadline Summer 2009Include revisions for operations.Already know we have to connect SPS -> LHC and vice-versa
SMP 1v0
SMP 2v0
SMP 3v0
Safe Machine Parameters System 40 of 42 [email protected]
Realising the SMP
2. Evolution to the Proposal- Basic Architecture- Enhanced Architecture
3. Electrical Realisation- CISP Back Panel- CISX Base Board
1. Safe Machine Parameters Overview- Basics- Piggy-Back on GMT
4. Partition of workload- January 2008
Safe Machine Parameters System 41 of 42 [email protected]
Who is doing what?
Frame Receiver – CISR - AlexFlag Generator – CISG - Ben
Generator Thresholds Board - IvanGenerator Arbiter – CISA - Alex
Generator Arbiter B - CISBSMP Transmission Cross-Checker – CISC
Chassis Debugger – CISD - Bertrand
We are on track… SMP 1v0 was done (electrically sound). SMP 2v0 is in the pipeline (4 CISX & 2 Chassis here next week)
Safe Machine Parameters System 42 of 42 [email protected]
FIN
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