IEEE TRANSACTIONS ON COMPUTER-AIDED IIESIGN OF I N T E G K A T t l l ClKCUlTS A N D SYSTEMS. VOL. 17. NO I . J 4 N I I A K Y IS93 59

Formal Definitions of Edge-Based Geometric Design Rules

Kjell 0. Jeppson, Senior Member, IEEE, Sven Christensson, Member-, IEEE. and Nils Hedenstierna, Member, IEEE

Abstract-A structured method for geometric design rule def- initions is presented in terms of edge-based constraints. Using this approach, intralayer design rules such as width and spac- ing of single layers, and interlayer design rules such as clear- ance, margin, extension, and overlap of two different layers can be specified in terms of two high-level design rule macros only. The tedious and complicated task of specifying detailed design rules in the technology file is thereby eliminated and replaced by a simple macro rule file giving a much better overview of the design rules. Efficient rule compilers have been developed to expand these macro descriptions of the design rules into basic checks for Magic and for corner-based design rule checking. As an example, the MOSlS scalable CMOS design rule set can be described in terms of the two design rule macros only. More complicated design rules, such as conditional and conjunctive design rules, are also discussed.

I . I N T R O D U C T I O N

NY PHYSICAL layout of an integrated circuit has to A follow a set of geometrical design rules typical of the particular fabrication process. Geometric design rules are imposed by the limitations of the integrated-circuit fab- rication process and describe the minimum geometric constraints necessary for a certain yield in production. Typical design rules imply a minimum width of geometric regions or a minimum space to other geometric regions in the same or different mask layers.

Most VLSI designers are familiar with the Mead and Conway [ l ] descriptions of design rules as arrows repre- senting the minimum measures between geometric re- gions. Despite the fact that design rules are considered a trivial problem and a consensus about the meaning of a design rule seems to have emerged between semiconduc- tor manufacturers and CAD system vendors, exact defi- nitions of the geometric design rules in terms of easily accessible, descriptive terms have not been published in the scientific literature. A formal approach to design rule checking has been published by Modarres and Lomax [ 2 ] , in which they lay a mathematically correct foundation for geometric design rule analysis. A less formal but equally

Manuacript received January 29, 1991: revised April 7, 1992. Thi \ work was supported in part by the Swedish National Board for Technical Devel- opment (STU). This paper was recommended by Associate Editor R . H . J . M. Otten.

The authors are with the Department of Solid-Slate Electronics. Chal- mers University of Technology. S-412 96 Gdteborg. Sweden.

IEEE Log Number 9202986.

powerful format for geometric design rule description was presented by Taylor and Ousterhout [3]. Nevertheless, the geometrical problem of defining unambiguous interlayer design rules between two mask layers has not been ana- lyzed before in the literature.

Exact definitions of geometric design rules would fa- cilitate the use of design rule macros where design rules are described in a high-level format. The use of such macros for design rule specification would considerably simplify the adaption of a design rule checker (DRC) to different processes. However. the design rules must be clearly defined, since in using macros there is no longer room for ad hoc adjustments.

There are many areas where the need for exact and un- ambiguous design rule definitions is encountered. One is the EUROCHIP environment, where any design tool can be used but the designs have to comply with the manu- facturers’ design rules. Usually, the manufacturer sup- plies the technology file containing the design rules. The manufacturer then either has to support these files for many different design systems or the designer must use a design system recommended by the manufacturer. The al- ternative is to make one’s own implementation of the de- sign rules by interpreting graphical representations sup- plied by the manufacturer. When the circuit is sent for processing. the manufacturer runs a recheck using his own DRC and the customer has to pay again for this CPU- intensive process. Eventually, after a number of ad hoc adjustments. the two DRC’s are calibrated against each other.

Similar problems are encountered in the university en- vironment in adapting Magic’s DRC [3] to different pro- cesses. Magic’s own rule compiler is far from exploiting the inherent power of Magic’s descriptive rule format.

We encountered the need for strict design rule defini- tions while developing corner-based hierarchical DRC’s. Because of its locality, corner-based design rule checking can be used to check small areas of layout independently. This makes corner-based design rule checking, suggested by Arnold and Ousterhout [4]. ideal for hierarchical de- sign rule checking. However, corner-based design rule specifications are cumbersome to make and one might easily be lost in details. However, this problem is elimi- nated once and for all if strict design rule definitions are specified in declarative terms and made use of by a high- level rule compiler.

In Section I 1 we introduce an edge-based rule tormat t o pre se n t such de sc rip t i v e d e fi n i t ions of g eo met ri c des i g n rules, Using this format. design rules can be described a4

a collection of geometric constraints bet\vcen the edges of geometric regions in the layout of an integrated circuit. Of particular interest are the interlayer design rules. Here. we have replaced the low-level macros for spacing. cn- closure. and extension with one interla) er macro contain- ing all the necessary parameters. All interlayer design rules that are not con-junctive or conditional can he de- scribed using this rule description. as xhoun in Section 111. More complicated geometric dcsign rules. such as conjunctive and conditional rules. are considered in Sec- tion IV and an extension of the rule format i \ discussed.

Once the matter of defining the geometric design rule\ is settled. design rule compilers can be dc\eloped to e x - pand these macros into the neccssar! operations o f the DRC. For region-based DRC's. the macros arc expanded into procedures of Boolean operations bet\\een mash la! ~

ers. For edge-based and corner-based DRC's. the rule compiler attaches constraints to the endpoints of thc spec- ified edges. The problem of identifying corners that are forbidden as u ~ l l as corners t o \vhich tolerance tests applq is the same. whether or not Boolean m u \ h operation5 o r corner-matching processes are usecl.

Two examples of rule compilers t o r Magic and corncr- based design rule checking are shown i n Section V . Magic has been chosen because o f its widespread use in uni\cr- sity environments and because of the simplicity \+ i t t i which our definitions can be translated i n t o Magic's OM n rule format. Corner-based design rule checking ha\ been chosen to support our pro-ject on hierarchical VLSI circuir verification. Using the halo algorithm IS] i n conjunction with corner-based design rule checking. hierarchical DRC's can be developed. allowing unrestricted use ot overlapping subcells. Through the development of the rulc compiler. the ma.jor objection to corner-based design rulc checking is removed. However. it is be!ond the scopc of' this paper to demonstrate the perforniance o f corner-based design rule checking. and w e refer to thc reader to othcr publications [SI-[ I O ] .

11. R L 1.1. Foi<\l.\ I

A layout of a VLSI circuit is a collection of geometric primitives. Following the formalisin of' Modal-res and Lo- niax [?]. a geometric primitive. o r simpl! primiti\,e. in ;I

Manhattan layout is a rectangle. For non-Manhattan la) - outs. their formalism can be expanded to trapemids. However, for the sake of simplicit) i n dctining geometric design rules. Manhattan layout \vi11 he assumed i n this paper.

A layout layer. o r simply layer. is a set of primitives. New layers can be derived bq performing Boolean oper- ations ('ANL). O K . ~ 0 1 . ) on the areas coLered bq primitiies of existing layers. Two layer5 arc said to he nonolcrlap- ping i f the AXI ) opcration pertormed oii the tuo layer\ results in the einpt) set (a).

A priri1itii.e has lOur edges. 111 a layout, some parts of thew edges are co\,ered b! other primitives in the saiiie layer t'orniing a geometric shape. \I hilc other parts he- come the edges of the geometric shape. The name of an cdge of' a geometric shapes is delincd as follows.

IIc;fi/ii/io/i 1; Any part 01' 311 edge o f a primitive in type1 that is touched bk ;I priniiti\,e in typc2. where type? i \ a nonoverlapping lahcr ( t ) pel ri/itl type2 = 3 1. is

I n a type 1 /t! pe2 edge. the t! pc I laker is said to appear on the inside of the edge and thc type2 layer is said to appear on the outside of the edge. As an example. the e d z ~ s ot' geometric shape4 i n la!er '-1 can be described as

There arc basicall) t \+o t j pe5 of geometric design rules that apply to edges. ancl thc) are the restricted separation between two edge5 and the torhiclden edge.

f l c $ / i i r i o r i 2: '4 geometric design rule either prescribes ;I re4rricted separation bct\\cen pair4 of edges of a coiii- iiion la>.er o r simplj forbids i i i i edge to appear in the

The rc\triction can hc ;I niiniinurn. maximum. o r exact wparation. A restriction between t! pe 1 /type2 and type31 (pe2 edges is illu\tratecl i n Fi?. 1

Examples of restricted wparationx between pairs of edges ~ i r c the i i i i n i n i u n i \\ i J t h arid minimum spacing rules o f metal wire5 a n c l the exact s i / e rules for contact5 and \ ias. Eumple4 ot i'orbiddcn ctlges are the contact and via edge\ that mu\t not appear \\ ithout the contacting layers.

Dcifi/ri/io/r 3: I n ii ininimuiii (riiaxiiiiuiii) separation rule h e t \ + c ~ 1 1 t \ \ o edges. each of the edge> has a ( ~ o / ~ . ~ / ~ ( ~ i / ~ ~ /.c,,y,io/r \ i i t h in v, hich thc othcr edge must not (must) appear. , _

Thc constraint region o t ; i n edgc for a certain design rule i x a rectangle placed along the outside of the edge. Thc LS iclth of the rectangle. perpendicular to the edge. is gi\en by the scpar;ition nic;istire i t ' of the design rule. For design rules that should onl! hc checked perpendicular to the edge. the length of the constriiini region is that o f the edge. Howe\,er. \oiiie de5ign rtilcs should also be checked cliagonallq from the endpoint o f the edge and then the con- straint region inust be extended bt.!oncl the endpoint. The con4traint region cxtenxion can casil) be adapted f o r both Manhattan and Euclidean nietric5. ;ix shown in Fig. 2. For Manhattan metric. the con\traiiit regions of ;I primiti\ e torn1 a set o f rectangles consistcnt \L i th the purticil cJ.qxl/i- j i o / r , j c ' r introduced b j Motlarrcs and Loinax 121.

If ;I gconictric design rulc prescribes a minimum sepa- ration betueen t) pc l 'tb.pe2 edges iiiid type3itype2 edges. neither edge must appear in4idc the constraint region of the othcr- edge. For mo\t ctc\ign I-LII~ sets. type3 can be

~ ~~. i~allcd a t> pc 1 . t) pe2 cdgc.

I !'.l-eciges.

I q o L I l . 1 -

JEPPSON P / [i / EDGE-BASED GEOMETRIC DESlGK KULFS 61

t V D 0 3

t y p e 2 minimum-distance

type<

Fig. 1 . Illustration of a restricted separation hctac.cn two e d g e of a coni mon layer.

Fig. 3 . The con\traint rcgions 01 an edge can be confined to the endpoints ol the edge.

F ig , 2, The con\tralnt of ~l certain tqpe ,,f edge l a ) e r A Fig. 1. Design I-ule checking is ;I hidirectional proccaa because design rule violations can he found from the coi-nerr of either geometric region. de- pending on their rcllrtive S I L C and po\itioii.

appears on the inside of the edge

regarded as the forbidden layer of the constraint region of typel/type2 edges and, similarly. typel as the forbidden layer of the constraint region of type3itype2 edges. These views are identical under conditions such that if violations are reported due to type3 or typel edges other than those matching the design rule specification. there are other de- sign rules to justify these violations. These conditions hold for most design rule sets in practical use. and will be de- rived in Section 111-D.

To formally describe a design rule. or rather a design rule violation, we introduce the following edge function:

edge type 1 , type2 [, forbidden-layer, disrunce] [, * ‘con- ment”] [, modifier].

The function is true if primitives of the forbidden-layer intersect the constraint region of the type litype2 edge: otherwise, i t is false. The width of the constraint region is given by disrarzce. By default, the length of the con- straint region is extended by distarzce beyond the endpoint of the edge if, and only if, the endpoint is a convex corner whose both edges match the typelitype2 edge specifica- tion. This condition can be changed by the modifier. If the forbidden layer is omitted, the function is true for all typelitype2 edges. In terms of forbidden layers, the type2 layer defining the edge is the forbidden layer of the design rule as well.

For maximum separation design rules, we use the niod- ifier max, which has the effect of negating the value of the edge function. To forbid concave corners to appear in the layout, we use a second modifier, concave. This mod- ifier overrules the normal condition for extending the con- straint region. Instead. the constraint region is extended beyond all endpoint corners. Concave corners are forbid- den when geometric shapes, such as contacts and vias, must have an exact size. This edge function is very sini- ilar to the one suggested by Taylor and Ousterhout [3 \ . However, while the condition for extending the constraint region must be repeated for each edge in their fcmnat, our edge function is simplified as a result of an attempt to unify design rule definitions. Due to the simplified edge description, the edge function is also more convenient to

use than the formal functions introduced by Modarres and Lomax 121.’

In a practical implementation, the edge-based con- straint regions can be confined to the endpoint corners of the edge as shown in Fig. 3. This is based on the obser- vation that if a design rulc is satisfied at the corners of a design. then it is satisfied everywhere along the edges of the design. However. corners of both edges involved in the design rule must be checked, because violations can bc found from the corners of either geometric shape de- pending on their relative size and position. In Fig. 4, for instance, the design rule violations to the right will not be found if only corners of t?pel/type2 edges are checked. When design rules are checked along the full length of the edge. it is sufficient to check the design rule from one of the two involved edges.

111. INTK..\- AND I N II :KI ,AYER DESIGN RULES A . Introduc~tioti

I n this section we define intralayer design rules, such as the spacing and width restrictions for single layers and interlayer design rules, such as the clearance, margin, ex- tension, and overlap restrictions, using the edge format from Section 11.

The new approach of this work is to collect single-layer design rules into one intralayer macro and all design rules involving two layers into one interlayer macro, instead of using separate, lower level macros for each rule. For in- tralayer rules it may seem immaterial if two separate macros are used for space and width or if they are col- lected into one niacro (with two parameters), however. tor interlayer design rules clarity is increased. This gives a structured approach to the complete interlayer relation-

’A design rule violation spccifecl h) tht. edge function a \ edge type l . type?. 1orhidtlen~l~r! el-. 11’ a ou lc i he specilied bq Modarres and Lomax 121 ‘l s

S , , (R. tqpc l . L ) = l’INTEKSECT(K. COMPLEMENT(PARTITION(R. EDGE(R). t!pe?). R) . II‘ . 1o rh iddc i i~ l ; i~c r )

\ \here R is ;I priiiiitiLc i n 1) pe I and I . I \ the \et of all layers

ship as a whole. The interla>er design rules are i l lu j t ra tec l by several eaaniples.

B. Ii it ta I(r>,o Y Dcsigi i Rir It, Mrr Rcvrrictioii,\

For single laqers two design rules can be gi\.en. spacing and width restrictions. These restriction\ are t! picall! in i n i m u m rest ri c t io ns . but ilia a i i i i ti m rest ri ct i o n s c;i 11 a 150

be given. Minimum and iiiasiiiiunl restrictions c;in a l s o he combined to prescribe an esact si/e 0 1 ' certain shapes. such as contact cuts ancl \ ias. I t is ~ O L I ;I trit ial problenl t o define thew design rules using our edge format. I n 'I

single mask layer .,I o n l ) one t l pe 01' eclgc. . 4 - ( ~ 1 , q t , \ . lirii

iting regions o f laqer -4 . is present. For this edge. spacing is a11 external check a n c l LI idth is a n internal check defined a s fOl lOLI. \ .

Dcfiriiriori 4: Th<> i i i i n i i i i u i i i xpacing ancl minimuni Lvidth rules of a la! e r :I are clcfinecl h! thc edge l'unctions:

edge A . A . .A. .S/Jti~'iil~:

and

edge 2. .4. '4. \r.ic/tli

,ti) i' U'itltli ( i / i d S p i 1 . c

\\ here \ p i c i i i g and \l.irirli arc the mininium spacing and width measures. rc\pccti\.el> .

The corresponding corner c.hecks ;ire s h o \ ~ n i n Figs. 5 and 6. As shown in the figures. the diagonal constraint check is performed for con\'ea cornel-s. but not t'or co11- cave corners. The minimum M idth rule can be conibinccl w i t h the maximum tt idth option to spcci 1) 311 exiict t e ;~ ture si/c f o r shape4 in certain IaLerh. e . g . . contiict cuts a n c l i a x . Exact si/cs are spccitiecl through ;I i i i i i i i n iu i i i

and 21 i i i ; ixiniuii i U idth. bet\ieen ~ h i c h the exact \\ Idrh 15

the onl) allo\ted width. N o concaw cot'nerx :ire a l l o ~ e t l f o r shapes ha \ ing :in exact siLe. This rulc can be checLed b), use o f the concave modifier i n the iiiinimum spiic~ing statement. The following rules are then obtained t'or exact f'ea t U re s ires :

edge 2. .4. 2. \i:c

edge A , 3 . A . . \pr i ( . i / i ,q. concave

where the i t i ( i . t i / / iu i / i - \t,itltli is one grid u n i t larger than the . s i x measure.

l h e s e edge statements can easil) be generated 17) ;I ru le compiler f rom a macro description of the intrala! e r design rule. Thc syntax for this micro could he defined ;is

Single-_layer ( l ( i > , c i . . \t,itl//i. . \ p ~ i ~ ~ ( , . ~~coiiiiiient" I . modi- f ier ] )

where Itr\ .oi- is the layer U hose ~r.itlt/i a n c l . \p i ( ' i r ig iirc to be specified. The a\,uilable modifiers are

_- I !

C ' . / r l t c / ~ l ( i \ ~ c ~ ~ D C \ l qr1 KlilcJ.\

KO\\ le t us l o o k at the relationship between two differ- cnt 1a~c1.s .4 a r i d H .

Lh;/i i i i / io/i .i; Intcrla! er des ign rules between two lay- crh .4 anel B prcsc i~ ihc rttstriction\ on the distance5 between

I-: Since Ia>ei-\ .4 anc l B can appear in f o u r different c o n -

hrnations: .-1B (.I and B ) . :Is (.,l and not B ) . 2 B (not il and not B. TiH ( n o t .4 and B ) . each able to ser\'e as the t! pe-! l;i!cr t i t ' ;I rule ;is shown i n Fig. 1 . there are four interla!cr dcsign ~~ulcs to hc \pecitied. Hence. lhur paran- c'tcrs arc neeclccl. namel! . the clearance. margin. extcn- \io11 and o \c r l ap parameters as illustrated in Fig. 7.

Since there <irt x i x wa)s lo select two out of four . the t'our conibinations 01' layers .4 and B can be bounded by an! of the t'ollo\t ing s i x edges:

1-inside-B ,113 ' 4B

.-1-outsicie-~ -IH ;I H

H-inxicIe-.4 4~ ,iB ~-outsitie-:~ I IH .1 H

in\icle -tot ict i - 1 ~ .I B oLlth1Cle toucl1 .AH . i B .

e c l y 3 OI' .'I ancl eclgch 0 1 ' H .

Dqfiri ir iorr 6: 1 he four interlayer design rules are de- l i 11 ed ;I s re s t r i c I c cl c pa I;l t i o l i s bet w ec 11 t he fo I 1 o \v i ng op- pohin2 4 iind 8 cdgch:

clciiraiicc .I-out\idc-H H-outside-.4

ni;rrgin .l-insidc-R H-outsicte-.,l

c x I e 11 si o 11

( ) \ c rl ap

'4 -()ut s id e- B

. 4 - i n., i d c > - B

H - i n s i de - .4

N- i 11s ide-..l

13) ~ I e l i n i t i o i i cili:ti edge i s in\,ol\ed in two design rule paraincters. I ttc~ch edges. being edges of both layers. arc

niax and exact-width. not i n \ ol\ccl in the definitions o f the interlayer rules. This

63

, clearance I--.I , r i

Fig. 7 . The four parameters. clearance. margin. extcn\ion. and o\er lap. that are needed to specif) the relations between two geometric primilr\cs of different layers.

facilitates the use of m i r i i r m r n distutiw or touch rules and avoids redundant measures that can be specified as intra- layer rules. Touch edges occur when edges of both layers coincide (graze). Touching can occur from the outside (outside-touch) and the inside (inside-touch).

Dejnifion 7: In terms of edge functions, the minimum interlayer design rules for two layers, A and B, are defined by the following statements:

edge AB. AB, AB, clearance

edge AB, A B , AB, clearunce

edge AB, AB. A B . margin

edge AB, AB, AB, margin

edge AB, AB, A B, exterisiori

edge A B , AB. AB, e.xtension

edge AB, AB, AB, o\vrlup

- _ _ -

_ - -

- _ _

edge AB, AB, AB, overlup. r The conditions when Definitions 6 and 7 are consistent

are derived in Section III-D. When specifying the interlayer relationship between

layers A and B, each parameter validates the two edges associated with i t . Since there are six different edges that can appear in the layout, two flags are needed to validate the inside-touch and outside-touch edges not being val- idated by any of the design rule parameters. If we list the six edges together with the parameters and flags that val- idate them, the following result is obtained:

edge parameter or f a g

A-inside-B margin overlap A-outside-B clearance exten\ion B-inside-A extension overlap B-outside-A clearance margin inside-touch inside-touch outside-touch outside-touch

Each edge is validated by one or more parameters or by flags. Conversely, if a certain edge is not validated by any of its parameters, it is regarded as forbidden. As a result of this discussion it would be most convenient to specify

interlayer design rules using statements or macros where all these parameters and flags are involved, instead of us- ing one statement for each design rule which is normal practice in today’s commercial DRC’s. A practical format for such an interlayer design rule macro would be

Interlayer (layer A , layer B , cleurance, tnargin, exten- sion, overlup, “comment” [. inside_touch] [, outside -touch])

where clcwraticcJ. margin, exremion, and overlup are the four parameters while inside-touch and outside-touch are the two flags. When using this macro, each parameter infers the corresponding edge checks while each omitted flag or pair of omitted parameters forbids a certain edge, as can be deduced f‘rorn the table above. As an example, the specification of cleurmrzce on!\ leaves the A-inside-B and B-inside-A edges as forbidden edges while the spec- ification of clcaruncc urid margin leaves the B-inside-A edge as a forbidden edge. Finally, we have not allowed one parameter alone to be omitted. If there is a certain parameter we do not care about, it can be specified as Lero. Contrary to omitting the parameter, no forbidden edges are implied, but on the other hand, no checks are performed either.

The use of the interlayer design rule macro will be i l - lustrated by a number of examples.

Example I : Trunsistor Rules: For a transistor, the four parameters, deurunce, murgiti, extension, and overlup correspond to 1) minimum clearance between (field) poly and active, 2 ) minimum margin of poly to active to ensure minimum sourceidrain overhang, 3) minimum extensiori of poly over active to ensure minimum poly overhang, and 4) minimum overlup to ensure proper minimum width transistors. These situations are illustrated in Fig. 8. Us- ing MOSIS’ scalable CMOS rule set3 as an example, the transistor rules are specified by means of the interlayer design rule macro as

Interlayer (Poly, Active, 1 . 3, 2 , 3. “MOSIS SCMOS Rules 3.3-3.5”)

where the comment is a reference to the corresponding design rule in the MOSIS scalable CMOS rule set. 0

Examples of rules where only one parameter is given are the cleurunce only and margin only rules.

Example 2: Cleurunce On&: For certain layers, like Via and Contact-to-poly, that are not allowed to overlap, clearance is the only given parameter.

Interlayer (Via, Contact-to-poly, 2 , -, -, -, “MOSIS SCMOS Rule 8.5”)

Here, Via edges inside Contact-to-poly and Contact-to - poly edges inside Via are forbidden (together with the

Example 3: Murgin Only: For certain layers, like Con- tact-to-poly and Poly, where one layer must appear in-

touch edges). c

‘MOSIS Scalable and Generic CMOS Design Rules, Revision 6. Feb- ruary 1988.

1 I

side the other layer. margin is the on11 gi\,en paratnetcr. This is the traditional enclosure rule.

Interlayer (Contact-to-pol). Pol). -. I . -. -. "MOSIS SCMOS Rule SB.?")

Here. Contact-to-po14 -edges outside Pol! and pol^ -edge\ inside Contact-to-pol> are forbidden (;is are the touch edges).

There are t w o typical examples o f interlayer design rules where t w o parameters are specified. name14 the c?rciruiicx> riiitl itiCii.<yiii and ct-teii.sioti r i t i d o \> ( , r lq rules.

E.raniplc 4 : Clcrirtiricc~ t i i i r l Mnrgir i : When ;I certain layer. such as Via. must appear either ou ts idc o r iriside o f another layer. such as Active o r Pol) . hut n o t be placed across Active or Poly edges. the c,lcJrri.ciiic.c. t i i id iti(ii.giii

rule is used:

Interlayer (Via. Active or Poly. 2 . 2 . -. -. "MOSIS SCMOS Rule 8.4").

Consequent11 . Active or Poly edges itre I'orbidden in\icle Via.

Exuniplc 5: Estois iot i ~iiitl o \ ~ ~ r l c i p : Another " tuo pa- rameter" rule i s the guard-band rule. where Well edges must be covered by guard-bands. I n the case of 3 - p n - wide guard-bands. a rule specification like

Interlayer (Guard-band. \\ell. -. -. 2 . 2 . "guard-band rule")

can be used. as illustrated in Fig. 9. Well edges without guard-bands are forbidden.

E.r~iniplc 6: " I i i tho Diroctioti of' ': A rule that requires some consideration is the select rulc: ( "MOSIS SCMt )S Rule 4.1") which is illustrated in Fig. I O . If this rule is to be interpreted "in the direction ot'Active" o n l y . i t must be specified as a margin rule and not as ;i clearance rule. This could be done as

Interlayer (Gate. N-_acti\.e. 0. 3. -.

"MOSIS SCMOS Rule 4 . I " . inside-touch)

Interlayer (Gate. P-active. 0. 3. -. -.

"MOSIS SCMOS Rule 4.1". inside-touch)

where /-active = (Active and not Select). P-actiLc =

(Active and Select). Gate = (Po14 and ActiLc). Since

Guard

on l ) one of the edges ot' the con\ 'es gate corners matches the edge specifcation. the minimum margin is checked onl) in the direction of' clifl'usion (Active). The clearance iiieasure is put t o /er0 i n order n o t to interfere with other , A c t i ~ ~ e / S e l e c t tntcrlaycr rules such as the minimum clear- ;itice between Wactivi. and P-acti\,e. Forbidden edges are :ill Select edge\. either inside Gate or touching Gate. rl

D . LiiTiitutioti,s (!I' .Sii~ip/i / i( ,r/ l i t i ~ ) l ~ , i i i ~ ~ i i ~ ~ i ~ ~ o i i . \

According to design rule Definition 3 . a minimum sep- iiration rule between t> pc 1 1 t ) pe? and type3/type? edges means that t> pc3:type? edges must not intersect the con- \traint regions 01' type 1 't) pc? edges. and vice versa. Hou ever. in the edge function implementation. type3 is regarded ;is ;I i'orhidclen l a e r which must not appear Lvithin the constraint region of type1 /type2 edges. and >iniilarl>/ type 1 la>,er\ must not appear within the con- straint region of' type3/t>,pc2 edges. This implementation \implitiea constraint checking and increases DRC eff- ciencj . For intralayt'r design rules. this interpretation is always consistent with the design rule definitions. but for intcrlayer design rule\. Definitions 6 and 7 are consistent if. and o n l ~ , if'. the following conditions are fulfilled:

clearance 5 min {spacing(.-l) + extension + overlap.

spacing(B) + margin + overlap)

margin i min spdcing(,4) + o\,erlap + extension.

width(B) + clcarance + extension}

extension I ni in (spacing(H) + overlap + margin,

width(il) + clearance + margin)

owrlap I n i i t i (u,idth(.4) c margin + clearance.

width(B) + extension + clearance}

JEPPSON ( 2 1 ( I / . EDGE-BASED G E O M E T R I C DESIGN RULES

m - layer 0

6.5

extensinn

where A and B are the two layers of the interlayer macro. The interpretation is consistent with the design rule defi- nition in the sense that edges other than those matching the design rule definition cannot appear in the constraint region under the conditions above, without violating an- other design rule.

The limitations can be deduced from Fig. 1 1 . As an example, let us look at the clearance constraint of the rightmost A-rectangle. The constraint region must not reach the AB layer in the middle of the figure because this layer is not bounded by a correct edge for clearance checks. It is an A-edge instead of a B-edge. The corre- sponding limit for B rectangles can easily be derived by interchanging layers A and B. From these two figures, two limits for margin and extension are also obtained. The remaining four limits are similarly obtained by reversing layers A and B.

For most design rule sets, the forbidden layer specifi- cation can be further reduced t o increase DRC efficiency even more. If the t y p e I h p e 2 edge is an A-edge and type31 type2-edge is a B-edge, it is more efficient to use layer B (or its complement) as the forbidden layer instead of a layer combination of A and B. This simplification reduces the constraint checking to one layer instead of two, or as in Magic, reduces the number of allowed tile types. This implementation is consistent with the design rule defini- tions as long as the following conditions are fulfilled:

clearance I rnin { spacing(A) + extension, spacing(B)

+ margin}

margin I rnin {spacing(A) + overlap, width(@

+ clearance)

extension I rnin {spacing(B) + overlap, width(A)

+ clearance}

overlap I rnin (width(A) + margin, width(B)

+ extension}

which limitations are a little tighter than above. These limitations can be derived from Fig. 12 in a way similar to above. The only rule we have encountered that does not meet these conditions is the Active to Well rule, for instance in the Swedish University 3 pm CMOS process.‘ Here, a large clearance measure is required between ac- tive areas outside the well and the well. However, usually this clearance constraint should be met, regardless of whether the well is covered by a guard-band or not. In this case the guard must be defined in a separate layer, or Boolean layer operations or electrical node information must be used to distinguish between guard-bands and other active areas.

When touching is allowed the derived limitations are somewhat modified. The worst cases are:

clearance I min { space(A), space(B)}

5pace

‘Portable CMOS Design Rules for the Swedish Universities, 1985

e, overlap

4 ’ c

margin layer A ~

extensinn 4 ’ ’ c

clearance

Fig. 1 I . When clearance IS checked a \ the distance hetween A-outside- E-edges and Kedges . the situation indicated by the clearance arrow does not comply with the definition of clearance, and such violations should not be reported. The same is true when margin is checked between A-inside- E-edges and E-edges. as illustrated by the margin arrow.

layer A -

overlap space I‘B !%,I!cJ clearance

I

layer A

Fig. 12 . When clearance is checked as the distance between A-outside- E-edges and E-edges. the situation indicated by the clearance arrow does not comply with the definition of clearance, and such violations should not he reported. The same is true when margin is checked between A-inside- E-edges and E-edges. as illustrated by the margin arrow.

overlap I rnin {width(A), width(B)}

when inside-touch is allowed and

margin I min {space(A), width(B))

extension I min {space(B), width(A)}

when outside-touch is allowed

IV. SPECIAL DESIGN RULES The design rules discussed so far are considered simple

rules. More complex design rules, like conditional and conjunctive rules. can also be defined by the proposed rule format. Conjunctive rules usually allow a relaxed mini- mum value or require an extended minimum value in the presence of a third layer. The most common “benchmark rule” is the metal reflexion rule as shown in Fig. 13(a). The presence of polysilicon under a metal edge increases the metal spacing requirement. The metal reflexion rule, as formulated in the figure, is easy to check because it is a local design rule. The conjunctive layer is present in the comer where the constraint check is performed. The rule definition is

edge (metal and not poly), not metal, metal, space-1

edge (metal and poly), not metal, metal, space-2

marg n ' m r ayer A I o B m> ex eided-wargin l rom layer A to B I - direct o r 0 1 cur rer ' tk rb layer C)

i 'I I t i : 11. t \ t c i i i l c d iii<iryiri 01 ci i i i t ; ic I i . 11 t i l pol!\ilicon (Lo in direction (11 lllrt3l ( C )

p o l y s l l t c o n

.re's

Lias. Such a conditional spacing rule can be formulated space- 1 s2ace-2 saace 3

3s

718:8l edge (metal and not contact_grown-by-margin_to_

ih, metal). (not metal).

(nietal and not contact-grab n-by-margin-to-metal).

normal-spacing I h ) (<i>h:il

1 tis 1.2 hletdl I i ' l l C \ 1 0 1 1 rule cp;lLc I < \pact 1 C' \p,Icc 7 1 , l ) I . l l i . , l

edge (metal and not poly). not metal. (metal and poly ). edge (metal and contact-gron,n_bl-margin_to

sprr cr-2 metal). (not metal), metal. rrlr~red-spnci/?g.

Another way of handling con.junctive and conditional rules is to extend the rule format by conditional con-

edge (metal and poly). not metal. (metal and poll ).

spricii-3 straints of the tqpe

As before. SI inmetrical convex corner$ of metal are edge type 1 . tq.pe2. constraint I . conditional constraint]. sub.ject to the extended diagonal check. while other cor- ners are limited to perpendicular checks. If the metal re- flexion rule also applies to the situation shown in Fig, 13(b), we face a much more difficult problem [4]. This rule is not a local design rule. To check this rule i t is necessary first to perform grow operations on the pol! layer in order to transform the problem into the one we solved in Fig. 13(a).

Another conjuncti\ e design rule concerns the margin of poly around a poly contact. Often an increased margin is required in the dircctioi~ of c u r w i t 1 I 1. [ 12) as illus- trated in Fig. 14. The physical basis ofthis rule is to a\,oid metal thinning at the polysilicon edge. If .*the direction of current" can be interpreted as the existence of a pol l - inside-metal edge. the rule is quite simple to specify. For most processes. this design rule definition is appropriate because the normal margin to poly is larger than the mar- gin to metal. This rule is then defined bq :

edge (metal and not poly). (metal and poly). con- tact-to- poly, I..rtrndrci_rnnrgin

in addition to the normal margin rule. If the normal mar- gin to poly is smaller than the margin to metal the rule can be defined using a virtual layer obtained by growing the contact-to-poly by e.rrended-margiri.

A common conditional design rule is that a smaller minimum spacing can be allowed between metal wires when their length is shorter than a certain value. This rule will allow room for contact and via flanges without sac- rificing metal pitch. A verj simple interpretation of this rule can be implemented if the edges to which the rule applies can be identified by their adjacency to contacts or

For the "direction of current"-rule, a first constraint check can be used to find the direction of metal from the contact-to-poly-edges. If the conditional constraint check is true, a second constraint check is performed to check the extended poly margin. The conditional constraint can also be used to check the length of an edge before check- ing conditional minimum spacing rules.

V . Two EXAMPI.FS o b RULE COMPILERS '4. Inrrodirction

In this section we will present two rule compilers we have developed for Magic and for corner-based design rule checking. Magic has been chosen because of its wide- spread use in university environments and because of the simplicity with which our design rule definitions can be translated into Magic's own rule format. Comer-based design rule checking has been chosen to support our proj- ect on hierarchical VLSI circuit verification.

B. Magic Magic uses edge-based design rule descriptions very

similar to the edge function described in Section 11. This edge-based rule description follows the format [ 131:

edge4way type I type2 d OK-types corner-types cor- rirr-distance.

where the keyword edge4way specifies type1 hype2 edges in the same way as our edge function. Within a distance d from the edge. only OK-rJpc layers are permitted. If layer corrirr-txpes is present in the lower right quadrant. the constraint region is extended by conier-distance into the upper right quadrant. By specifying corner-types equal

JEPPSON ( 2 1 U / kDGE B A S E D G E O M E T R I C DESIGN R U L E S 61

to type2 and cornerdistance equal to d the same con- straint region is obtained as in our edge function (bearing in mind that OK-types are the reversed type3 layers).

A straightforward rule compiler for intralayer and in- terlayer design rules can easily be developed for Magic using a preprocessor like M4 in the UNIX environment. For each parameter in the macro rule description, the cor- responding edge checks are added to a list of edges for which constraint checks are to be performed. For each pair of omitted parameters, the corresponding forbidden edge is added to a list of forbidden edges. For each omit- ted flag, the corresponding forbidden edge is added to the list of forbidden edges. Forbidden edges, for instance, in- side-touch-edges, are specified by statements of the form

edge4way ( A and B ) (not A and not B ) 1 0 0 0

used in incremental checkers, as well as in hierarchical checkers where regularity of repetitive structures can be exploited, as in the halo algorithm [ 5 ] .

Contrary to traditional, region-based DRC’s, DRAC- ULA being a typical example, where polygon algebra is used to derive new virtual layers for design rule checking from the original mask layers, comer-based DRC’s work only on the original mask layers. The global mask oper- ations are replaced by three corner-based steps: comer identification, context matching, and constraint checking. Instead of checking one or two layers at a time using scan- line techniques [ 111 as in region-based design rule check- ing, all layers are checked in one step. Checks are per- formed, rectangle by rectangle, using the remaining lay- out as “background information” for context matching and constraint checking. Each comer of a rectangle is in-

while constraint checks, like the clearance checks, are specified by statements like

vestigated to see if i t matches the context of any of the design rules. For matching corners the constraints of the applicable rules are checked. edge4way ( A and not B ) (not A and not B ) cleurunce To describe design rules in terms of comers, a comer

I

not(B) (not A and not B) cleurunce function, similar to the edge function, is introduced hav- ing the format: edge4way (not A and B) (not A and not B ) cleurunce -

not(A) (not A and not B ) cleurunce.

To gain DRC efficiency, the constraint checks can be confined to one of the two edges. For clearance and over- lap checks it is unimportant which of the two edge checks is selected. However, for the margin and extension checks, we choose to check from inside edges since these edges usually are fewer in number (than the outside edges).

Since Magic uses a unique corner-stitched data struc- ture where the layout is stored as tiles in a number of planes, the rule compiler must also translate the different mask layers used to specify the design rules into the cor- responding tile types. When two mask layers A and B are stored in the same plane, all four layer combinations of A and B , AB ( A and B ) , AB ( A and not B ) , A B (not A and not B , AB (not A and B ) , appear as separate tile types. The active plane, for instance, storing the Poly and Active masks, contains the tile types gate, poly, diffusion, and spacing. The gate tiles, in their turn, are either N-gate or P-gate tiles and the diffusion tiles are either N-diffusion or P-diffusion tiles.

A detailed presentation of the application of the intra- layer and interlayer design rule macros to Magic, includ- ing its limitations when the two layers belong to different planes, is presented elsewhere [ 141.

C. Corner-Based Design Rule Checking Comer-based design rule checking was introduced by

Amold and Ousterhout [4]. Corner-based design rule checking is based on the observation that if a design rule is satisfied at all comers of a design, then it is satisfied everywhere along the edges of the design. Due to its lo- cality, comer-based design rule checking can be used to check small areas of layout independently. This can be

corner-type type: [ ] [ ] [ ] 1 , [forbidden layer, dis- runce] [“comment”] I , modifier]

where corner-type is either convex or concave and the other parameters have the same meaning as for the edge function (except that max is the only modifier). The four square brackets represent the context of the comer, and in a Manhattan layout it specifies layers that are required in the four grid-sized quadrants of the corner. The order of the quadrants is [lower left (1l)I [upper left (ul)] [lower right (Ir)] [upper right (ur)]. This order is relative to the orientation of the comer, which means that the type 1 layer is always present in the lower left quadrant. Empty brack- ets mean arbitrary contexts, i . e . , all corners of the spec- ified corner type are specified. The definition and orien- tation of the convex and concave corner types of a certain layer, type, are shown in Fig. 15.

The constraint region is placed in the upper left quad- rant. Just as the constraint region of an edge is sometimes extended according to Definition 4 , the constraint region of a comer is extended for certain convex corners, such as the symmetrical convex corners.

For comer-based design rule checking, a straightfor- ward preprocessor expansion of the interlayer design rule macros, as for Magic, would result in inefficient design rule checking. This is - because _ - - the “combinational lay- ers” of A and B (AB, AB, A B , AB) have not been derived and, therefore, the corners of primitives in these layers are not directly accessible. For each interlayer design rule, the simplest possible edge specifications should be used in order to simplify corner identification and the simplest possible constraint specification should be used to in- crease constraint checking efficiency.

Let us illustrate this paragraph by considering the cleurunce only rule as an example. If both inside-touch and outside-touch are forbidden, a straightforward expan-

\\ he re

inter\ection 4 R

edge \tatenlent\

edge AB. A B. AB. c~lrrrrcriic~~ - _ _ -

edge AB. B. A B . chwnrncc

edge A B . A B. "inside-touch"

edge AB. AB. .'outside_touch'

edge AB. AB. "A-inside-B"

edge AB. AB. "B-inside-A".

by the following edge statements:

edge A . 2. B. c. lerrr trr icx3

edge B. B. A . c ~ l r r r m i i r ~ ~

edge AB. 2 B. "inside-touch"

It can be shown that the same errors M i l l be disco\,ercd

if the conditions described in Section I l l -D are met. All design rule violations. except inside touch. uill be

found by performing clearance check4 from a l l il- ant i B-edges. At first. i t might appear to be a n etficiency l o s s that the forbidden edges must be disco\ered by constraint checking instead of by context matching. However. since there are not supposed to be a n y forbidden edges in the layout, the efficiency loss when constraint cheching must be performed for a few forbidden edges is ncgligiblc. compared to the speedup in context matching f o r ;I large number of correct edges.

Besides obtaining ii much shorter I i \ t of forbidden edges. the specification of the edges I'rom lvhich coil- straint checks arc performed are siiiiplilied consiclerabl! ,

The advantage of this simplification bccorne\ e\ idcnt when the edge\ are expanded into corners according to

Fig. 16. Following - -~ the rules indicated b j Fig. 16. thc endpoint\

of A B / A B-edges are given by:

convex AB: I 1 (231 [AH1 1 I convex A B : I 1 IXB1 [ A + ~1 1 1 concave A + B: (AB1 [ I I 1 [ 1 while A/A-edges are ended hj , the I'ollowing corners:

convex A : I 1 [ I concave A : [ 1 I 1 I ] I 1 intersection A B

I [ 1

14 the intersection comer obtained when two layers. A and H . intersect. i . e . .

con\e\ .3H: I ] p l B ] l . iB] I.1HI. Hcnccx. for c~lco , - t r i rc .c , orrl\.. the original corners can been

I c t l ~ i i ~ c ~ l i o corners v , i t h niuch simpler contexts which will \peed up corner matching considerably.

,A s a I ;I \ t opt i 111 i /.at i c )n r, t e p . gcoine t ric considerations ciiii he u\ed to remo\ e coiic;i\ c corner rules under circum- stances nhcn the wiiic \ iolation can bc found at convex

An optimi/cci rule coiiipilcr consisting of I150 lines of' i ~ x l c has hccn \\ ritten in C . The ctfciency of the DRC using both the optimitcd rule compiler and a straightfor- v, ard MI1 preprocessor cxpansion L\ a s compared. The poly ixjntact I-ules and the transistor rules given as examp!es in Section 111-C were conipiletl both uays and tested on a circuit with 511 contact cuts a n d 756 transistors. Through the optimiration. the run t i m e \+a\ reduced by 31 '% (from 75 to -13 s ) t o r thehe i w o riilcs. The time for context riiatching \ \ ;1 rccl~iced b! ;I f a ~ ~ t o r of 5 from 60% to 23 57 0 1 ' the total time for corncr checking. The largest eHi- cicni,j gains arc obtainccl f o r clcsigii rules with only one o r t\vci \pecificcl 1xiramctcrs. a i d thcse rules dominate the total number of' rules.

corner\.

V I . CO\(.I I \ I O \ S

I n this papcr \vc h;i\.c introduced an edge-based rule t'ormat to express definitions of' intralayer and interlayer design rule\ in rei-ins of' n i i n i i ~ i u n i ( o r niaximum) dis- tances be tween edges. To raise the specification of design rules to ;I higher level. u c ha\,c suggested intralayer and intcrlaj er design iiiacro4 \\ here all design rule parameter\ itrc collected i n thc smiic iiiacro. Rule compilers to expand i i i x r o s into ctiicient edge-based and corner-based rule code ha\c hcen de\ eloped. Both corner-based and edge- based DKC's. lihe Magic. ha\ e lacked interlayer design rule iiiacros before. v, hich has seriously decreased their adaptabilith to ne\\ proce\se\. Now this limitation is re- movcrl.

From ;I \iiiiple obscr\,ation o f the fact that constraint cheching should he extended f o r diagonal checking at all 41' iiit~ictriciil co i i~~ex corners. a rule of fundamental ini- pot-tance has bccn derii,ed. Such a unified approach con-

JEPPSON r / r r / EDGE-BASED GEOMETRIC DESl(iN KU1.b.S 69

siderably simplifies design rule specification. With this definition one realizes that enclosure and extension rules are the same type of rules, and that they differ only in their forbidden edges. To our knowledge, such an approach has not been published before. In his thesis on corner-based design rule checking, Arnold 161 does not consider exten- sion checks in the same section as spacing and enclosure checks. In Tailor, which is an edge-based layout system containing 45” multiple angles based on trapezoidal cor- ner-stitching compatible with Magic, Marple et al . [15] use different design rule macros for clearance, margin, extension, and touch, and their extension checks are not extended for symmetrical comers, as opposed to their margin checks. In this paper we have shown that all four interlayer design rule parameters are of the same nature because they are only layer permutations of each other. The same conditionality in whether checks should be made perpendicular to an edge or include diagonal checks ap- plies to all four design rule parameters.

Special attention has been given to corner-based design rule checking. Even if we have applied corner-based de- sign rule checking only to Manhattan layouts, it can easily be expanded to handle 45 O trapezoidal layout as in Leo45 [6]. Because of their local properties, corner-based DRC’s show excellent performance, both in terms of CPU speed and IiO requirements, for hierarchical designs and/or in- cremental checking. Locality is necessary to exploit hi- erarchy and repetition in VLSI designs. Our results in hi- erarchical design rule checking using the halo algorithm and inverse layout trees have recently been summarized [ I O ] .

Ac K NO w I . EIX M E N T

The authors would like to thank Dr. Lennart Lundgren for many valuable comments which greatly improved the manuscript.

REFERENCES

I I ] C . A . Mead and L . A . Conway, l n f r o d w f i m f o VLSlSysfern.s, Read- ing. M A . Addison-We\lcy. 1980. Chap. 2 .6 (Plates 1-3).

121 H . Modarres and R. J . Lomax. “A formal approach to design-rule checking,’‘ /E€€ Trtrrr.v. Corfii,u/cr-~lclrt~,r-Ar~/[,[/ L)c, . \ igii . vol. CAD-6. pp. 561-572. July 1987.

131 G . S. Taylor and J . K . Ousterhout. ”Magic’s incremental design-rule checker,” in Proc. 2/s / De.siR/f Aufowwfiori Cori,f.. June 1984. pp. 160-165.

141 M . H. Arnold and J . K. Ousterhout. “Lyra: A new approach to geo- metric layout rule checking.“ i n Pro[ . . 19fh L)e.\igri Autoimrriorf Cor!/:. June 1982. pp. 530-536.

[SI N . Hedenstierna and K. 0. Jeppson. “The halo algorithm for hicr- archical design rule checking o n VLSI circuit /iurer-Aidril L)rJsi,qri, vol. 12. pp. 00-00. this

161 M. H. Arnold. “Corner-based geometric layout rule checking l o r VLSl circuits.“ Univ. Calif., Berkeley. Rep. UCB’CSD 861264. also Ph .D . dissertation. 1985.

171 B. J . Nelaon and M . Shand. “An intcgrated. technology-indepen~ dent. high-performance ar tuork analyzer for VLSl circuit design.” J. VLSI trrid C m f p f e r S y s f . . ~ ~ o l . 1 . pp. 271-295. 1983.

181 N. Hedenstierna and K. 0. Jeppson. “New algorithms for increased

etficiency in hierarchical design rule checking.” Infrgr tr f ion . vol . 5 . pp. 319-336. Dec. 1987.

191 -, “The use of inverse layout trees for hierarchical design rule checking,“ in Proc. 26fh D If Auformrriori corif., June 1989. pp. 508-512.

I I O ] N . Hedenstierna, “Hierarchical corner-based design rule checking.“ Ph.D. dissertation. Chalmers Univ. of Technol., 1991.

I I ] M . T. Yin, “Layout verification of VLSl designs,” VLSI Sysr. Dc>- sign, vol. 6. pp. 30-38, July 1985.

121 S. Perry. S. Kalman, and D. Pilling. .‘Edgc-based layout verifica- tion.” VLSl ST.\/. DPsi,qn. vol . 6. pp. 106-1 14. Sept. 1985.

131 W. S. Scott and J K. Ousterhout. “Magic maintainer’s manual #2: The technology file,” in lY86 VLSl Too/.\, Univ. Calif.. Berkeley. Rep. UCBiCSD 861272. 1985.

141 N . Hedenstierna and K . 0. Jeppaon, “A compact interlayer design rule miicrn and its application to magic-Parts I and 11.” /E€€ Cir- cu i r s crnd Dn.ic.r.7 Mrrg . . vol. 6. (Part I ) . pp. 8-10 and (Part 11). pp. 7-9. 1991.

[ IS ] D. Marple. M . Schmulders, and H . Hegen. “Tailor: A layout system based o n trapezoidal corner stitching,” l € E E Trans. Corn/,ufer-Aic/ec/ Dc,;\i,yii. vol. 9. pp. 66-90, Jan. 1990.

Kjell 0. Jeppson (S’68-M’76-SM’83) received the M.S . degree i n electrical engineering in 1970 and the Ph .D . degree in solid-state electronics in 1977. both from Chalmers University of Technol- ogy. Giiteborg, Sweden.

Since 1978 he has been a Lecturer (Associate Professor) at the Department of Solid-state Elec- tronics at Chalmers University of Technology. He spent the academic year 1973- 1974 writh Rock- well International. Anaheim. C A , and the fall se- mester of 1985 at the Southampton University Mi-

croelectronics Centre, Southampton, U .K. His main research interest is MOS devices and CMOS VLSI design. He has published several papers o n MNOS nonvolatile memories. MOS transistnr modeling and parameter ex- traction, CMOS gate delay, and hierarchical DRC. He has also authored a textbook (in Swedish) on semiconductor devices.

Sven Christensson (S’67-M’68) received the M.S . degree in electrical engineering in 1964 and the Ph.D. degree in solid-state electronics in 1971. both from Chalmers University o f Technology, Goteborg. Sweden.

He has been with the Department of Solid-State Electronics at Chalmers University of Technology since 1964. During 1969-70 he was with Cornell University and Cayuga Associates, Ithaca, NY. His main research interest is in MOS devices and CMOS VLSI design.

Nils Hedenstierna (S’88-M’89) received the M.S. degree in electrical engineering in 1984 and the Ph.D. degree in solid-state electronics in 1991, both from Chalmers University of Technology, Goteborg, Sweden, where he is a Member of the Research and Teaching Staff at the Chalmers Uni- versity of Technology Department of Solid-state Electronics .

His main research interest involves different as- pects of CMOS VLSI design, such as hierarchical design verification. design rule checking, and tim-

ing models