DIGITAL IMPLEMENTATION OF RF DIGITAL RECEIVER ON FPGA

A DISSERTATION Submitted in partial fulfillment of the

requirements for the award of the degree

of

MASTER OF TECHNOLOGY

in

ELECTRICAL ENGINEERING

(With Specialization in System and Control)

By

GORAKH NATH CHAUBEY RAL

• • ,c

1.4t~ Cj

4

~ Y

•01

1 X

I

DEPARTMENT OF ELECTRICAL ENGINEERING

INDIAN INSTITUTE OF TECHNOLOGY ROORKEE

ROORKEE-247 667 (INDIA)

JUNE, 2012

D/ T/ISO /r /v /13

INDIAN INSTITUTE OF TECHNOLOGY ROORKEE

` ROORKEE

CANDIDATE'S DECLARATION

I hereby declare that the work which is being presented in the dissertation thesis

entitled "Digital Implementation of RF Digital Receiver on FPGA" being

submitted by me in partial fulfillment of the requirement for the award of Master of

Technology in Electrical Engineering with specialization in Systems & Control at

I.I.T. Roorkee is a bonafide work carried by me under supervision of Dr.(Ms) Indra

Gupta, Associate Professor and Dr. Vishal Kumar, Assistant Professor, Electrical

Engineering Department, I. I. T. Roorkee.

The matter embodied in this dissertation thesis has not, been submitted by me

for the award of any other degree or diploma.

Date: i2/o6J2o12

(GoraF Nath Chaubey)

Thisis to certify that the above statement made by the candidate is correct to the best of our knowledge

(Dr.(Ms) DRA GUPTA)

Associate Professor

EED, IIT Roorkee

(Dr. VISHAL KUMAR)

Assistant Professor

EED, IIT Roorkee

ACKNOWLEDGEMENT

I express my deepest gratitude to Dr.(Ms) Indra Gupta, Associate Professor and Dr.

Vishal Kumar, Assistant Professor, Department of Electrical Engineering, Indian Institute

of Technology, Roorkee for their valuable guidance, support and motivation for this work.

The valuable hours of discussion and suggestions that I had with them have undoubtedly

helped in supplementing my thoughts in the right direction for attaining the desired

objective. I am deeply indebted to them for devoting time despite their busy schedule.

I also wish to record my gratitude to all the faculty of Electrical Department who were of

constant support throughout my work. My sincere thanks to the laboratory staff to access

the computers and other resources at will for completion of this work.

Last but not the least, I am highly indebted to my parents, family members and friends,

whose sincere prayers, best wishes, moral support and encouragement have a constant

source of assurance, guidance, strength and inspiration to me.

Date: 12rbG/zo / 2

GORAKH NATH CHAUBEY

Place: IIT, Roorkee Enrollment No. 10530007

M.Tech -- lindYear

EED, I IT Roorkee

ABSTRACT

This dissertation report presents the design and implementation of RF digital receivers on

FPGA. As the development of digitization, especially the hardware technology increases

enormously, software defined radio (SDR) becomes a mainstream gradually. The thought of

SDR theory is to implement all radio functions by software programming on a universal,

standard and modularized platform. SDR emphasizes an opening architecture and full

programmability, and new functions will be realized by software upgrade. SDR theory adopts

standard, high- performance, bus-opening structure, and it is beneficial to upgrade and expand

the hardware modules. According to the SDR theory, AD/DA should approach RF or IF section

to digitize, and realize all receiver functions by digital signal processing. However, RF full

sampling cannot be achieved because of the limitations of digital devices.

RF band-pass sampling receiver has become possible to achieve due to enhancement of DSP

and micro-electronics technology. In this dissertation report, general structure of digital receiver

is summarized first. The second section discusses the multi-channel parallel digital down

conversion (DDC). Digital signal parallel correlation processing (match filtering) and data

output-interface are mentioned separately in the next sections. DDFS is for generating digital

sinusoidal waveform to generate shape for the incoming bit-streams. This digital receiver has

been implemented by using system generator platform and VHDL coding.

iv

LIST OF FIGURES

Figure Figure name Page no: no:

I.1 Traditional super-heterodyne receiver 01

2.1 Digital receiver block diagram 05

2.2 Logical structure of RF Digital Receiver 07

3.1 The architecture of the conventional DDC 10

3.2 Poly-phase form of FIR decimation 13

5.1 Structure of Standard DDFS 24

5.2 Schematic layout of the direct digital synthesizer 26

5.3 Block diagram of DDFS 27

5.4 Clock management system 28

6.1 Design flow overview diagram for Xilinx synthesis . 35

6.2 Proposed design of RF digital receiver by system generator 39

6.3 JTAG Hardware Co-Simulation block of RF digital receiver 40

6.4 Overview of RF digital receiver 40

7.1 Simulation o/p of ADC 41

7.2 Debugging o/p of ADC 42

7.3 Simulation o/p of noise affected signal 42

7.4 Debugging o/p of noise affected signal 43

7.5 Combined simulation result of DDC for all 8 channels 43

7.6 Comparison of simulation results of conventional and proposed DDC 44

7.7 Test bench result of proposed DDC 45

7.8 Combined simulation result of FIR filter for all 8 channels 46

v

7.9 Simulation result comparison of original signal and o/p signal . 46

7.10 Wave-scope result of the RF digital receiver 47

7.11 Device utilization summary of the RF digital receiver 48

vi

NOMENCLATURE

FFT Fast Fourier Transform

FPGA Field Programmable Gate Array

PLA Programmable Logic Array PAL Programmable Array Logic

LUT Look Up Table

ALU Arithmetic Logic Unit

I-IDL Hardware Description Language

VHDL (Very High Speed Integrated Circuit) Hardware Description Language

ISE Integrated Software Environment

RTL Register Transfer Level

PAR Place and Route

JTAG Joint Test Action Group

CPLD Complex Programmable Logic Device

I-IWCOSIM Hardware Co-Simulation

UCF User Constraints File

XST Xilinx Synthesis Technology

DDC Digital Down Converter

DDFS Direct Digital Frequency Synthesizer

PSOC Programmable System on a Chip

FIR Finite Impulse Response

I.PF Low Pass Filter

1313 Base Band

RF Radio Frequency

I F Intermediate Frequency

vii

TABLE OF CONTENTS

> Candidate's Declaration ii > Acknowledgement iii > Abstract iv > List of Figures v > Nomenclature vii > Table of Contents viii

Chapter-1: Introduction 1 1.1. Traditional Receiver 1 1.2. Digital Receiver 1 1.3. Organization of Dissertation 2 1.4. Objective of Dissertation Work 3

Chapter-2: General Structure of Digital Receiver 4 2.1. Structure of Digital Receiver 4 2.2. Types of Digital Receiver 6

Chapter-3: Parallel Digital Down Converter 9 3.1. Principle of Working 9 3.2. Conventional DDC 9 3.3. Proposed design of DDC 10

3.3.1. Linear Phase Filter 13 3.4. Filtering and Decimation 14

3.4.1. Filtering for Narrowband DDC 14 3.4.2. Filtering for Wideband DDC 16

3.5. DDC Over Analogue Technique 17 3.6. Summary 18

Chapter-4: Correlation Processing in Baseband 19 4.1. Time-Domain Correlation Processing 19 4.2. Frequency Domain Correlation Processing 21

4.2.1. Introduction of FFT 21 4.2.2. Floating Point FFT and its Analysis 21

4.2.3. DIT-FFT algorithm Principle 22 4.2.4. Structure of Floating Point FFT 23 4.2.5. Code Coverage 24

4.3. Summary 24

Chapter-5: Direct Digital frequency Synthesizer 25 5.1. Introduction 25 5.2. Principle of DDFS 27 5.3. DDFS Architecture 28 5.4. Sub Modules of DDFS 29

5.4.1. Clock Management System 29 5.4.2. Phase Accumulation 31 5.4.3. Compressed ROM 31 5.4.4. Single Bit DAC 32

5.5. Frequency/Phase hopping and Capabilities of DDFS 32 5.6. Summary 33

Chapter-6: Simulation of RF Digital Receiver with System Generator 36 6.1. Software Details 36

6.1.1. Xilinx ISE 13.1 with Service Pack3 36 6.1.2. Xilinx System Generator 39

6.1.3. Xilinx System Generator Board Description 39 6.2. Design Process for Reconfigurable Computing 40 6.3. Simulation Of Digital Receiver with System Generator 41 6.4. Summary 43

Chapter-7: Simulation Results of RF Digital Receiver 44 7.1. Simulation Results with sinusoidal signal 44 7.2. Summary 46

Chapter-8: Conclusion and Future Scope 48

REFERENCES 50

ix-

CHAPTER#1

INTRODUCTION

1.1 Traditional Receivers

Traditional receivers adopt analog circuit structure, and the basic idea is mixing signal from

radio frequency (RF) to intermediate frequency (IF). After filtering the IF signal, the second mixing

shifts its frequency spectrum to zero frequency, and then the processed signal would be outputted to

user interfaces. As the development of digitization, especially the hardware technology, software

defined radio(SDR) becomes a mainstream gradually.

The schematic diagram of the traditional receiver is shown below:

[Fig 1.1 Traditional super-heterodyne receiver]

1.2 Digital Receivers

The thought of SDRtheory is to implement all radio functions by software programming on a

universal, standard and modularized platform, and detach from a communication equipment design

for special use [1]. SDR emphasizes an opening architecture and full programmability, and new

functions will be realized by software upgrade. SDR theory adopts standard,high-performance, bus-

opening structure, and it is beneficial to hardware modules upgrade and expansion. According to the

SDR theory, AD/DA should approach RF or IF section to digitize, and realize all receiver functions

1

by digital signal processing. However, RF full sampling cannot achieve because of the digital

devices performance at present.

RF band-passsampling receiver has become possible to achievedue to enhancement of DSP and

micro-electronics technology. In this paper, general structure of digital receiver issummarized first.

The second section discusses the multi-channel parallel digital down conversion (DDC). Digital

signal parallel correlation processing (match filtering) and data output interfaces are mentioned

separately in the and nextsections.

The hardware implementation of RE Digital Receiver is to be implemented further on FPGA

platform by using HDL language and the layout of the probable hardware system design for this

project is discussed briefly at last.

1.3. Organization of Dissertation

Chapter 1

Inthis chapter, the introduction about traditional receivers as compared to digital receivers is

discussed.

Chapter 2

The general structure of the digital receiver is explained and also the type of the digital receiver

based on the signal bandwidth.

Chapter 3

Traditional and improved with efficient DDC structure is discussed in this chapter.

Chapter 4

In this chapter the correlation of the original message signal with noise affected signal is discussed in

two domains namely time domain (with FIR filters) and frequency domain (FFT algorithm).

Chapter 5

The generation of the I-phase and the Q-phase signals (digital sine and cosine waveform) is

discussed with the probable architecture of the direct digital frequency synthesizer.

Chapter 6

The software details of the Xilinx system generator with the design process of the RF digitaI receiver

is explained.

0A

Chapter 7

The debugging and simulation results with the data signals added with the inherent AWGN are

included inthis chapter.

Chapter 8

Conclusion and the future scope of this RF digital receiver is discussed briefly.

1.4. Objective of Dissertation Work

• To studythe features of RF digital receivers and how it will overcome thelimitation of traditional receivers.

• To study the enhanced DDC in-phase technique for RF digital receiver.

• Design and implement the proposed RF digital receiver with different type of signals mixed with AWGN.

• Comparing results with the original message signal with the received signal.

W

3

CHAPTER # 2

GENERAL STRUCTURE OF DIGITAL RECEIVER

2.1 Structure of Digital Receiver

Digital receiver technology has nowreplaced many of the traditional analogtechniques of radio

reception. Let's take a look at a digital receiversystem, where the basic functions of the

analogreceiver are still there. The signal processingblocks perform high-speed

digitization,downconversion, filtering, decimation anddemodulation, all done with digital

signalprocessing circuitry. Depending on thetype of signal, the demodulator extractseither analog

signals or digital data.

To pluck a weak signal from the air, weneed an antenna and the RF amplifier. If the frequency of the

input signal is too highto be digitized by the A/D converter, a RFanalog downconversion is also

necessary.The resulting input to the A/D converter iseither a baseband signal or an IF signal witha

bandwidth of typically 45 MHz or less.Digital samples from the A/D converterat rates up to 100

MHz and higher are nowsent into a mixer. Here this mixer isactually two digital multipliers capable

ofcornputing o/p products at the A/Dsampling rate. The other i/p's to the mixerare digital in-phase

(I) and quadrature phase (Q)components of a LO signal, alsoarriving at the A/D sampling rate.

The LO is actually a direct digital frequencysynthesizer (DDFS) delivering sampledsine and cosine

waveforms at a programmablefrequency. The LO is driven by theA/D sampling clock and uses a

phaseaccumulator and digital sine LUT to generate complex o/p samplesJust as in the case of the

analog receiver,the output of the mixer consists of both sumand difference frequencies and we are

interestedin keeping the difference productsignal.

Compared to its analog counterpart,the precision of the digital circuitry in themixer dramatically

reduces unwantedmixer byproducts.Another distinction in the digital receiversystem is that by

multiplying the digitizedRF input by the sine and cosine signalsfrom the LO, we are performing a

4

singlesidebandfrequency translation of the inputsignal. This allows us to translate this complexsignal

right down to DC or 0 Hz, which is ideal forthe filter.

The schematic diagram to support the method of working of digital receiver can be as follows:

ALL DIGITAL IMPLEMENTATION

jH MIX

RF RF AID DI!

AMP

DSP D/A RF

_J TRANSLATOR CONVERTER. DEMOD CONVERTER: CAMP MIX

AID CLOCK DIGITAL LO

[fig: 2.1 Digital receiver block diagram]

To select the desired bandwidth of ourreceived signal, we send the mixer outputinto a complex FIR

low pass digital filter.Unlike the IF amplifier filters in the analogreceiver, the digital FIR filters are

extremelystable, accurate and need no tuning or calibration.They also offer a linear phaseresponse,

ideal for time domain signals, andexcellent channel-to-channel matching tosupport applications such

as direction finding&beam forming.

By programming the FIR filter coefficients,we can change its bandwidth easily over awide range. At

the filter output, we takeadvantage of the bandwidth reduction todrop the output sampling rate, a

processcalled decimation. Since the bandwidth and decimation arelinked, many digital receivers

allow simplecontrol of both, through a parameter calledthe decimation factor N. The final

outputbandwidth of the FIR filter is determinedby dividing the AID sampling rate by N,making it

quite easy to program.

5

2.2. Types of Digital Receiver

Digital receivers can be divided into twoclasses.

• Narrowband receivers:

These receivers typically havea decimation range of about 32 to 65,536 and,therefore,

provide output bandwidths frombelow I kHz to about 2.5 MHz for samplingat 100 MHz.

• Wideband receivers:

The decimationfactors ranging from 1 to 64, candeliver bandwidths from approximately2

MHz up to about 45 MHz.

Depending on the digital receiver chipused, the output formatter stage can provideeither real or

complex digital outputs in 16, 24 or 32-bit fixed point or floating-point to match the needsof the DSP

stage.As far as the demodulator function isconcerned, it is now performed digitally ina DSP

processor. For standard commercialbroadcast stations, envelope detectionalgorithms can handle AM

signals and frequency discriminator algorithms canhandle FM signals. The demodulatedsampled

outputs can be sent into a D/Aconverter to produce an analog signal andthen connected to an

amplifier and speaker.Digital data transmission employs dozensof different schemes for encoding

phase,amplitude and frequency, each schemetargeted for a specific application.

On thereceiving side, demodulation tasks for theDSP processor are

• Channel equalization

• SymboI tracking

• Frame detection

• Convolution

• Error correction

• Decoding and

• Decompression.

No approach other than digital signalprocessing could possibly handle these tasks.

Because they are inherently programmable,as new modulation standards areinvented, digital receiver

systems can often beupgraded by loading new software routinesinstead of replacing expensive

[.1

hardware.The other major benefit of digital receiversystems is the economy of scale for highchannel

count systems. While it may stillbe cheaper to use- an analog receiver inyour Walkman, a cell phone

base stationtakes full advantage of low cost per channel,low power, improved accuracy andstability,

high reliability, re-configurabilityand fast switching characteristics offeredby digital receiver

technology.

Later on the RF digital receiver is to be design and implement on FPGA board. The probable

logical architecture of the digital receiver can be as follows

[ Fig: 2.2 Logical structure of RF Digital Receiver]

RF analog signal is sampled by ADC into two channels, and FPGA completes digital down

conversion (DDC), signal correlation processing (such as matched filtering or FIR filtering depends

upon modes used), data buffer gradually, and outputs the result through parallel data interface in the

end. Also, analog output can be implemented by DAC controlled by FPGA. The entire hardware

platform achieves prospective functions by FPGA programming, so parallelism and real-time can be

controlled exactly.

7

I CHAPTER # 3

PARALLEL DIGITAL DOWN CONVERSION

3.1 Principle of Working

A DDC is basically complex mixer, shifting the frequency band of interest to baseband. Consider the

spectrum of the original continuous analogue signal prior to digitization because it is a real signal it

has both positive and negative frequency components. If this signal is sampled by a single A/D

converter at a rate that is greater than twice the highest frequency. The continuous analogue

spectrum repeated around all of the sample frequency spectral lines.

The first stage of the DDC is to mix, or multiply, this digitized stream of samples with a digitized

cosine for the `I' channel and a digitized sine for the `Q' channel and so generating the sum and

difference frequency components.The amplitude spectrum of either the `I' or `Q' channel after

mixing, the mixer frequency has been chosen in this example to move the signal frequency band

down to base-band.

The amplitude spectrum of both I/Q channels will be the same but the phase relationship of the

spectral components is different. This phase relationship must be retained, which is why all the

filters in the phase path must be identical to those in the Q-path. It should also be noted that because

theQ-signals, spectral components from both positive and negative frequencies can be overlaid, for

non-Q sampling the two frequency components would have to be kept separate and so requiring

twice the bandwidth.

3.2 Conventional DDC

The conventional digital down converter (DDC) mainlyconsists of two simple cascaded integrator-

comb filters and afinite input response filter preceded by a modulator that iscontrolled with a

numerical controlled oscillator [1]. Cascaded integrator-comb (CIC) filters are computationally

efficientimplementations of narrowband low-pass filters. But, with theincrease of the bandwidth in

8

modem RF digital receiver, thecompensation filter will cost more resources. With thesampling

technique in which the sampling frequency is 4times as high as the intermediate frequency and the

use ofhalf band filter architecture, an efficient architecture andimplementation of digital down

converter are presented for the wide band RF digital receiver.

[Fig 3.1 The architecture of the conventional DDC]

The conventional digital down converter (DDC), with thecascaded integrator-comb filters,

avoids multiplications, andis an efficient method for narrowband signals. With theincreasing

bandwidth in modem radar systems, theconventional DDC needs more resources for

thecompensation filter to flat the pass-band.

3.3Proposed architecture of DDC In typical decimation filtering applications, we desirereasonably flat pass-band and narrow transition

region filterperformance. These desirable properties are not provided by cascaded integrator-comb

filters alone, with their droopingpass-band gains and wide transition regions. The

conventionalmethod flats the pass-band by following the CIC filter with a compensation finite

impulse response filter[2].For narrowband signals, the conventional DDC is efficient.But, with the

increasing of the bandwidth, the compensationfinite impulse response filter will cost many

0

resources,especially when the bandwidth is more than 1/4 of thesampling frequency.So, the

improved method uses half band low-pass filterinstead of the CIC filter and the compensation finite

impulseresponse filter.For modem intermediate frequency radar signal, thesampling technique in

which the sampling frequency is 4times as high as the intermediate frequency is often used. Inthis

condition, the complex mixing sequence will be 1, i, -1, -i,etc. So, downconversion of an input time

sequence could beaccomplished merelywith data assignment, or signal routing.

A fundamental part of many communications systems is Digital Down Conversion (DDC).The.aim

of DDC is to convert signals from intermediate frequency to baseband. Most common used methods

include LUT, CORDICPOLY-PHASEfiltering and so on.

• LUT output is sine and cosine amplitude according to the different phases, but this method is

less used because of the requirement of huge storage for preset waveforms.

• CORDICalgorithm adopts iteration for mixing phase's generation, and its iteration restricts

the arithmetic speed.

• POLY-PHASE filtering DDC is easy to implement, and it requires sampling frequency as

fs=4fc/(2m+1),fs>=2B, where fc is thesignal center frequency, m is a free positive integer

and B isthe signal bandwidth. This method suits for low ratesignals, and improvement is

asked for RE signal processing. Sample frequency adopts fs=4fc/(2m+1), but sampled signals

are separated in to 8 channels. Then, if each channel'sprocessing rate unchanged, DDC will

work in a much higherfrequency.

Digital radioreceivers often have fast ADC converters to digitize the band limited RE or IF signal

generating high data rates;but in many cases, the signal of interest represents a small proportion of

that bandwidth. To extract the band ofinterest at this high sample rate would require a prohibitively

large filter.

A DDC allows the frequency band ofinterest to be moved down the spectrum so the sample rate can

be reduced, filter requirements and furtherprocessing on the signal of interest become more easily

realizable. Here the radio signal lying in the range 300-400MHz has been used. The signal

bandwidth is 40MHz. However, it is often digitized with a sampling rate over 100MSPS,

representing in the region of 200Mbps while implementing on FPGA hardware system.The DDC

10

allows us to select the 3-4MHz band, and to shift its frequency down to baseband and in doing

soreduce the sample rate, with a 1MHz bandwidth, a sample rate of 2.5MHz would be fine - giving a

data rate ofonly 5Mbyte/second:

The sample timing sequence of the DDC for each I/Q channels can be visualize as follows

N K K+1 K+2 K+3 K+4 K+5 K+6 K+7

Phase n/2 n 31t/2 0 n/2 rc 3it/2 0

Coefficient +1 -1 +1 -1 +1 -1 +1 -1

Output I(4N) Q(4N) I(4N+1) Q(4N+1) I(4N+2) Q(4N+3) I(4N+3) Q(4N+3)

Poly-phase filters:

Poly-phase is a way of doing sampling rate conversion that leads to very efficient

implementations.But more than that, it leads to very general view point that are useful in building

filter banks.Before delving in mathematics we can see a lot just by looking at structure of filtering.

Efficient FIR Filtering for Decimation:

The following algorithm is used to find the decimated samples and their filtering action

Filtering: X[n] = E j x[i] h[n — i] .......................................................[i]

Decimation: X( )m[n]= X[nM

X( )m[n] =x[i] h[nM — i]........+ ..................................................[ii]

Let us consider that the sequence of the samples is x[i] and the filter impulse response is h[n] where i =1,2,3,4,5......... and n = 0,1,2,3,4............

Here for sake of simplicity we took 16 samples for equivalent division between 8 channels of individual impulse response taken from h[n].

The proposed architecture to find the length of the filteris as follows:

11

0

[Fig : 3.2 Poly-phase form of FIR decimation]

3.2.1 Linear Phase Filter:

It is mentioned that the filters used to reduce the bandwidth of the signal usually have linear phase

characteristics.Linear phase filters are usually more complex than those with arbitrary phase

characteristics, so once again, there is a good reason for this. Communications systems often depend

on the relationships between multiple carriers. These carriers may be the same frequency but with

different phase;" or they may be completely different frequencies. In either case, disturbing the phase

relationships would have worse impact on the reception of signal. For this reason, most DDC

designers will try to use linear phase filters exclusively. These appear as a simple delay to the signal,

and as all elements of the signal are delayed by the same amount, the signal's integrity is preserved.

3.3 Filtering & Decimation

There are two main classes of DDC

• Wideband DDC

• Narrowband DDC,

12.

The above two types of DDC can bedifferentiated by their decimation ratios. As a rough

guide, if the decimation ratio is less than 32, consider the DDC wideband; if 32 or more, the

DDC is narrowband.

The filtering we will perform is different for narrowband or wideband, so is tackled separately.

However, the decimators can be treated identically for wideband or narrowband systems.

Note also that in some systems it may make sense to combine wideband and narrowband DDCs.

For example, in a GSM system which uses 8 carriers, a wideband DDC could be used to shift the

carriers down to a moderate frequency. This could be done using a simple oscillator — no complex

components. 8 narrowband DDCs could then be used to select the individual carriers. The theory is

the same as the above explained.

3.3.1 Filtering for Wideband DDCs

With a wideband signal, the sampling rate is reduced by a small amount, and the data output rate is

large. Note that the output rate of a wideband DDC should be checked as part of our overall system

design. In some systems that data rate will be significant, and could saturate a DSP processor — if

that is meant to be receiving it.

The main challenge of a wideband receiver is getting enough processing to filter the signal. All the

processing is performed at a fairly high rate, often 20-40MHz. Because of this, the filters tend to

be very gate-intensive; a single wideband channel will typically consume more of an FPGA than

several narrowband channels.

Each design has different requirements. However, the following is a rough guide to implementing

the filter. The filter is best implemented as an FIR, and in fact the best approach is to use a multi-

rate FIR. This may sound complex, but in fact a multi-rate FIR is simply an efficient way of

implementing large filters with decimation. Imagine we need to implement a large filter at a high

sampling rate, before decimating the signal. We could implement a 128-tap filter at 100MHz, but

this would require a lot of multipliers and a huge FPGA.

13

Hdwever, if the filter is splitted then the first filter can perform enough filtering to allow us to

perform some decimation. The second filter is now operating at a much reduced sampling rate.

Typically by splitting the filter in this way, the number of taps in the filter could be reduced and

also the sampling rate that some of these taps operate it, could also be reduced. Both reduce the

amount of FPGA resources used, which is required to build the filter.

So, with a simple FIR, a filter implementation can be started. This stage should have a small

number of taps - if we are operating at a high sampling rate, each FPGA multiplier will implement

a very small number of taps. Use symmetric FIRs here — the processing load is about half a non-

symmetric filter, and the core generator provides this as an option. Regardless of which FPGA are

using, this stage will take a lot of silicon! The filter's bandwidth should match the output

bandwidth of the DDC.

(Npte: the output bandwidth is the band that we're interested in — typically only a few hundred

KHz wide)

Immediately after this filter, decimate the signal by 2, and implement a larger filter. Again, the

filter's bandwidth should match the DDC output bandwidth. This will improve the response of the

first filter. You can afford to have more taps in this stage, as the sampling rate is lower.

If we are operating a low decimation ratio, this could be all we have to do. That means that these

filters have to have more taps than if we can use an additional stage. Experiment by trying

cascades of filters with varying numbers of taps — we will probably have to do this iteratively,

using the Xilinx tools to try several different scenarios.

For higher decimation ratios (e.g. 8 and up), you can afford to use a third stage filter. This can have

significantly more taps than the first two, as each multiplier here can implement at least 4x as

many taps as in the first stage. Again, the experiment with the layout of the filters to see what gives

best performance, has been given further.

14

F zAI

c'' 3.3.2 Filtering for Narrowband DDCs r

Ndrrowband DDCs have a different set of challenges. With these, we need filters that can allow

large decimation ratios without consuming too much of the FPGA.

A very useful filter here is the Comb-integrator Cascade filter, or CIC filter. This filter has

remarkable properties — it can implement decimation within the filter, and it provides a steep cut-

off for relatively few stages. Best of all, it is implemented using only adders and delays, which

makes it very well suited to FPGA implementation.

Me CIC has one failing — it has a lot of "droop" in its pass-band, and serious ripples in its stop-

band. I lowever, we can compensate for these with additional filtering of its output.

Because of the need for additional filtering on a CIC's output, it is at its best with large decimation

ratios. The larger the decimation ratio, the smaller the overhead of the filters used to compensate

for the CIC. This makes it unsuitable for the wideband DDC we looked at earlier as the

compensation filter becomes significant. However, for the narrowband DDC, it is ideal as a first

stage.

We would then follow that with a multi-rate FIR filter, as with the wideband DDC. Now, we can use

as many taps as a single multiplier will allow. Generally a two-stage FIR works well, decimating by

2 between the stages. For many applications, 23 taps will work well in the first filter, and should be

realizable with a single multiplier design; while 63 would be ideal in the second. Again, use

symmetric FIRs to reduce the processing load

3.4 DDC Over Analogue Technique:

Plainly a DDC is implementing something which could be done in analogue — it's sometimes good

to stop and check why we'd want to do this. The DDC is typically used to convert an RF signal

down to baseband. It does this by digitizing at a high sample rate, and then using purely digital

techniques to perform the data reduction.

Being digital gives many advantages, including:

15

(1) Digital stability — not affected by temperature or manufacturing processes. With a DDC, if

thesystem operates at all, it works perfectly — there's never any tuning or component

tolerance toworry about.

(2) Controllability — all aspects of the DDC are controlled from software. The local oscillator

canchange frequency very rapidly indeed — in many cases a frequency change can take place

on thenext sample. Additionally, that frequency hop can be large — there is no settling time

for theoscillator.

(3) Size- A single ADC can feed many DDCs, a boon for multi-carrier applications. A single

DDCcan be implemented in part of an FPGA device, so multiple channels can be

implemented oradditional circuitry could also be added.

However, there are some disadvantages:

(1) ADC speeds are limited. It is not possible today to digitize high-frequency carriers

directly.There are techniques to extend the range of ADCs, but often it is simpler to use

analogue circuitsto bring the carrier down to an IF that digital circuits can then manage.

(2) ADC dynamic range is limited. In many communications systems, the signal's amplitude

canvary greatly. Fast ADCs often only have l2bits of resolution — giving an absolute

maximumdynamic range of 72dB. It is often better to use analogue circuits in conjunction

' with the ADC toimplement AGC functions to ensure that this range is best used.

In time, more and more systems will use predominantly digital technology. However, the high

speeds of many communication systems will ensure that a hybrid approach, using analogue and

digital, will be the best route for many systems for a long time to come.

3.5 Summary:

The novel digital down converter algorithm in this reportprovides a high efficient architecture for

wide band RF digitalreceiver. Based on the sampling technique in which thesampling frequency is 4

times as high as the intermediatefrequency and the use of half band filter architecture, theimproved

method avoids most of the multiplication unitescompared with the conventional DDC. This

architecture has been used in some RF digital receiver systems.

' 16

CHAPTER #4

CORRELATION PROCESSING IN BASEBAND

Baseband signal correlation processing means that signals pass through a matched filter, with the

output port emerging a high SNR moment for signal detection. In digital communication, signal

correlation processing is widely used. Signal correlation processing can be achieved either in time

domain or frequency domain.

4.1 Time domain correlation Processing

In time domain processing, a FIR filter is necessary, but it is often used in a low time-bandwidth

product -situation

The proposed expression to find the FIR filteringaction is as follows:

Let an FIR filter of length `M' with i/p x(n) and o/p y(n) is described by the difference equation

y(n) = box(n) + b1x(n-1) + b2 x(n-2) + ..........+ bM_lx(n-M-1). . . .(i)

= Zk=o bk x(n — k) .........................................................(ii)

Where { bk } is the set of filter coefficients. Alternatively, we can express the o/p sequence as the

convolution of the unit sample response h(n) of the system with the i/p signal. Thus we have

y(n) = Zk o h(k)x(n — k) ...................................................... (iii)

Where the upper andlower limit of the sum represent the causality and finite duration characteristic

of the fi-lter.The filter can also be characterized by its system function as

17

n

H(z) _ Ek o h(k)z—k ............................................................. (iv)

An FIR filter has unit linear phase if its unit sample response satisfies the condition

h(n) = + h(M- 1-n) or - h(M-1-n) ...................................... (v) where n= 0,1,2......M-1 when the symmetry and anti-symmetry condition in (v) are incorporated into (iv) we have

H(z)= h(0)+ h(1)z-1 + .......... h(M-2)z-(nor-2) + h(M-1)z-(M-1)..(vi)

H(Z)- Z-(M-1)/2 {h(Ml) ~(M-3)/2 h(n)[z(M-1-2k)/2 +l- Z-(M-1-2k)/2]

for M is odd and

H(z) = Z -(M-1)/2+ E(M2 h(n)[Z(M-1-2k)/2 +l- Z-(M-1-2k)/2 Lin=O

forM is Even

Now on substitutingz-lfor z in (iv) and multiply both sides of the resulting equation by z-(M-1) ,

Th'e above expression becomes

z_(M-l)H(z) _ +/- H(z) ................................................ (vii)

This results implies that the roots of the polynomial H(z) are identical to the roots of the

polynomial H(z-1) i.e. the root occurs in reciprocal complex conjugate pairs.

18

The simulation and debugging result for the base-band correlation process by FIR filters is given in

chapter 7

4.2 Frequency Domain Correlation Processing

Frequency domain processing is common used where matched filter is widely adopted, and the most

important keys are signal conversion between time domain and frequency domain. So, FFT and

IFFT are important.

4.2. ]Introduction of FFT

In digital signal processing, many algorithms such asconvolution, filtering, and spectral analysis can

beimplemented by fast Fourier transform (FFT). The FFT hasbecome the most basic algorithms of

DSP[1 1], and is widelyused in power equipment monitoring and fault diagnosissystem. According to

the different data bits and form duringthe operation, FFT can be divided into

• Floating-point FFT

• Block floating point FFT

• Fixed-point FFT[12].

Fixed-point arithmetic is simple but it is hard to ensure that there is no overflow. Block floating

point can avoid overflow but it delays too much[13]. If the system requires high precision and can

solve the problem of the single-frequency interference during high frequency, floating point FFT is

the best choice. To fasten signal processing speed and achieve high precision, this paper provides the

design of floating point FFT with Radix-2 algorithm and 32-bit single precision format.

4.2.2Floating point FFT Analysis

The IEEE computer society has developed a standard forbinary floating-point arithmetic. Its basic

format sizes ofsingle precision are 32 bits which are divided into three parts:bit 0 through 22 are the

mantissa part, bits 23 through 30 arethe exponent part and bit 31 is the sign bit part.[13]These

bitsform the floating point number, V, by the following relation:

19

V = (_1)s * M * 2E-127

The term(-1)s denotes the sign bit S which is 0 for apositive number and 1 for a negative number.

The variable,E, is one number between 0 and 255 represented by the eightexponent bits. The mantissa, M, is formed from the 23 bits asa binary fraction.

4.2.3DIT FFT algorithm Principle

Figure 1 shows the 8 point DIT-FFT algorithm schematic.The inputs are firstly stored in the address

unit in accordancewith the natural order. After a three-stage butterfly operation,the results of FFT are

then outputted in a bit reversed addressso that final output is in accordance with the natural order.

The signal flow graph includes 12 butterflies. Eachbutterfly represents a two point FFT. For each

twp pointFFT, if the input is complex A (x + j X) and B (y+ j Y), theoutput is complex Al and B1.

Then we have the followingrelationship [14]:

y \ZNkI (--))2k 2ky Zk/1 Al = x + cos + \

Ysin + 'J( X + Y cos\l — \

sin

y 2Nk (—_))+J(X_Ycos(__)+(ys1n(-_))2 kZk 2kB1=x— cosll—\Ysin

Pipeline FFT structure is a better choice than recursive structure and parallel array structure, for it is

resource-saved and successively calculable. Pipeline FFT algorithms include radix-2 SDF (Single

Delay Feedback), radix-4 SDF, radix-22SDF and so on.

The resource occupation is shown in table.

MULTIPLIERS ADDERS MEMORIES R-2SDF 2(log4N-1) 4log4N N-1 R-4SDF (log4N-1) 8log4N N-1 R-2^2SDF (logiN-1) 4log4N N-1

20

R-2^2SDF FFT takes fewer resources than the other two structures. R-2^2SDF FFT algorithm

improves from R-4 FFT, which takes two-level R-2 FFT butterfly concatenation to achieve an R-4 FFT butterfly function.

4.2.4 Structure of Floating Point FFT

Operation of the processor consists of three parts: datainput, FFT computation and data output.

Processor cyclesbegin from the input process, during which the samplingdata is read and stored in

memory. During the FFTcalculation process, the stored data is computed. FFTcalculation results are

read out for subsequent calculations,during the output process.As shown in figure 2, FFT processor

includes a singleradix-2 butterfly, a dual-port FIFO RAM, a coefficient ROM,a controller, an

address generation unit, and a cycle unit. Thecycle unit can separate the various cycles, namely c0,

cl, c2and c3. Over FFT computation, the process of writing intothe RAM starts only five cycles after

the first data is readfrom RAM. Then the counter unit counts these cycles. Alldata are 32-bit single

precision format, and coefficients arestored as 32-bit words.

Th'e butterfly computes a two point FFT. It reads the twodata from memory and calculates the FFT,

and then writesthe results to the same memory location.The butterfly processing unit has a multiplier

and twoadders. Four clock cycles are needed to compute a two-pointFFT and it has a latency of five

cycles. The three input data(y, Y and x) requires three cycles for an output to becalculated. The other

two cycles are to pipeline the RAMread and write operations.

Here in this dissertation report, frequency domain filtering is used which is sufficient for the low

time bandwidth product therefore for the better debugging and simulation results on system

generator platform frequency domain filtering is used.

4.2.5 Code Coverage The major problem of the simulation approach is tochoose a good metric to gauge the quality of the

test pattern[15]. One popular metric of verifying the design written inHDL is the code coverage

metric in software testing. Code- coverage of sub-modules inthe FFT processor and that of the test

pldtform after two testvectors run. The results are very encouraging: the code coverageof some sub

modules was 100%; the coverage of FFT processor control module was as high as 98.4%; the

21

coverage of thetesting platform reached at 93.8%; the coverage ofmultiplication module rose

significantly from 87.9% to 97%by changing the test vector; the coverage of address indexmodule

was 88.9%; the coverage of the clock module was81%; and the coverage of addition control module

was95.4%. Some codes are not executed but they are "others"statement in the "case" statement and

will only be executedunder abnormal conditions. Therefore, it will not affect thetest completeness.

4.3Summary

In this FFT algorithm, the floating point FFT based on system generator. Simulation results show

that it takes 875nsto execute the 8-point FFT when main clock frequency is 100MFIz.The code

coverage is normally 100% except forvery few modules, whose code coverage is also higher than

80%. Verification results demonstrate that applying Xilinx block-set to FFT signal processor can

accomplish float-point FFT and that the simulation is very complete. In the future, implement 1024

point floatingFFT to improve signal processing capability and efficiency,and apply the FSM

coverage test to traverse the wholetransition graph completely during the simulation process.For

example, the controller is modeled as a finite state machine.

22

CHAPTER # 5

DIRECT DIGITAL FREQUENCY SYNTHESIZER

5.1 Introduction

Frequency synthesizer is an electronic device that acceptssome reference frequency and generates

one or more newfrequencies based on a control word. Recently, frequencysynthesis has found

applications in precision biomedicalequipment and communication systems that demand veryhigh

frequency, fine resolution, large bandwidth and highswitching speeds [31, 32]. There are many

approaches to realizefrequency synthesizers that include Direct Analog Synthesis,Indirect Synthesis

and Direct Digital Synthesis [33]. However,to achieve stringent performance requirements, All

DigitalDirectDigital Frequency Synthesis (DDFS) is considered apromising approach [34, 35].

Because digital circuits possessexcellent stability, in addition to maximum possible switchingspeeds,

these properties make all digital DDFS a suitablecandidate for applications that require frequency

agility andstability [34].

A DDFSis based on classical architecture proposed by Tierney [37] onFPGA chip was reported by

Grama and Muntean [38]. Thesetechniques are limited by the size of Lookup table ROM.Thus ROM

compression is needed to afford high precisionand accurate phase and frequency resolution. ROM

compression techniques have been developed that givebetter spurious behavior and more

compression thanpreviously reported in [38]. Also, a single bit DAC has beenused instead of n Bit

DAC which results in an alldigital design thereby reducing area and power. Anotherinteresting

aspect thatcomplete the DDFS along with the onebit DAC has been accommodatedon a single FPGA

chip and no external DAC is needed.

The proposed standard diagram of the DDFS is given as follows:

23

FCW phase word amplitude word sample &hold

[Fig 5.1 Structure of Standard DDFS]

Standard DDFS consists of three stages

• Numerically Controlled Oscillator(NCO) comprising of Phase accumulator (PA) and Sine

lookup table (ROM)

• Digital to Analog Converter (DAC),

• Low-pass Filter (LPF)

The structure of a standardDDFS is shown above.The frequency control word (FCW) is used as the

constant addend to the PA. The output of PA is fed back to the PAsuch that at each time step the

phase is accumulated. The PAoperates on modulo 2N basis so it simulates the phase of Sinefunction

which is a modulo 2it function. Thus the output ofPA has a one to one correspondence with zero to

2i period.Each value of PA is used to address the lookup table (LUT) which stores corresponding

values of Sine amplitude henceLUT is used to transform angle 0 to Sine(A). The amplitudeword that

is output from LUT is fed to DAC which furnishes its corresponding analog value at the output. This

anhlogvalue is provided to a low-pass filter (LPF) which outputs the

smooth output frequency signal.

Demerit:

• The approach is the size of LUT which increases exponentially with phase word resolution

and linearly with the amplitudeword resolution. Practical systems require phase resolution

ofmore than 22 bits and amplitude resolution of over 12 bits [31].It is obvious that this

phase resolution requires prohibitively large LUT memory which consumes excessive chip

area. Corresponding power dissipation and speed of operation arealso affected.

24

• Another major issues is due to the analog part ofthe system, the DAC. Nonlinearities

introduced by the DACbecome prohibitive as amplitude word resolution exceeds 12 bits

[35].

The problem related to the size of LUTis addressed by compressing the ROM through

utilizingquarter wave symmetry and additional elimination of twomost significant bits of amplitude

words from ROM storage.The DACrelated issues have been addressed through the useof a singlebit

DAC that avoids some nonlinearity inherentin multibit DACs [34]. The synthesizer bandwidth has

beenimproved through multiples of system clocks.

5.2Principle of Working 0

Direct digital synthesis (DDS) is a technique for using digital data processing blocks as a means to

generate a frequency- and phase-tunable output signal referenced to a fixed frequency precision

clock source. In essence, the reference clock frequency is "divided down" in a DDFS architecture by

the scaling factor set forth in a programmable binary tuning word. The tuning word is typically 24-

48 bits long which enables a DDS implementation to provide superior output frequency tuning

resolution.

DDFS advantages:

• Micro-Hertz tuning resolution of the output frequency and sub-degree phase tuning capability, all

under complete digital control.

• Extremely fast "hopping speed" in tuning output frequency (or phase), phase-continuous

frequency hops with no over/undershoot or analog-related loop settling time anomalies.

• The DDS digital architecture eliminates the need for the manual system tuning and tweaking

associated with component aging and temperature drift in analog synthesizer solutions.

• The digital control interface of the DDS architecture facilitates an environment where systems

can be remotely controlled, and minutely optimized, under processor control.

• When utilized as a Q synthesizer, DDS afford unparalleled matching and control of I and Q

synthesized outputs.

25

0

The schematic working diagram for the DDS is mentioned as follows:

Frequency Numerically

Control Controlled DAC LPF Register Oscillator

(NCO)

Reference Oscillator

[Fig: 5.2 Schematic layout of the direct digital synthesizer]

5.3. DDFS Architecture

The all digital DDFS proposed in this work comprises of aclock management system (CMS), phase

accumulator (PA),Compressed Read Only Memory (ROM), singlebit DAC(SBDAC) and a

programmable lowpass filter (PLPF). Thisarchitecture is. illustrated in Fig. 2. The relation between

thegenerated signal frequency and the clock frequency in thisapproach is given as:

fclk

f out = ZN x FCW

where FCW is the Frequency Control Word, N represents thelength of phase word and D represents

the size of amplitudeword.

This equation suggests that by increasing PA size, thephase resolution can be made finer, and by

increasing clockfrequency the bandwidth of the synthesizer can be inereasedlt is evident from (1)

that for fixed amplitude resolution (D)and phase resolution (N), if the sampling frequency is kept

aslow as possible for a desired bandwidth and the samplingfrequency is increased only when the

26

output frequency higherthan the current bandwidth is required, the dynamic powercan be saved.

These observations have been used in this workfor bandwidth adjustable DDFS.

The proposed Block diagram for the DDFS is as follows:

BWCW Div_clk FCW Phase_word amp_word

[Fig 5.3 Block diagram of DDFS]

5.4Sub Modules of DDFS

5.4.1 Clock Management System

The clock management system (CMS) takes standard clockand a bandwidth control word (BWCW)

as input. CMSproduces two output signals, one is Mul_Clk which is amultiple of input clock and the

second one is Div Clk, adivided by 2**D version of Mul_Clk. As soon as BWCWchanges value,

the sampling frequency (Div_Clk) changesand frequency of the output signal becomes multiple of

thefrequency that was called by FCW at the first place. ThisDDFS is an all digital circuit and it uses

a singlebit DAC forproviding corresponding analog output value. The singlebitDAC (SBDAC)

requires 2D (D is size of amplitude word)times faster clock than rest of the circuit in order to

prgvidefull amplitude resolution as it generates the pulse widthmodulated (PWM) signal [10].

Therefore Mul Clk drives theSBDAC and Div Clk drives PA.

27

The CMS uses digital clock managers (DCM) to providemultiples of the input clock. DCM is a

primitive module provided in modern Xilinx FPGAs [13]. Itprovides many functions like clocked

delay lock loops, anddigital phase shifters etc. The dynamic power consumed bythe DDFS is given

as:,

P = ACV2 x Mul clk

Where P is the dynamic power consumed by the circuit, A isthe activity factor, C is switch

capacitance and Mul_Clk is theoperating clock frequency. If A and C are assumed to be constant

throughout the operation of DDFS, then formaximum bandwidth, maximum Mul Clk is needed

which isa multiple of global clock. Mul_Clk is given by:

Mul clk = n X clk

0

[Fig 5.4 Clock management system]

Where Mul_Clk is the operating clock frequency, n is the multiplying factor and clk is global clock

signal which is50MHz on the FPGA development board used in this work.

28

5.4.2Phase Accumulation

The frequency control word (FCW) is externally applied bythe user through switches. On each clock

cycle, the value ofFCW is added to the accumulated latched value of phase accumulator as shown in

Fig. 4. The operation of PhaseAccumulator (PA) can be modeled mathematically as follows:

S(n)=S(n-1) +FCW

The PA is a modulo2**N device with maximum value equalto 2**N-1. The size of PA

determines the phase resolution of theDDFS. The value of phase word is applied as an address to

the lookup table.

5.4.3 Compressed ROM

The Lookup table has been implemented within the FPGAB1ock memory. Normally, according to

phase resolution, pre-computed values of Sine(0) for each value of phase angle Ofrom 0 to 2t are

stored in the lookup table. The size of thememory dictates the phase resolution and becomes an

important issue as the phase resolution and amplituderesolution increase. LUT size increases

exponentially with thesize of phase word and the increase is linear with amplitudeword size. One

approach to deal with increasing LUT size is to use the L most significant bits of the phase word as

addressof the LUT [8, 12]. However, truncation of phase word causeserror in the output. The error

follows a periodic saw-toothwaveform. This periodic phase error causes correspondingperiodic

amplitude error at the DDFS output. The periodicitymanifests itself as spectral line in the output

spectrum. Thesecomponents are not the harmonics of the required outputsignal and are commonly

called "spurs" [4, 12]. However, tokeep the output spectrum clean from above mentioned spurs,we

have not used phase truncation; instead ROM compressionwas employed to avoid undue increase in

area and power.

29

5.4.4Single Bit DAC

Singlebit DAC (SBDAC) is a pseudo DAC as it is usesjust one flip flop to provide analog voltage

signal of only twolevels; it does not contain any analog components. Theamplitude word obtained

from lookup table is applied as inputto the SBDAC. SBDAC acts as a pulse width modulator(PWM).

Since there are 2D possible amplitude values, so tohave a pulse width corresponding to each

amplitude value, abit string of 2D bits is needed. Therefore, the amplitude wordshould remain stable

at the input of SBDAC for 2D clockcycles. SBDAC generates a bit string of 2D bits correspondingto

each possible amplitude word [10]. This bit stringrepresents a PWM signal being modulated by the

amplitude word.

Duty cycle variations of PWM Modulated rectangularwave represented by this bitstring generates

thecorresponding analog value at terminal of RC low-pass filter.This arrangement makes an all

digital DDFS possible. Due tothis set up, it becomes possible to avoid many problems inherent in any

multibit DAC like differential nonlinearities(DNL), offset error, gain error and glitch impulse etc.

whichmay produce additional spurs in the spectrum of DDFS [4].

SBDAC restricts the bandwidth but it compensates this byproviding lower noise floor and high

SFDR due to noiseshaping and high over sampling ratio [12]. The use ofSBDAC makes the DDFS

an all digital solution. This factmore than compensates the bandwidth reduction effect. Alldigital

solution affords advantages as it imparts long life tothe device with no ageing effects; which are

inherent inanalog parts. This makes it suitable for the application where human intervention is not

possible or is rare e.g. space probesand devices implanted in human body. Harmonics of

thefundamental frequency output may be used to offset thebandwidth reduction if band-pass filters

could be used at the last stage of the DDFS.

5.5Frequency/phase-hopping Capability of DDFS

• Calculating the Frequency Tuning Word

The output frequency of a DDS device is determined by the formula:

30

FouT = (M (REFCLK)) /2^N

Where: FOUT = the output frequency of the DDS

M = the binary tuning word

REFCLK = the internal reference clock frequency

N = The length in bits of the phase accumulator

The length of the phase accumulator (N) is the length of the tuning word which determines the

degree of frequency tuning resolution of the DDS implementation.

As for an example:

Let's find the frequency tuning word for an output frequency of 41 MHz where REFCLK is 122.88

MHz and the tuning word length is 32 bits (binary). The resulting equation would be:

41 MHz = (M (122.8 MHz)) /2^32

solving for M...

M = (41 MHz(232))/122.8 MHz

M= 556AAAAB hex

Loading this value of M into the frequency control register would result in a frequency output of

41 MHz, given a reference clock frequency of 122.8 MHz.

' • Determining Maximum Tuning Speed:

The maximum tuning speed of a DDS implementation is determined by the loading configuration

selected, parallel byte or serial word, and the speed of the control interface. In some DDS

applications, maximum output frequency tuning speed is desired. Applications such as GMSK and

ramped-FSK modulation, require maximum frequency tuning speeds to support spectrally-shaped

transitions between modulation frequencies.

31

When the tuning word is loaded by the control interface, the constraint to frequency update is in the

speed of the interface port. Typically a DDS device will provide a parallel byte load which facilitates

getting data into the control registers at a higher rate. Control data clocking rates of 100 MHz are

typically supported for a byte-load parallel control interface. This means that a new tuning word can

be present on the output of a DDS device every 10 nS.

The phase-continuous output of DDS frequency transitions is well-suited for high-speed frequency-

hopping applications. DDS devices also usually provide a set of registers that can be pre-

programmed with tuning words. The contents of these registers are executed with an external pin on

the device package. This provides for the maximum output frequency hopping speed between pre-

programmed frequency values. This arrangement is especially suitable for FSK modulation

applications where the "mark" and "space" frequencies can be readily pre-programmed.

• The DDFS Control Interface

All of the functions, features, and configurations of a DDS device are generally programmedthrough

the device's control interface port. The control interface for DDS devices is available in a variety of

configurations. The common configurations are serial interface and byte-loadparallel interface. The

interface conventions range from a single 40-bit register that stores all ofthe functional control

words, to a microprocessor-compatible a synchronous serialcommunications port. Control interface

functionality and timing diagrams are detailed in the datasheets for the individual DDS devices.

• The Effect of DAC Resolution on Spurious Performance

Th'e resolution of a DAC is specified by the number of its input bits. For example, the resolution of a

DAC with 8 input bits is referred to as having "8-bit resolution". The impact of DAC resolution is

most easily understood by visualizing the reconstruction of a sine wave. Consider a 8-bit DAC is

used to reconstruct a perfect sine wave. The vertical lines are time markers and identify the instants

in time at which the DAC output is updated to a new value. Thus, the horizontal distance between

32

the vertical lines represents the sample period. [Note the deviation between the DAC output signal and the perfect sine wave].

The vertical distance between the two traces at the sampling instants is the error introduced by the

DAC as a result of its finite resolution. This error is known as quantization errorand gives rise to an effect known as quantization distortion. To understand the nature of the quantization distortion, note

the sharp edges in the DAC output signal. These sharp edges imply the presence of high frequency

components superimposed on the fundamental. It is these high frequency components that constitute

quantization distortion. In the frequency domain, quantization distortion errors are aliased within the

Nyquist band and appear as discrete spurs in the DAC output spectrum.

33

CHAPTER # 6

DESIGNING OF RF DIGITAL RECEIVER

In 'this chapter design procedure to developedthe RF digital receiver has been described. For this

dissertation project, design of the receiver has been developed by System generator along with the

VHDL coding for the DDC and DDFS section. System generator has generated the code for the

FPGA processor from simulink model. So here some sections like FIFO, BUFFER has been directly

used from system generator block-sets and therefore the implementation of the receiver becomes

easy in some manner.

6.1. Software Details

The software's used are

• Xilinx® Integrated Software Environment (ISETM) 13.1 with Xilinx servicepack 3

• MATLAB® Version R2010a

• Xilinx System Generator for DSP 13.1

• Xilinx System Generator Board Description Builder

6.1.1 Xilinx® Integrated Software Environment (ISErm) 13.1 with Xilinx

service pack

Xilinx® ISE 13.1 is a synthesis tools for Xilinx FPGA's. Xilinx ISE 13.1supports Design Entry,

Simulation, Synthesis, Implementation and downloadingthe configuration onto FPGA device.

Xilinx service pack 3 is an upgrade to Xilinx® ISE 13.1. Synthesis of a design isdone in the

following steps.

The Figure 6.1 shows design flow using Xilinx ISE.Brief descriptions about individual steps are

given as below. 0

34

[Fig 6.1. Design flow overview diagram for Xilinx synthesis]

35

➢ Creating HDL Module

In this step the HDL module is created for the design which we want toconfigure onto FPGA.

This is done using Xilinx ISE editor.

➢ Simulation of Design

In this step, we verify functionality of our design. This can be done usingseparate simulations to

individual designs or creating testbench to overalldesign.

> Setting Design Constraints

Setting constraints is important step in design implementation. In this step, weassign pin numbers of

FPGA device for input acquisition and output display.

Timing constraints are also included in this step.

• Synthesis and Design Optimization

The design is translated into gates and it will - be optimized for the targetarchitecture.

• Size and performance Evaluation

After Synthesis of design, we check whether design logic is sufficient forimplementing on FPGA

device. If design logic exceeds the resources availableon chip, then we cannot implement the design.

The design size andperformance details are listed in Device Utilization summary of Synthesisreport

for analysis.

> Place and Route

Once synthesis is completed, the place and route fits design into a Xilinxdevice, and the post place

and route timing information about the design canbe obtained. The stage consists of taking the

synthesized netlist throughtranslation, mapping and place and route.

> Generate Bit Stream

When the design all requirements are fulfilled, the programming file can becreated. It indicates the

information needed to program the device. This file iscalled as bit stream file. The bit stream file is

downloaded to the target device.

➢ Downloading

It is the process by which the bitstream of the design, as generated by Xilinxsoftware, is loaded into

the internal configuration memory (SRAM cells) of theFPGA.

> Timing Analysis

In this step, static timing analysis is done. The setup and hold times areanalyzed.

36

> Design Modification

In this step, the design performance is improved by modifying code and byincorporating FPGA

system features.

➢ Creating a PROM, ACE or JTAG File

The configuration bitstream file can be saved in PROM, so that configurationdetails are not erased

from chip when Power is turn off.

6.1.2. Matlab

MATLAB® is a high-performance language for technical computing. In thisdissertation

MATLAB® Version R2010a is used. MATLAB is used to carry outfunctional Simulation and

Synthesis for FPGA device configuration, using Xilinx System Generator Plug-in. It is used to

implement the Feature extraction processMATLAB SIMULINK is a model based design, which

provides an interactivegraphical environment and a customizable set of block libraries that lets

usdesign, simulate, implement, and test a variety of designs. Xilinx SystemGenerator blockset is

added to SIMULINK upon configuring MATLAB.

6.1.3. Xilinx System Generator

Another tool used for synthesis is Xilinx System Generator. It is blocksetprovided by Xilinx in

MATLAB SIMULINK. System Generator is a system-levelmodeling tool that facilitates FPGA

hardware design. It extends SIMULINK inmany ways to provide a modeling environment that is

well suited to hardwaredesign. The tool provides high-level abstractions that are

automaticallycompiled into an FPGA at the push of a button. The tool also provides access

tounderlying FPGA resources through low-level abstractions, allowing theconstruction of highly

efficient FPGA designs.System Generator allows device-specific hardware designs to be

constructeddirectly in a flexible high-level system modeling environment. 9

In a SystemGenerator design, signals are not just bits. They can be signed and unsignedfixed-point

numbers.System Generator allows designs to be composed from a variety of.ingredients.Data flow

37

models, traditional hardware design languages (VHDL, Verilog, andEDIF), and functions derived

from the MATLAB programming language, can beused side-by-side, simulated together, and

synthesized into working hardware. System Generator simulation results are bit and cycle-accurate.

This meansresults seen in simulation exactly match the results that are seen in hardware. System

Generator simulations are considerably faster than those fromtraditional HDL simulators, and results

are easier to analyze. The key features of System

Generator for DSP are

• DSP modeling

To Build and debug high-performance DSP systems in SIMULINK using theXilinx Blockset that

contains functions for signal processing, error correction, arithmetic, memories (e.g., FIFO, RAM,

ROM), and digital logic. The XilinxBlockset also provides blocks for importing MATLAB functions

(e.g., to createcontrol circuits) and HDL modules (System Generator provides HDL co-simulation

interfaces to ISim from Mentor Graphics and the Xilinx ISE Simulator).

• Hardware Co-Simulation

Creates an "FPGA-in-the-loop" simulation target: a code generation option thatallows validating

working hardware and accelerating simulations in SIMULINKand MATLAB. System Generator

supports Ethernet (10/100/Gigabit), PCI,Cardbus, and JTAG (Joint Test Action Group)

communication between ahardware platform and SIMULINK. It should be noted that Plug-ins for

thespecified FPGA development kits have to loaded in order to simulate thedesigns.

6.1.4 Xilinx System Generator Board Description

System Generator supports hardware co-simulation, making it possible toincorporate a design

running in an FPGA directly into a SIMULINK simulation.The System Generator Board Description

Builder makes it easy to addhardware co-simulation support for any board with a Xilinx FPGA.

6.2.Design Process for Reconfigurable Computing

38

Using MATLAB SIMULINK along with Xilinx System Generator and the XilinxISE synthesis and

implementation tool, it is possible to implement DSP designsin FPGA. As a plug-in to the MATLAB

SIMULINK modeling software, the XilinxSystem Generator provides a bit accurate model of FPGA

circuits andautomatically generates a synthesizable VHDL code including Test bench.

Thissynthesized VHDL design can be used for implementation in the Xilinx's FPGAsplatform

Design process for reconfigurable computing.

6.3. Realization of RF Digital Receiver on System Generator

The RF digital receiver is realized with the help of xilinx block-sets on system generator platform.

The schematic system generator architecture of the digital receiver is as follows

[Fig 6.2 Proposed design of RF digital receiver by system generator]

Before dumping the above designed RF digital receiver on the FPGA kit, it is to be ensured that the JTAG

hardware Co-Simulation block must be generated properly. The procedure to find this JTAG hardware Co-

39

Simulation block has already been discussed earlier in chapter-6. The required Co-Sim block would be as follows:

[Fig 6.3 JTAG Hardware Co-Simulation block of RF digital receiver]

6.4. Summary

The RF digital receiver can be summarized with the help of the hardware system design.

Theproposed hardware system is shown in below.

Analog o/p RF analog i/p

P Filter

Mand

agnmer

Dr ve ADCOBD1000

FPGA Other xC4VSX55 signal

Parallel Data

Interface

[ Fig 6.40verview of RF digital receiver ]

40

2 4 6 8 10 Time (sec)

-100 0

100

-50

M

CHAPTER # 7

SIMULATION AND DEBUGGING RESULTS OF RF DIGITAL RECEIVER

In this dissertation report, simulation and implementation of RF digital receiver has been done by

using system generator platform and VHDL coding of blocks like DDC and DDFS. The baseband

signal time domain correlation processing through FIR filter was verified with the optimum use of

Xilinx block-sets and the simulation followed by debugging result of each function block is

mentioned one by one.

The system has been achieved RF signal receiving and processing with center frequency 400MHz

and bandwidth 40MHz. According to Nyquist sampling theorem, sampling frequency adopts 1 GHz.

• The simulation result of the sampled form of the signal with the help of 8 bit A/D converter

is as follows

[Fig 7.1 Simulation o/p of ADC]

41

• The debugging result of the input data signal after passing through the ADC i.e the samp

signal is given below:

• The amplitude of the analog RF signal is +/- 5v with the frequency of 400 MIHz. the ADi

sampled the analog signal with the sampling rate of 100 MSPS.

[Fig 7.2 Debugging o/p of ADC]

• The simulation result of the AWGN affected sampled form of the signal after passing

through A/D converter is as follows

10° r 50

0

-50

-100 0 2 4 6 8 10

time (sec)

[Fig7.3 Simulation o/p of noise affected signal]

42

2 4 6 8 10 time (sec)

100

50

0

-50

-100 0

• The noise affected signal has spikes and spurs in the amplitude and it can be viewed clearly

from the above simulation result. Here the SNR of the noise affected signal is 60 db which is

deliberately inducted in the sinusoidal signal.

[Fig7.4 Debugging o/p of noise affected signal]

• The next section of the receiver is to down convert the IF signal to base-band with the

algorithm " poly-phase filtering" and the simulation result for the same is as follows

[Fig 7.5 Combined simulation result of DDC for all 8 channels]

43

• The down-sampled (by 8) signal, after filtering by CIC and Compensation FIR filter,

becomes IF to baseband. Afterwards the baseband signal is ready for the correlation

processing.

• The complex signal can be bifurcated into its real and imaginary part. The real part of the

DDC out is given as follows:

The real-part of the conwntionat DDC result 1000

> 500 E I ,illiil I ~I Ii, .

a II I I .i _ ICI I I it ~ 50p

0 5 10 15 Time /us

The real-part of the improved efficient DDC result 1000

500 E

0 •0_.. I~~tliEdr~N~~4'

II -500 E - III 1 I I I ', I I II•

111 1

5

10

15

Time lus [ Fig 7.6 Comparison of simulation results of conventional and proposed DDC]

• The test bench results for the DDC is shown below in which the eight channels of the

receiver are mentioned one by one as OSI, OCI, OS2, OC2, OS3, OC3, OS4, OC4. The

delayed sampled can easily be predicted after looking into the time cycle diagram in which

for the busy low signal i.e negative going pulses (from ADC), the output of the DDC

channels comes with each sample dealy.

• The 8 bit sampled signal and the 5 bit output from the DDFS in the form of SINE and

COSINE alternately multiplied with the 8 bit data sample.

44

• The first channel contains SINE and the second one gives COSINE alternatively. The SINE

is termed as I (in-phase) and COSINE is termed as Q (quadrature- phase) signals

respectively.

[Fig7.7 Test bench result of proposed DDC]

In this dissertation report FIR filter iswith the unit impulse response as H(z) = 0.5 + 0.5 for

each of the eight channels in the system to correlating the pass-band sampled signal to response of

the FIR filter and the simulation result for the same is as follows:

45

40

0 c6

—

-40 ` 1

0 2 4 6 8 10 time (sec)

[Fig 7.8Combined simulation result of FIR filter for all 8 channels]

• The comparison of the simulation results of the received i/p RF signal at the front end of the

RF digital receiver and the baseband analog o/p at the back end of the receiver is as follows

C

2 4 6 8

10 time (sec)

= o a Ca

rii 0 2 4 6 8 10

time (sec)

[Fig 7.9 simulation result comparison of original signal and o/p signal]

46

The previous simulation result came from the simultaneous comparison between the original

information signal and the analog o/p of the RF digital receiver. It reveals that o/p has some error in

the amplitude which is only due to inherent AWGN noise which cannot be remove entirely from the

message signal but there are several way to suppress the AWGN.

The minimization of the AWGN can be seen by comparing the simulation results of the receiver.

• The wave-scope output of the RF digital receiver is given below in which the each time cycle

for each blocks are given one by one.

• From the wave-scope it could be clearly see that the down-sampled and the correlated signal

are buffered to synchronized the first and the last sample of the data signal.

[Fig 7.10 Wave-scope result of the RF digital receiver]

• The device utilization summary reveals the utilization of the hardware used to implement the design.

• The summary table has been given below:

47

'.. )S*•GCflj k- :--

-n.y a- a- •i _3_. d r...., c

• p.---. 0 _3I. • —• - • I

— z-- M.

.M..g. _•, .* — r.._,, l3• ,_ —

—_.-- 4

• "s-.- • e — e —D—r

e — — — • C.*p. bp C.uC___ - •_o_,•u_1 O.3.

Ii U.k

3.' UI'

LI' UI

OUT 11W. -

14 231 23%

11111 I U • -

a'

- U rS1 . 4 •.i 4c..,Io: lb—I

o...., 0W

[Fig 7.11 Device utilization summary of the RF digital receiver]

From the above table one can compare the design and efficiency of RF digital receiver with their proposed receiver design.

CHAPTER # 8

CONCLUSION AND FUTURE SCOPE

Conclusion

The simulation and implementation of the RF digital receiver has performed onSystem

generator platform and Virtex-5 FPGA kit respectively. The system achieves RF signal parallel DDC

and time domain correlation processing, and the RF receiver decreases the analog deviation primly

with higher performance than normal receivers.

Future scope

This signal processing mode is widely used in

• UWB communication

• PD radar and other fields

• X-band Military Satellite Communications (MILSATCOM) signals

• This system can be interfaced withtransponders used to demonstrate live data and video

traffic in anexisting Army Earth Terminal.

• It has achieved initial Technology Readiness Level (TRL) 6 capability by operating in a

relevant environment. More testing will be performed in the near future when the optimized

version of the XADR chip to be clocked at 30 GHz is ready for system integration. The X-

band ADR concept is just a first stepping stone toward an All-Digital-RF Transceiver (ADT)

architecture for future SATCOM Earth Terminals. The overall goal of the ADT is a true

software-defined SATCOM Earth Terminal, which will provide direct RF digitization of the

whole satellite payload bandwidth for all incoming signal carriers from the antenna and

consolidate all digital-RF distributions from the antenna into a single all-digital

• Digital Sideband Separating Mixer (DSSM) -- This initial proof of concept has been achieved in

the form of an L-Band (1200-1700 MHz) down-converter with 500 MHz total IF Bandwidth, the digital recombination performed in software as post-processing.

49

• DSSM With Integrated ADCs -- This milestone will demonstrate the compact integration of

high-gain analog and high-speed digital components in a common housing with sufficient

isolation to avoid self-interference.

• Digital Ortho-Mode Transducer (DOMT) -- This will be the initial proof of concept for digital

polarization isolation. Prototypes will be developed at X-Band using both the three- and four-

probe configurations. As with the above milestones, digital signal recombination will be

performed in post-processing at this stage.

• Real-Time Signal Recombination -- The signal recombination arithmetic will be programmed

into an FPGA, allowing for the first time the digital sideband separation and polarization

isolation to be performed not in post-processing, but in real-time.

• Complete Next-Generation Receiver at X-Band -- A complete X-Band receiver will be tested on

the Green Bank Telescope (GBT), including a cryogenic front-end module with either a three-

probe or four-probe OMT, an RF-input/fiber-output warm receiver module, a minimal-overhead

photonic link, and real-time signal recombination hardware feeding into the backend

spectrometer.

• Next-Generation FPA at W-Band -- Two or more complete next-generation receivers will be

constructed as above, this time at W-Band, and tested as a small prototype focal plane-array with

approximately 2.3cm spacing.

• Beam-Forming Array Prototype at X-Band -- The X-Band next-generation receivers will be

replicated, with a modified DOMT configured to mate with crossed-dipoles instead of a feed

horn, and tested as a beam-forming array with approximately 2cm spacing.

• Ultra-Wideband Next-Generation Receivers -- As higher-speed ADCs, FPGAs, and

Optoelectronic components become available, subsequent generations of the receivers described

in this white paper will be constructed with increasing instantaneous IF bandwidths.

It has a broad application prospects. Widespread use of radio transmissions of digital data now

supports rising markets for cell phones, pagers. wireless LANs and HDTV.

50

REFERENCES

[1] Yang Xiaoniu, Lou Caiyi, Xu-xianliang. Software Defined Radio Enabling Technologies. Beijing:Publishing House of Electronics Industry.

[2] Wei Bingchao. Digital DS spread spectrum communication receiver on ASIC. Computer

Network, Vol 26, pp. 57-59 (2003.3)

[3] Liang Shilong, HaoZuquan. The design and implementation of the digital IF receiver for a PD radar seeker. System Engineering and Electronics, Vol 25, pp. 934-937, 984 (2003.8)

[4] Wei Yijia. Digital IF receiver and algorithm research. University of Electronics Science and Technology of China, 2005.6

[5] Zhu Qun. Design of digital IF receiver and hardware implementation. National University of Defense Technology, 2004.11

[6] Li Tao, Han Yueqiu. Trigonometric function generator based on pipeline CORDIC. System Engineering and Electronics, Vol 22, pp. 85-87 (2000.4)

[7] LanJinqiao, Sun Xiaowen, Wu Shunjun. Choice of digital quadrature demodulation based on polyphase filter. Computer Engineering and Applications, Vol 18, pp. 215-224 (2004)

[8] Wu Tailiang, Liu Zheng. Design of time domain pulse compressor based on FPGA. Guidance &Fuze, Vol 28, pp. 45-50 (2007.12)

[9] He S, Torkelson M. Designing pipeline FFT processor for OFDM (de) modulation. International Symposium on Signals, Systems, and Electronics. New York, pp. 257 --- 262 (1998)

[ 10] Li' Wei, Sun Jinping, Wang Jun, et al. Implementation of 32k points ultra high speed FFT processor based on FPGA devices. Journal of Beijing University of Aeronautics and Astronautics, Vol 33, pp. 1440-1443

[11] XiaodongRen, Wen Bo. CPLD/FPGA. Advanced ApplicationsDevelopment Guide. First

Edition. Beijing: Electronic IndustryPress,2003,pp:43-46

[12] Wayne Wlof. System Design Based on FPGA.Beijing; Machinery Industry Press,2006,pp:25-28

[ 13] UweMeyer-Baese. Digital Signal Processing with Field ProgrammableGate Arrays, Second

Edition, Springer Ltd,2006.6,pp:219-223

[14] Peiqing Cheng. Digital signal processing turorial.Second Edition.Beijing: Tsinghua University Press,20 01,pp : 13 9-15 0

51

1151 C-N.Liu, J.-Y.Jou. Efficient Coverage Analysis Metric for HDL Design Validation.IEEP

roceedings online no.200102.03.http://eda.ee.nctu.edu.tw, 20033582

116] Chu, S. and Burrus, C. "Multirate Filters Designs UsingComb Filters," IEEE Trans. Circuits

and Systems, Vol.CAS-31, pp. 913-924, (Nov. 1984).

1 17] Hogenauer, E. "An Economical Class of Digital Filtersfor Decimation and Interpolation," IEEE

Trans. Acoust.Speech and Signal Proc., Vol, pp. 155-622, (April 1981).

II Powell, S. "Design and implementation Issues ofAll-digital Broadband Modems," DSP World

WorkshopProceedings, pp. 127-142, (Sept. 13-16, 1998).

1191 Frerking, M. "Digital Signal Processing inCommunications Systems," Chapman &Hall, pp.

330,(1994).

1201 http.z/wwwxilinx.com/ipcenter, datasheet for DigitalDown Converter V1.0 , pp. 27, (2002).

1211 Shi Ying, XueXiaogang, Zhongxinchao .FPGA/CPLD design tools:XILINX ISE Used Details.

Beijing: People's Posts & TelecomPress, 2005.

1221 Tian Yun, XuWenbo and so on. Wireless Communications FPGA design. Beijing: Electronic

Industry Press, 2008.2

1231 Wang Jian, ZhuoXingwang. Digital applications and design basedVerilog HDL. Beijing:

National Defense Industry Press, 2007.

1241 [3aiJuxian. Direct Digital Synthesis. Xi'an: Xi'an JiaotongUniversity Press, 2007.7

1251 Michael D. Ciletti. Verilog HDL advanced digital design. Beijing: Electronic Industry Press,

2007

1261 Xilinx ISE 10.1 FPGA / CPLD Design Guidelines. Beijing: People's Posts & Telecom Press,

2008.8

1271 Wang Xudong. MATLAB and Its Application in FPGA application.Beijing: National Defense

Industry Press, 2006.

128111. T. Nicholas, H. Samueli, "An Analysis of the OutputSpectrum of Direct Digital Frequency

Synthesizers in thePresence of Phaseaccumulator Truncation", 1987, pp.495502.

1291Soenkemehrgard, "Noise Spectra of Digital Sine GenerationUsing the TableLookup Method",

Vol. ASSP31, NO. 4, August,1983.

130] V. Reinhardt, K. Gould, K. McNab, and M. Bustamante, "AShort Survey of Frequency

Synthesizer Techniques", May 1986, pp. 355-365.

1311 B. Goldberg,LLHtechnology Publishing, ISBN: 187, 1999.

52

[32]DirectDigital Frequency Synthesizer a basic tutorial, OsicomTechnologies Inc., accessed on Feb 19, 2009;http://www2.itu.edu.tr/—pazarci/ddstutor.html

[33] J. Vankka, "Methods of Mapping from Phase to Sine Amplitudein Direct Digital Synthesis", vol. 44, pp. 526534,March 1997.

[34]J. Tierney, C.M. Rader, and B. Gold, "A Digital frequencysynthesizer,. " IEEE Trans. Audio Electroacoust, vol. AU19, pp.48-57, 1971.

[35] AlinGrama, and Gabriel Muntean, "Direct Digital FrequencySynthesis Implemented on a FPGA

Chip," in,Maienthal, Germany, 2006, pp. 92-97

[36] A. M. Sodagar, G. R. Lahii, "A Pipelined ROMLessArchitecture for SineOutp'ut Direct Digital

FrequencySynthesizers Using the SecondOrder ParabolicApproximation" , vol. 48, no. 9, September,2001

[37]J. Logue, "Xilinx Application Note XAPP154", URL:

http://www.xilinx.com/support/documentation/application_note s/xapp 1 54.pdf, September 23,

1999.

[38]J.M.P. Langlois, and D. Al Khalili, "Phase to Sinusoid Amplitude Conversion Techniques for

Direct Digital FrequencySynthesis," in Dec. 2004, pp. 519-528.

[39]J. Rogers, C. Plett and F. Dai. Artech House Publishers,ISBN: 153, 2006.

[40]http://www.digilentinc.com/ accessed on Aug 20, 2009 .

53