Pertemuan 3 Karakteristik Logik Gerbang MOSFET
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1 Pertemuan 3 Karakteristik Logik Gerbang MOSFET Matakuliah : H0362/Very Large Scale Integrated Circuits Tahun : 2005 Versi : versi/01
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Pertemuan 3 Karakteristik Logik Gerbang MOSFET. Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01. Learning Outcomes. Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menjelaskan karakteristik logik gerbang MOSFET. a = 0. a = 1. y. y. x. - PowerPoint PPT Presentation
Transcript of Pertemuan 3 Karakteristik Logik Gerbang MOSFET
1
Pertemuan 3
Karakteristik Logik Gerbang MOSFET
Matakuliah : H0362/Very Large Scale Integrated Circuits
Tahun : 2005
Versi : versi/01
2
Learning Outcomes
Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menjelaskan karakteristik logik gerbang MOSFET.
3
Ideal Switch
a
b
a . 1
b . 11
+
f = a + b
Hubungan paralel:
x y
a = 0
x y
a = 1
buka tutup
a b
1a . 1 (a . 1) . b
g = a . b
Hubungan seri:
Assert-high
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Ideal Switch
a b
1a . 1 (a . 1) . b
g = a . b
Hubungan seri:
Assert-lowx y
a = 1
x y
a = 0
buka tutup
Gerbang NOT:
f = a . 1 + a . 0 = a
a
a
a . 1
a . 0
1
+
0
a
1
0
f(x) = a . 1 + a . 0Mux
5
MOSFET Switch
Source Drain Drain Source
Gate Gate
nFET pFET
Simbol
+
-
+
-
VDD
VSS
Power supply
VDD > 0 V
VSS < 0 V
Ke chip
Dual power supply voltages
+
-
VDDRangkai
anCMOS
Single voltage power supply
0
VDD
Logik 1
Logik 0
Tak tentu
6
x y = ?
a = 0
x y = x
a = 1
buka tutup
nFET
x y = ?
a = 1
x y = x
a = 0
buka tutup
pFET
MOSFET Switch
7
nFET
VA
Gate
Source
Drain
+
-VGSn
Mn
Ke VDD
VA
VTn
VDD
A = 1 Mn ON
A = 0 Mn OFF
VA
Gate
Source
Drain
+
-V
SGp
Mp
VDD
VA
(VDD - |VTn
|)
VDD
A = 1 Mp OFF
A = 0 Mp ON
pFET
Ke ground
Threshold voltage
MOSFET Switch
8
in out
VDD
Vx = 0 V
+
-
+
-V
y = 0 V
in out
VDD
Vx = V
DD
+
-
+
-V
y = V
DD - V
Tn
+-
VTn
in outV
x = 0 V
+
-
+
-V
y = |V
Tp|
|VTp
|-+
Pass CharacteristicsnFET
in outV
x = V
DD
+
-
+
-V
y = V
DD
pFET
MOSFET Switch
9
Gerbang Logik CMOS
Contr
ol blo
cka
bcin
puts
1
0 VSS
SWn
SWp
VDD
f (a, b, c)
outputC
ontr
ol blo
ck
a
bcin
puts
1
0 VSS
buka
tutup
VDD
f = 1
Contr
ol blo
ck
a
bcin
puts
1
0 VSS
tutup
buka
VDD
f = 0
10
Gerbang Logik CMOS
Gerbang NOTKe VDD
Mp
Mn
pFET
nFET
x
Ke VSS
Pasangan complement CMOS
Ke VDD
Mp ON
Mn OFF
X = 0
Ke VSS
Ke VDD
Mp OFF
Mn ON
X = 1
Ke VSS
xx x x
0 11 0
Mp
Mn
x
VDD
x
11
Gerbang Logik CMOS
Gerbang NOR
A B F0 0 10 1 01 0 01 1 0
A
B
F0123
01
AB
1000
MuxF = A + B
Mpx Mpy
Mnx
Mny
A B
1 . A . B
0 . B
0 . A
F = A + B
VDD
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Gerbang Logik CMOS
Gerbang NAND0123
01
AB
1110
MuxF = A . B
Mpx
Mnx Mny
A B
Mpy
1 . A
F = A . B
VDD
1 . B
0 . A . B
A B F0 0 10 1 11 0 11 1 0
A
B
F
13
Gerbang Logik CMOS
N
Fan-out N Fan-in M
M
14
Gerbang Logik CMOS
Gerbang Complex
A B
VDD
1 . A
C
1 . B . C
F = A . 1 + (B . C) . 1
A
BC
BC
A
F F
F = A . (B + C)
= A + (B + C)
= [A + (B . C)] . 1
= A . 1 + (B . C) . 1
AB C
0 . [A . (B + C)]
0 . (B + C)
F = 0 jika A = 1 AND (B+C ) = 1
0 . [A . (B + C)]
VDD
B
C
A
B
A
F
C
15
Clock dan Aliran Data
1
1
0 T 2T
time
time
T
1 f
hold t 2
T
Blok 1
Blok 2
Blok 3
System clock
Block level system timing diagram
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RESUME
• Ideal Switch: assert high, assert low.
• MOSFET Switch: nFET, pFET.
• Gerbang logic CMOS.
• Clock dan aliran data.
