PEMANCAR AMPLITUDO MODULASI DENGANAmplitude Modulation), modulasi frekuensi (FM-Frequency...

PEMANCAR AMPLITUDO MODULASI DENGAN

FREQUENCY HOPPING

TUGAS AKHIR

Diajukan untuk memenuhi salah satu syarat

memperoleh gelar Sarjana Teknik pada

Program Studi Teknik Elektro

Disusun oleh

ANDREAS RONY MARLINO

NIM : 015114033

PROGRAM STUDI TEKNIK ELEKTRO

FAKULTAS SAINS DAN TEKNOLOGI

UNIVERSITAS SANATA DHARMA

YOGYAKARTA

2007

AM TRANSMITTER WITH FREQUENCY HOPPING

FINAL PROJECT

Presented as Partial Fulfillment of the Requirements

to obstain the Sarjana Teknik Degree

in Electrical Engineering

By :

ANDREAS RONY MARLINO

Student Number : 015114033

ELECTRICAL ENGINEERING STUDY PROGRAM

SCIENCE AND TECHNOLOGY FACULTY

SANATA DHARMA UNIVERSITY

YOGYAKARTA

2007

ii

PERNYATAAN KEASLIAN KARYA

“Saya menyatakan dengan sesungguhnya bahwa tugas akhir yang saya tulis ini

tidak memuat karya atau bagian karya orang lain, kecuali yang telah disebutkan dalam

kutipan dan daftar pustaka, sebagaimana layaknya karya ilmiah”

Yogyakarta, September 2007

Penulis,

Andreas Rony Marlino

v

Tugas akhir ini dipersembahkan untuk :

Yesus Kristus dan Bunda Maria atas karuniaNya

Kedua orang tuaku tercinta (ST,Marli Subroto dan Lusia Ema

Sudarmi) Kedua kakakku (Mas Didik Mbak Yeni dan Ms Heru)

Adikku (Dony “Itong”)

Widy.......

Teman-temanku semua

yang selalu memberikan semangat, dorongan, dan doa.

Janganlah cemas, Janganlah takut. Di dalamTuhan berlimpah rahmat. Janganlah cemas, janganlah takut, serahkan Tuhan.

(Lagu dari Taize)

vi

INTISARI

Teknik frequency hopping (FH) merupakan salah satu metode transmisi data

dalam bidang telekomunikasi. Dengan frequency hopping, gangguan-gangguan pada

telekomunikasi seperti jamming dan noise dapat dikurangi. Penelitian ini bertujuan

untuk menghasilkan pemancar AM dengan frequency hopping.

Pemancar AM dengan frequency hopping ini terdiri tiga bagian utama yaitu

phase locked loop Driver dan Bouster. Phase locked loop berfungsi sebagai

pembangkit sinyal carrier. Komponen utama phase locked loop adalah pembangkit

frekuensi referensi, phase detector, low pass filter, voltage controlled oscillator,

pembagi terprogram dan pengendali data masukan pembagi terprogram. Pemancar ini

bekerja dengan frekuensi carrier yang bergantian pada dua frekuensi yang berbeda

yaitu 1000KHz dan 1050 KHz dengan periode hopping 0,5 detik.

Hasil dari penelitian ini adalah pemancar AM dengan frequency hopping yang

dapat bekerja secara efektif dan dapat digunakan baik di dalam ruangan maupun di

luar ruangan dalam radius 5 meter. Akan tetapi sinyal yang ditangkap penerima AM

tetap disertai noise yang berasal dari pemancar itu sendiri dan lingkungan sekitar.

Kata kunci : frequency hopping, phase locked loop, AM

vii

ABSTRACT

Frequency hopping technique is one of data transmission method in

telecommunication. Frequency hopping can minimize the effect of the

telecommunication disturbances such as jamming and noise. This research goal aim is

to produce AM transmitter with frequency hopping.

The transmitter consists of three phase locked loop (PLL) that serve as carrier

signal generator, driver and booster. The main component of PLL is reference

frequency, phase detector, low pass filter, voltage controlled oscillator, programmed

divider and programmed divider input data controller. The transmitter operates in two

carrier frequency, 1000 KHz and 1050 KHz with 0.5 second hopping period.

The result of the research is that the transmitter with hopping frequency can

work effectively and can be used both indoor and outdoor in the range of 5 meter.

However, the signal that is received by AM receiver still followed by noise that comes

from the transmitter itself and from the receiver environment.

Keyword : frequency hopping, phase locked loop, AM.

viii

KATA PENGANTAR

Puji dan syukur kepada Tuhan Yang Maha Esa atas segala kasih dan karunia-

Nya sehingga penulis dapat menyelesaikan penulisan skripsi ini. Skripsi ini berjudul :

Pemancar AM dengan Frequency Hopping.

Skripsi ini ditulis bertujuan untuk memenuhi salah satu syarat dalam

memperoleh gelar sarjana teknik pada program studi Sains dan Teknologi Universitas

Sanata Dharma. Penulisan skripsi ini didasarkan pada hasil-hasil yang penulis peroleh

berdasarkan pada perancangan alat, pembuatan alat, dan sampai pada pengujian alat.

Penulisan skripsi ini dapat diselesaikan berkat bantuan, dorongan, dan

bimbingan dari berbagai pihak. Pada kesempatan ini penulis ingin mengucapkan

terima kasih yang sebesar-besarnya kepada :

1. Yesus Kristus dan Bunda Maria atas rahmat dan karuniaNya

2. Bapak Damar Wijaya, S.T, M.T. sebagai dosen pembimbing I dan Alexius

Rukmono, S.T. sebagai pembimbing II yang telah bersedia memberikan ide,

saran, bimbingan, dan waktu untuk penulis dalam menyelesaikan tugas akhir.

3. Dosen-dosen Teknik Elekto, terimakasih atas segala ilmu dan pengetahuannya

yang sangat membantu dalam menyelesaikan studi di sini…

4. Laboran teknik elektro Mas soer dan Mas Mardie, atas lab nya dan ilmu yang

diberikan.

5. Bapakku dan ibukku (Marli dan Darmi)…. Makasih banget ya, buat semua

cinta dan kasih sayang yang gak pernah habis buat Rony…

x

6. Kedua kakakku dan adikku Mas Didik, Mbak Yeny, Dony”Itong” yang telah

memberi semangat dan setia membimbingku......

7. Roberta Maria Widyarani Boedi Harga, yang telah menjadi teman..

Terimakasih buat cinta dan kesabarannya..

8. Teman-teman “senasib hopping” Widi”03,Merry ’03 dan Kelik’02, atas kerja

sama selama pembuatan tugas akhir.

9. Teman-teman satu angkatan 2001 yang memberikan ide masukan dan

dorongan pada penulis, Indra”Klowor”, Maikel, Parto dan yang lainnya yang

tidak disebutkan satu-persatu.

10. Teman-teman “Tumindak Ngiwo” Kopet, Zigot, Barjo, Si Y, Windra, Sapi,

Kowok yang telah menemani penulis dalam keadaan suka dan duka.

Terimakasih atas dinamika selama ini......

11. Semua pihak yang tidak mungkin disebutkan satu persatu.. Matur Nuwun

Sanget!!!

Penulis sadar bahwa pada penulisan skripsi ini banyak terdapat kesalahan dan

kekurangannya, oleh sebab itu kritik dan saran dari berbagai pihak sangat diharapkan

agar penulis dapat lebih maju dan lebih baik.

Yogyakarta, 20September 2007

Penulis,

Andreas Rony Marlino

x

DAFTAR ISI

Hal.

HALAMAN JUDUL……………………………………………………… i

LEMBAR PENGESAHAN PEMBIMBING……………………………. iii

LEMBAR PENGESAHAN PENGUJI………………………………….. iv

PERNYATAAN KEASLIAN KARYA…………………………………. v

HALAMAN PERSEMBAHAN………………………………………….. vi

INTISARI…………………………………………………………………. vii

ABSTRACT………………………………………………………………... viii

KATA PENGANTAR……………………………………………………. ix

DAFTAR ISI……………………………………………………………… xi

DAFTAR GAMBAR……………………………………………………... xiv

DAFTAR TABEL………………………………………………………… xvii

DAFTAR LAMPIRAN…………………………………………………... xviii

BAB I PENDAHULUAN

A. Judul……………………………………………………………………

B. Latar Belakang………………………………………………………...

C. Pembatasan Masalah…………………………………………………..

D. Tujuan dan Manfaat Penelitian………………………………………...

E. Metodologi Penelitian………………………………………………….

F. Sistematika Penulisan……………………………………………………

1

1

2

2

3

3

BAB II DASAR TEORI

A. Blok diagram pemancar AM .............................................................

5

6

xi

B. Phase locked loop(PLL).

1. Detektor Fasa............................................................................

2. LPF (low pass filter)...............................................................

3. Osilator ..................................................................................

a. Osilator referensi.....................................................

b. Osilator terkendali tegangan....................................

4. Operasi Phase Loced Loop....................................................

C. Transistor sebagai penguat awal........................................................

D. Transistor Sebagai Penguat Daya........................................................

E. Timer 555............................................................................................

F. Frequency hopping.............................................................................

7

8

10

12

12

13

13

14

15

20 22

BAB III PERANCANGAN ALAT

A. Blok Diagram....................................................................................

B. Osilator dengan PLL.........................................................................

1. Rangkaian osilator referensi.................................................

2. Rangkaian VCO, Filter dan Detektor Fasa...........................

3. Rangkaian Pembagi Terprogram..........................................

4. Rangkaian timer 555............................................................

C. Rangkaian Penggerak (Driver).........................................................

D. Rangkaian Booster............................................................................

E. Modulator AM..................................................................................

24

24

25

26

27

29

30

30

31

32

BAB IV HASIL DAN PEMBAHASAN

A. Hasil Perancangan …………………………………………………..

33

33

xii

B. Pengujian dan Pengukuran Alat …………………………………….

1. Pengujian Transmisi pemancar……………………………...

2. Pengujian Saat Hopping …………………………………….

3. Pengujian Jarak Pancar …………………………………….

C. Pengujian Setiap Blok

1. Frekuensi Pembagi 10 KHz…………………………………

2. Frekuensi referensi 1KHz…………………………………..

3. Voltage Controlled Oscillator………………………………

4. Pembagi Terprogram……………………………………….

5. Phase detector dan Low Pass Filter……………………………

6. Timer………………………………………………………………

7. Analisa Phase Lokced Loop

8. Driver dan Booster………………………………………....

33

33

37

39

40

40

42

43

45

46

47

49

50

BAB V KESIMPULAN DAN SARAN

A. Kesimpulan…………………………………………………………..

B. Saran…………………………………………………………………

56

56

56

DAFTAR PUSTAKA……………………………………………………. 57

xiii

DAFTAR GAMBAR

Hal.

Gambar 2.1 Diagram blok sistem pemancar AM ……………………....... 6

Gambar 2.2 Diagram Blok system PLL ………………………………..... 7

Gambar 2.3 Karakteristik beda fasa ……………………….…………..... 8

Gambar 2.4 IC 74HC4046………………………………………………. 10

Gambar 2.5 (a) Filter RC pada rangkaian PLL ........................................

(b) Tanggapan frekuensi ………………………..................

10

Gambar 2.6 Blok diagram IC 74HC4046 ……………………………..... 12

Gambar 2.7 Ragam CE dengan prategangan Umpan-balik kolektor.......... 14

Gambar 2.8 Penguat daya CE dengan prategangan pembagi tegangan...... 16

Gambar 2.9 Rangkaian untuk mencari RTH ……………………………... 16

Gambar 2.10 Rangkaian untuk mencari VTH ……………………………... 17

Gambar 2.11 Rangkaian penguat daya CE dengan pembagi tegangan (a).

Rangkaian ekivalen dc (b). Rangkaian ekivalen ac................

18

Gambar 2.12 Garis beban dc dan ac dari transistor pada rangkaian

penguat daya CE dengan pembagi tegangan..........................

19

Gambar 2.13 IC LM555 ………………………………………….……….. 20

Gambar 2.14 IC LM555 sebagai multivibrator astabil …………………… 21

Gambar 2.15 Bentuk gelombang keluaran ........................................…….. 21

Gambar 2.16 Teknik frequency hopping …………………………………. 22

Gambar 2.17 Interferensi pada transmisi Frequency Hopping ......……….. 23

Gambar 3.1 Diagram Blok Pemancar AM ………………………………. 24

Gambar 3.2 Rangkaian pembangkit frekuensi 1Khz……...……………... 25

Gambar 3.3 Blok diagram IC 74HC4046 ………………………………. 26

xiv

Gambar 3.4 Rangkaian Fasa detector dan VCO ……………………….. 27

Gambar 3.5 IC TC9122P ………………………………………………… 28

Gambar 3.6 Diagram blok IC TC9122P ……………………………..….. 29

Gambar 3.7 Rangakaian Timer ………………………………………….. 30

Gambar 3.8 Rangkaian Penggerak ………………………………….….... 30

Gambar 3.9 Rangkaian Booster ………………………………………..… 31

Gambar 3.10 Rangkaian modulator …………………………………….… 32

Gambar 4.1 Blok pemancar hopping …………………………………….. 33

Gambar 4.2 Pengujian transmisi pemancar ……………………………… 34

Gambar 4.3 Spektrum frekuensi dengan frekuensi carrier 1000 KHz. …. 34

Gambar 4.4 Spektrum frekuensi dengan frekuensi carrier 1050 KHz … 35

Gambar 4.5 Sinyal informasi 4 kHz yang dikirim ….………………….. 36

Gambar 4.6 Modulasi amplitudo dengan gelombang carrier 1000 KHz 36

Gambar 4.7 Modulasi amplitudo dengan gelombang carrier 1050 KHz.

Gambar 4.8. Spektrum frekuensi audio pada penerima AM dengan

frekuensi carrier 1000 KHz…………………………………

Gambar 4.9. Spektrum frekuensi audio pada penerima AM dengan

frekuensi carrier 1050 KHz………………………………

37

37

37

Gambar 4.10 Pengujian kestabilan pemancar saat hopping ..……………. 38

Gambar 4.11 Gelombang output IC 4060 frekuensi referensi 10 KHz ….. 41

Gambar 4.12 Gelombang output IC 4060 frekuensi referensi 1 KHz ..…. 43

Gambar 4.13 Sinyal output rangkaian osilator 1000 KHz …………..... 44

Gambar 4.14 Sinyal output rangkaian osilator 1050 KHz………………. 45

Gambar 4.15 Gelombang output pembagi terprogram ………………...… 46

Gambar 4.16 (a) Sinyal output IC LM 555……………………………….. 48

xv

(b) Sinyal output IC LM 555 TON……………………………………….. 48

Gambar 4.17.a. Gelombang output driver frekuensi carrier 1000 KHz ….

Gambar 4.17.b. Spektrum frekuensi driver dengan frekuensi carrier 1000

KHZ………………………………………………….

51

51

Gambar 4.18.a. Gelombang output booster frekuensi carrier

1000KHz………………………………………………….

Gambar 4.18.b. Spektrum frekuensi booster dengan frekuensi carrier

1000KHz………………………………………………..

52

52

Gambar 4.19.a. Gelombang output rangkaian driver frekuensi carrier

1050KHz …………………………………………………

Gambar 4.19.b. Spektrum frekuensi driver dengan frekuensi carrier 1050

KHz…………………………………………………

53

54

Gambar 4.20.a. Gelombang output rangkaian boster frekuensi carrier

1050 KHz…………………………………………………. 54

Gambar 4.20.b. Spektrum frekuensi booster dengan frekuensi carrier

1050 KHz………………………………………………… 55

xvi

DAFTAR TABEL

Hal. Tabel 2.1 Pembagian frekuensi dalam bentuk BCD …………………. 30

Tabel 4.1 Data hasil pengujian pemancar saat hopping.………..…….. 39

Tabel 4.2 Data hasil pengukuran jarak pancar ……………….………. 40

Tabel 4.2 Data hasil PhaseLokced Loop……………………………… 50

xvii

DAFTAR LAMPIRAN

Rangkaian Lengkap Pemancar Dengan Frequency Hopping……………..

Data spectrum frekuensi pada penerima AM……………………………..

L1

L2

Datasheet 74HC/HCT4046A……………………………………………... L3

Datasheet CD 40460…………………………………………………… L4

Datasheet IRF510………………………………………………………... L5

Datasheet TC9122P………………………………………………………. L6

Datasheet 2N3904………………………………………………………. L7

Datasheet 74LS90……………………………………………………….. L8

Datasheet LM555………………………………………………………… L9

xviii

BAB I

PENDAHULUAN

A. Judul

Pemancar AM dengan Frequency Hopping

B. Latar Belakang

Komunikasi pada dasarnya merupakan pertukaran informasi antara dua

tempat yang berjauhan. Informasi bisa berupa sinyal suara dan gambar. Sinyal

suara tidak dapat dipancarkan secara langsung. Agar dapat dipancarkan, sinyal

suara harus ditumpangkan pada sinyal radio dengan frekuensi pembawa yang

lebih tinggi dari frekuensi sinyal suara tersebut.

Metode untuk menumpangkan sinyal suara pada sinyal radio disebut

modulasi[1]. Memodulasi artinya meregulasi atau menyesuaikan parameter suatu

sinyal carrier berfrekuensi tinggi dengan sinyal informasi berfrekuensi yang lebih

rendah. Modulasi yang biasa digunakan adalah modulasi amplitudo (AM-

Amplitude Modulation), modulasi frekuensi (FM-Frequency Modulation) dan

modulasi fasa (PM-Phase Modulation).

Pada penelitian ini dibuat sebuah pemancar dengan modulasi amplitudo.

Pada pemancar AM, amplitudo sinyal carrier berubah seiring dengan perubahan

sinyal informasi.

1

Kendala yang dihadapi pada pemancar AM adalah sinyal informasi yang

dipancarkan akan mengalami variasi amplitudo (fading), mendapat interferensi

dari dan noise. Sehingga sinyal informasi yang diterima akan berubah dan kualitas

informasi yang diterima berkurang. Cara mengatasi permasalahan ini adalah

dengan teknik frequency hopping. Teknik frequency hopping akan diterapkan

pada pemancar AM yang dibuat.

C. Batasan Masalah

Perancangan perangkat pemancar AM dengan frequency hopping ini

memiliki spesifikasi sebagai berikut:

1. Menggunakan frekuensi osilator 1000 Khz dan 1050 Khz.

2. Menggunakan bandwidth 50 Khz.

D. Tujuan dan Manfaat

1. Penelitian ini bertujuan untuk membuat pemancar AM dengan

frequency hopping, serta dapat menerapkan teknologi hopping dalam

pemancar radio.

2. Mengatasi fading dan jamming pada system komunikasi termodulasi

amplitudo

Manfaat dari penelitian ini diharapkan dapat menjadi rujukan untuk

mengembangkan kahandalan dan keamanan informasi pada komunikasi

termodulasi amplitudo.

2

E. Metodologi penelitian

Laporan tugas akhir ini disusun berdasarkan hasil pengamatan dan

penelitian. Untuk dapat merencanakan dan membuat peralatan, dilakukan

langkah-langkah sebagai berikut :

1. Studi literatur tentang pemasalahan yang ada, yaitu tentang peralatan

yang akan dibuat termasuk cara kerja, dan sekaligus cara-cara

merencanakan dan membuat peralatan.

2. Perencanaan peralatan dengan spesifikasi tertentu sesuai batasan

masalah.

3. Membuat peralatan dari bagian perbagian yang kemudian diuji.

Bagian-bagian tersebut lalu akan disatukan menjadi sebuah sistem dan

akan diuji kembali secara menyeluruh.

F. Sistematika Penulisan

Sistematika penulisan pada tugas akhir ini adalah:

BAB I PENDAHULUAN

Berisi Latar Belakang Masalah, Batasan Masalah, Tujuan dan

Manfaat Penelitian, Metodologi Penelitian, dan Sistematika

Penulisan.

BAB II DASAR TEORI

Membahas dasar teori yang berhubungan dengan Pemancar AM

dan frequency hopping.

BAB III PERANCANGAN

3

Menjelaskan tentang perancangan pemancar AM dengan frequency

hopping.

BAB IV HASIL DAN PEMBAHASAN

Membahas data hasil pengujian alat dan analisa pembahasan dari

hasil penelitian

BAB V KESIMPULAN DAN SARAN

Berisi tentang kesimpulan dan saran dari hasil penelitian

4

BAB II

DASAR TEORI

Pada pemancar AM, amplitudo sinyal pembawa akan diubah seiring dengan

perubahan sinyal informasi yang dimasukkan. Sedangkan frekuensi sinyal

pembawanya relatif tetap. Dalam proses pemancaran dari stasiun pemancar ke

penerima, sinyal akan mengalami variasi amplitudo(fading), mendapat interferensi,

noise, atau bentuk-bentuk gangguan lainnya. Akibatnya, informasi yang terkirim

akan berubah dan mutu informasi yang diterima berkurang.

Cara mengurangi kerugian yang diakibatkan oleh variasi amlitudo, noise, dan

interferensi cukup sulit. Frequency hopping adalah salah satu metoda untuk

mengatasi masalah tersebut. Frequency hopping atau lompatan frekuensi sinyal

pembawa secara periodis diatur oleh algoritma tertentu[2]. Frekuensi ini akan

membawa informasi selama perioda tertentu dan berpindah ke frekuensi yang lain,

begitu seterusnya.

Frequency hoping merupakan salah satu dari teknik spektrum tersebar

(spread spectrum) dengan bandwidth yang digunakan jauh lebih lebar dari bandwidth

minimum yang diperlukan untuk mengirimkan informasi yang sama jika

meggunakan frekuensi pembawa tunggal[3].

Penulis mencoba untuk menerapkan teknik frequency hopping dalam

pemancar AM ini. Adapun rangkaian pemancar AM ini berisi osilator dengan PLL

5

(phase locked loop) dan PLL sendiri dibangun oleh osilator acuan menggunakan

osilator kristal dan pembagi osilator, detektor fasa dan osilator terkendali tegangan,

filter pelewat bawah, pembagi terprogram dan timer.

A. Blok diagram pemancar AM

Bentuk dasar pemancar AM ditunjukkan pada gambar 2.1.

Osilator

Booster Driver

Modula

tor

Gambar 2.1 Diagram blok sistem pemancar AM [1]

Keterangan:

1. Osilator digunakan sebagai penghasil frekuensi yang akan dimodulasi

oleh sinyal informasi.

2. Driver berfungsi untuk memperbesar penguatan tegangan karena

amplitudo sinyal keluaran osilator masih kecil sinyalnya.

3. Booster berfungsi sebagai penguat akhir untuk menguatkan daya

sinyal termodulasi ke antena supaya dapat dipancarkan

4. Modulator adalah pengubah parameter sinyal pembawa agar informasi

yang akan ditumpangkan pada sinyal pembawa lewat sebuah trafo

modulator mempunyai daya yang cukup.

6

5. Antena pemancar digunakan untuk memancarkan sinyal termodulasi

yang berupa sinyal elektomagnetik.

B. Phase locked loop(PLL).

Rangkaian PLL merupakan rangkaian umpan balik kalang tertutup yang

menghasilkan sinyal output yang tersinkronisasi (lock) dengan sinyal input. Aplikasi

PLL antara lain sebagai demodulator AM, FM, deteksi FSK, frequency multiplyer.

PLL bisa dibangun dari beberapa rangkaian atau sebuah IC (Integrated Circuit).

Diagram blok PLL terlihat pada gambar 2.2.

iiθω V3

00ϑω

Gambar 2.2 Diagram Blok system PLL [1]

Detektor fasa (Kf)

Filter LPF

VCO (Kv)

Sinyal input sinusoidal atau kotak dengan frekuensi iω dan fasa iθ . Sinyal

output VCO (voltage controlled oscillator) sinusoidal atau kotak dengan frekuensi

0ω fasa 0θ merupakan input kedua detektor fasa. Output PLL bias V3 atau 0ω

iω =dt

d iθ dt

d 00

θω = ………………………………(2.1)

Karakteristik komponen yang disederhanakan :

7

1. Detektor Fasa

Bertugas untuk membandingkan fasa antara sinyal input dari pembagi

terprogram dengan sinyal osilator referensi dan hasilnya berupa ayunan tegangan

sesuai magnitude beda fasa.

Beda fasa membandingkan beda fasa antara 2 sinyal, sinyal yang pertama

merupakan referensi dan yang lain adalah sinyal yang akan dibandingkan. Apabila

frekuensi sinyal input lebih tinggi dari frekuensi sinyal acuan maka terjadi beda fasa

( )θΔ sebesar πθ n+=Δ atau frekuensi sinyal input lebih rendah dari frekuensi

sinyal acuan maka πθ n−=Δ , dan jika frekuensi sinyal input sama dengan

frekuensi sinyal acuan maka tidak terjadi beda fasa atau .0=Δθ

Secara sederhana beda fasa kedua sinyal dapat dilihat dari perbedaan perioda

sinyal, jarak waktu antara puncak naik sinyal yang satu dengan yang lain, yang

kemudian dikonfersikan menjadi tegangan.

V

Kf

0θθθ −=Δ i

Gambar 2.3 Karakteristik beda fasa

Dari gambar diatas didapat rumusan seperti dibawah ini

VS=Kf- iθΔ …………………………………………………….(2.2)

Vi=Kf( 0θθ −i )……………………………………………….….(2.3)

Penguatan kalang terbuka pada blok diagram system PLL dengan persamaan

H(S)+G(S) = KP + KF + KO + KN……………………………….…...(2.4)

8

Dimana:

KF = Panguatan detector fasa

KP = Penguatan Low-Pass Filter

KO = KV /s Penguatan VCO

KN = 1/n rasio pembagi

Dalam pemograman counter (KN) diperoleh

Nmin = Langkah

out

ff min …………………………………………………,,,(2.5)

Nmax = Langkah

out

ff max ……………………………………………………(2.6)

Dimana

Nmin : Konstanta minimum perbandingan frekuensi minimum dan

maxsimum

Nmax : Konstanta maxsimum perbandingan frekuensi minimum dan

maxsimum

Penguatan pada detektor fasa dapat dihitung dengan persamaan

π4CC

pV

K = ………………………………...……………..……….(2.7)

Detektor fasa dapat dibangun dengan IC 4046 yang didalamnya sudah

termasuk VCO. Dalam IC4046 terlihat pada gambar dibawah ini

9

U5

74HC4046

34

14

6

75

1112

12

13

9

1015

CINVCOUT

SIN

CX

CXINHR1R2

PPP1

P2

VCOIN

DEMOZEN

Gambar 2.4 IC 74HC4046

Output

R2

Input

C1

R1

2. LPF (low pass filter)

Tegangan keluaran dari pembanding fasa, harus ditapis dari sinyal pemodulsi.

Maka penapisan diperlukan agar tegangan kendali pada VCO meperoleh tegangan dc

murni. Untuk itu diperlukan filter pelewat rendah. Filter pelewat rendah ini dapat

dibangun dengan kombinasi resistor dan kapasitor seperti terlihat pada gambar.

Redaman (dB)

f

(a) (b)

Gambar 2.5 (a) Filter RC pada rangkaian PLL

(b) Tanggapan frekuensi

10

Untuk mencari frekuensi redaman max atau fcutoff dari gambar diatas dengan

persamaan:

f cutoff = RCπ21 …………............………..………….…………..(2.8)

Penguatan pada filter dapat dihitung dengan rumusan:

s

sK F )(11

21

2

τττ++

+= ……………………………….………….…(2.9)

Dimana 231 CR=τ dan 242 CR=τ

Penjumlahan karakteristik pada LPF dirumuskan

1 + H(S) G(S) = 0 ………………………………………………..(2.10)

Didapat

( ) ( ) 01

2121

22 =+

++

++

τττττ NVPNVP KKK

sKKK

s ……………………......(2.11)

Frekuensi natural Nω dihitung dengan rumusan:

( )21 ττω

+= NVP

NKKK

………………………..…………………….(2.12)

Nilai redamanξ dihitung dengan

( ) ⎥⎦

⎤⎢⎣

⎡+

+⎥⎦

⎤⎢⎣

⎡=

21

212

1ττ

τω

ξ NVP

N

KKK…………………..……….……......(2.13)

11

3. Osilator

Osilator merupakan rangkaian yang dapat membangkitkan sinyal sendiri,

pada pita frekuensi tertentu. Osilasi dapat dibangkitkan dengan adanya umpan balik

positif. Pada penelitiaan ini akan digunakan dua jenis osilator dalam PLL ini yaitu

osilator referensi dan osilator terkendali tegangan.

a. Osilator referensi

Osilator referensi akan menghasilkan sinyal dengan level amplitudo

keluaran yang sesuai dengan kebutuhan pembanding fasa, dan menjadi

referensi bagi detector fasa. Karena frekuensi ini harus tepat, maka digunakan

kristal karena tingkat kestabilan cukup tinggi. Osilator ini dibangun dengan

osilator kristal dan pembagi osilator, yaitu dengan IC 4060 yang berfungsi

membagi kristal menjadi frekuensi yang diinginkan. Komponen IC 4060

dapat dilihat pada gambar 2.6

U1

74HC4060

11

12

7546141315123910

PI

RST

Q4Q5Q6Q7Q8Q9

Q10Q12Q13Q14POPO

Gambar 2.6 Blok diagram IC 74HC4046

12

b. Osilator terkendali tegangan

Untuk mendapat mengubah frekuensi output osilator, maka parameter

pembangkit osilasi (R,L,C) harus diubah salah satunya. Perubahan nilai dari

R, L atau C dapat direalisasikan dengan menggunakan berbagai metode.

Pengubahan nilai R (ohm) L (henry), dilakukan secara mekanis, dan hal ini

membuat parametersistem lebih rentan terhadap gangguan.

Maka digunakan perubahan nilai kapasitans (C), karena pengubahan

nilai kapasitansi dapat dilakukan dengan jalan pengubahan nilai tegangan dari

suatu komponen semikonduktor, dalam hal ini adalah dioda varactor. Dioda

terpesang pada rangkaian dan berfungsi sebagai kapasitor variable. Dengan

pemberian tegangan DC secara bias mundur, maka nilai kapasitansi dioda

dikendalikan, yang berarti pengendalian terhadap frekuensi keluaran osilator.

Osilator terkemudi tegangan yang biasa dijumpai adalah jenis osilator coll-

pits, karena bekerja pada frekuensi menengah untuk frekuensi tinggi.

Penguatan pada VCO dapat dihitung dengan rumusan dibawah ini

Kv = )9.0(9.0

22−− CC

L

Vf π ……………………………………..(2.14)

4. Operasi Phase Loced Loop

Kedua input dari detector fasa adalah sinusoidal dangan frekuensi FRω dan

fasa yang sama maka V3 sama dengan nol yang merupakan input osilator terkendali

tegangan agar output tetap pada frekuensi iFR ωω = dan loop akan terjaga. Jika tiba-

tiba Vi naik dan ( 0 )θθθ −=Δ i maka keluaran dari Vi akan ditapis dan dikuatkan

13

sehingga V3 akan naik dan 0ω naik sampai iωω =0 yang terjadi adalah semua vektor

beroperasi pada kecepatan yang sama dan loop baru terjadi. Kejadian ini akan tejadi

saat iω turun. Saat terjadi kondisi terkunci (loocked), V3 akan proporsional dengan

frekuensi VCO jika 0ωω =i maka

V3 = 0k

FRi ωω −…………………………………..(2.15)

D. Transistor sebagai penguat awal

Transistor adalah komponen aktif dengan arus, tegangan atau daya yang

dikendalikan oleh arus input. Transistor juga merupakan komponen tiga terminal

yang terdiri atas basis(B), kolektor(K), emiter(E).

C1

I(IC+IB)

VCC

R2

OutputIC

Q1

3

2

1

Input

C2R1

IB

Gambar 2.7 Ragam CE dengan prategangan Umpan-balik kolektor

Konsep rangkaian prategangan umpan balik kolektor merupakan rangkaian

modifikasi dari penguat ragam CE yang digunakan untuk memberikan kemampuan

stabilisasi yang lebih baik rangkaian ini ditunjukkan dpada gambar 2.5. Dalam

rangkaian ini hambatan basis disambungkan dengan kolektor dan bukan dengan catu

daya.

14

Bila suhu naik, β dc dalam transistor juga naik. Hal ini mengakibatkan

kenaikan arus kolektor (Ic). Sesaat setelah Ic naik, tegangan kolektor emitor (Vce)

turun.

Dengan melihat aliran arus dari Vcc, R2, R1,Vbe, Ground, maka:

V= IxR…………………………………………...………(2.16)

VCC-VBE= (I x Rc) = (IB x RB)…………………………...(2.17)

I = Ic+IB.............................................................................(2.18)

IC = β dc × IB.....................................................................(2.19)

Vcc-VBE = [ IB +( β dc × IB)]×Rc + (IB× RB)…………(2.20)

IB = RBRcdcRc

VBEVcc+×+

−)(β

………………………………(2.21)

VCE = VCC-RC× (IB + IC)………………………………(2.22)

Dengan VCE = Tegangan pada kaki kolektor-emitor,VBE = Tegangan pada

kaki basis-emitor,Vcc = Tegangan catu, IB = Arus basis, IC = Arus kolektor,

Rc = Hambatan kolektor,RB = Hambatan kaki basis

E. Transistor Sebagai Penguat Daya

Gambar 2.8 memperlihatkan rangkaian penguat daya CE. “pembagi

tegangan” berasal dari pembagi tegangan yang dibentuk oleh R3 dan R4.

15

IB

L1

Input

C4R4

R3

Q2

3

2

1

C3

IC

Output

Gambar 2.8Penguat daya CE dengan prategangan pembagi tegangan

Dengan analisis thevenin, maka diperoleh dua besaran yaitu hambatan

thevenin (RTH) dan teganga thevenin (VTH).[7]

1. Untuk mencari RTH, maka rangkaian gambar 2.8 diubah menjadi

Gambar 2.9

RTH

R1

R2

Gambar 2.9 Rangkaian untuk mencari RTH [7]

Dari Gambar 2.29. didapat persamaan

RTH = R1 paralel R2…………………………………………..(2.24)

THR1 =

21

11RR

+ …………………………...………………….(2.25)

21

211RRRR

RTH ×+

= ………………………………………………(2.26)

RTH = 21

21

RRRR

+× ………………………………………………(2.27)

Dengan RTH = Hambatan Thevenin

16

2. Untuk mencari VTH, maka rangkaian Gambar 2.9 diubah menjadi Gambar

2.10

VTH

R1

VCC

R2

Gambar 2.10 Rangkaian untuk mencari VTH [7]

Dari Gambar 2.10. didapat persamaan

VTH = CCVRR

R×⎟⎟⎠

⎞⎜⎜⎝

⎛+ 21

2 ………………………………………(2.28)

Dengan VTH = Tegangan Thevenin

Setelah diperoleh besaran RTH dan VTH rangkaian Gambar 2.8 diubah

menjadi gambar 2.10, untuk mencari IBQ dan ICQ yang digunakan untuk

menggambarkan garis beban ac dari transistor Gambar 2.8.

Dari Gambar 2.10 didapat persamaan

IBQ = TH

BQTH

RVV −

..................................................................(2.29)

ICQ = BQdc I×β ……………………………………………(2.30)

IC(Sat) = ICQ + e

CEQ

rV

…………………………………..…...(2.31)

VCE(cutoff) = VCEQ + (ICQ × re)…………………………….(2.32)

17

Keterangan: IBQ = Arus basis dc, ICQ = Arus kolektor dc, VBE =

Tegangan basis-emiter,(Si = 0.7V danGe= 0.3V), VCEQ = Tegangan basis

emitter dc, VCE(cutoff) = Tegangan putus ac, IC(sat) = Arus jenuh ac, rc =

Hambatan ac, rc = RP // Rl,

C1

L

C2

Q

3

2

1

RTH

Input

Output

IB

VTH

IC

Rangkaian Pengganti Thevenin

VCC

(a)

L(rc)

Q 3

2

1

Vth

12

RTH

IB

IC

+Vce-

(b)

Gambar 2.11 Rangkaian penguat daya CE dengan pembagi tegangan (a).

Rangkaian ekivalen dc (b). Rangkaian ekivalen ac

RP = QL LX× .....................................................................(2.33)

XL = 2 fLπ ………………………………………………..(2.34)

18

Keterangan: RP = Hambatan kumparan parallel, RL = Hambatan

beben, besarnya 500Ω , XL = Reaktansi induktif, QL= Faktor kualitas

kumparan, minimal besarnya 50Ω

Dari nilai-nilai IBQ, ICQ, VCEQ, IC(sat) dan VCE(cutoff), dapat digambarkan

garis beban ac transistor yang ditunjukkan pada Gambar 2.12.

IC (mA) Titik jenuh

ICEQ+ C

CEQ

rV

garis beben ac IB2 Garis beben dc

IB1

IBQ Titik kerja (Q)

ICQ IB3

IB2 Titik sumbat

VCE (V) VCEQ VCEQ + (ICQ × re )

Gambar 2.12Garis beban dc dan ac dari transistor pada rangkaian penguat

daya CE dengan pembagi tegangan

Garis beban transistor merupakan garis yang menyatakan semua titik operasi

dc dari suatu transistor. Pertemuan garis beban dc dengan garis arus disebut dengan

titik jenuh (saturasion point) dan Pertemuan garis beban dc dengan garis tegangan

merupakan titik sumbat (Cutoff point). Titik kerja tensistor (Q) terletak pada suatu

tempat sepanjang garis beban dc.[11]

Garis beban ac suatu transistor merupakan garis yang menyatakan titik

operasi ac dari suatu transistor. Pada suatu saat selama periode ac, titik operasi

19

“sesaat” terletak pada suatu tempat sepanjang garis beban ac sedangkan titik operasi

yang “tepat” .

F. Timer 555

Multivibrator adalah rangkaian pembangkit pulsa yang menghasilkan

keluaran gelombang segi empat [12]. Multivibrator diklasifikasikan menjadi

multivibrator astabil, bistabil, atau monostabil. Suatu multivibrator astabil juga

disebut dengan multivibrator bergerak bebas. Multivibrator astabil menghasilkan

aliran pulsa yang kontinyu.

IC pewaktu 555 multiguna, dapat digunakan sebagai multivibrator astabil,

bistabil, atau monostabil. Skema IC ditunjukkan pada Gambar 2.13.

Gambar 2. 13 IC LM555 [12].

Frekuensi keluaran multivibrator dapat ditingkatkan dengan menurunkan nilai

dari resistor dan kapasitor, sesuai dengan rumus umumnya yaitu :

CRBRATf

)2(44,11

+== ...............................................................( 2.35)

20

Gambar 2.14 IC LM555 sebagai multivibrator astabil [12].

Perancangan menggunakan rangkaian yang ditunjukkan pada Gambar 2.14.

Pengisian kapasitor dilakukan melalui RA dan RB, sedangkan untuk pengosongan

dapat dilakukan melalui RB, dengan duty cycle :

RBRA

RBD2+

= .............................................................................(2.36)

Dalam mode operasi ini kapasitor mengisi dan mengosongkan dengan tegangan

antara 1/3 Vcc dan 2/3 Vcc, dan frekuensi tidak tergantung pada supply tegangannya.

Bentuk gelombang keluaran ditunjukkan pada Gambar 2.15.

Gambar 2.15 Bentuk gelombang keluaran [12].

21

G. Frequency hopping

Frequency hopping atau lompatan frekuensi adalah perubahan frekuensi

sinyal pembawa secara periodis yang diatur oleh algoritma tertentu [2]. Frekuensi ini

akan membawa informasi selama periode tertentu dan berpindah ke frekuensi yang

lain, begitu seterusnya, seperti diperlihatkan pada Gambar 2.16.

Gambar 2.16 Teknik frequency hopping [2].

Anak panah pada Gambar 2.16 menunjukkan urutan lompatan (hop)

frekuensi, dari frekuensi , demikian

berulang-ulang. Perpindahan frekuensi terjadi beberapa ratus sampai beberapa ribu

kali dalam satu detik. Stasiun penerima juga harus melakukan perpindahan frekuensi

dengan lompatan yang sama supaya informasi yang dikirimkan dapat diterima

kembali.[13]

6452731 fffffff →→→→→→

Frequency hopping merupakan salah satu dari teknik spektrum tersebar

(spread-spectrum) dimana bandwidth yang digunakan jauh lebih lebar dari

bandwidth minimum yang diperlukan untuk mengirimkan informasi yang sama jika

menggunakan pembawa tunggal [3].

22

Sistem komunikasi yang menggunakan teknik spread spectrum akan

mempunyai kelebihan dalam aplikasinya, meliputi kemampuan antijam, penekanan

interferensi dari luar, mampu melawan multipath fading, Low probability of intercept

(LPI), komunikasi yang aman, dan perbaikan efisiensi spektral.

Lompatan dari satu frekuensi ke frekuensi yang lain diatur secara berurutan

atau secara acak dengan menggunakan sandi pseudorandom. Sandi pseudorandom

adalah sandi acak yang mempunyai deretan sandi yang akan terulang secara periodis

dalam perioda yang cukup lama. Dengan mengacak pola lompatan, sinyal penggangu

(interfering signal) diharapkan dapat dihindari. Jika interefensi muncul dan

menggangu salah satu kanal berfrekuensi, misal , maka sinyal pembawa akan

selalu mengalami gangguan tetapi hanya saat berada pada frekuensi . Hal ini

diperlihatkan pada Gambar 2.17.

2f

2f

Gambar 2.17 Interferensi pada transmisi Frequency Hopping [16].

23

BAB III

PERANCANGAN PERANGKAT KERAS

A. Blok Diagram

Gambar 3.1 merupakan diagram blok penerima AM dengan frequency

hopping

PD LPF VCO BOOSTER DRIVER

PT

ORF

MOD

Gambar 3.1 Diagram Blok Pemancar AM

Keterangan:

ORF : Osilator Acuan (Osilator Refferensi), PD : Detektor Fasa (Phase

Detector), LPF : Filter Pelewat Bawah. (Low Phass Filter), PT : Pembagi

Terprogram

Skema terdiri dari osilator dengan PLL ( osilator referensi, detektor fasa,

low pass filter, osilator terkendali tegangan), driver, dan booster.

24

B. Osilator dengan PLL

Penentuan spesifikasi sistem perlu dilakukan bertujuan untuk memberikan

batasan dalam menentukan ukuran dan kemampuan alat yang akan dibuat.

Pembangkit frekuensi ini diharapkan mempunyai spesifikasi sebagai berikut:

Frekuensi keluaran : 1000 Khz dan 1050 Khz

Frekuensi langkah (step) : 1 Khz

Waktu : 1 ms

Overshoot : < 20%

Frekuensi keluaran merupakan frekuensi keluaran yang diharapkan dari

perancangan. Frequency steps adalah perubahan frekuensi tiap clock.

1. Rangkaian osilator referensi

Osilator referensi akan menentukan besar langkah frekuensi (frequency

step) yang terjadi, pada tiap perubahan digit bilangan masukan, dan pada resolusi

frekuensi keluaran. Untuk kestabilan, dipilih osilator kristal. Osilator

menggunakan kristal 10.240 Mhz, yang digunakan sebagai input dari IC4060.

Keluaran dari IC ini adalah 10Khz pada kaki IC nomor 15, kemudian keluaran IC

4060 akan dibagi dengan 1000 dengan pembagi sepuluh IC 74LS90 agar

menghasilkan frekuensi 1 Khz yang akan menjadi frekuensi referensi.

25

Gambar 3.2 Rangkaian pembangkit frekuensi 1Khz

2. Rangkaian VCO, Filter dan Detektor Fasa

Perancangan VCO dan detektor fasa ini menggunakan IC 74HC4046.

Pada kondisi mengunci detektor fasa adalah saat tidak ada beda fasa atau

perbedaan fasanya nol

Blok diagram IC 74HC4046 ditunjukkan pada Gambar 3.3. VCO pada IC

74HC4046 menggunakan komponen eksternal resistor dan kapasitor yang

menentukan frekuensi kerja osilator.

U5

74HC4046

34

14

6

75

1112

12

13

9

1015

CINVCOUT

SIN

CX

CXINHR1R2

PPP1

P2

VCOIN

DEMOZEN

Gambar 3.3 Blok diagram IC 74HC4046 [14]

26

Gambar 3.4 merupakan rangkaian VCO dan detektor fasa dengan IC

CD4046 dan rangkaian eksternal. Tegangan yang akan diberikan pada masukan

VCO akan mengendalikan frekuensi yang dibangkitkan. Frequency range

ditentukan oleh trimmer kapasitor yang terhubung ke pin 6 dan pin 7. Pada pin 13

dan pin 9 terdapat resistor (R3) dan kapasitor (C2) yang berfungsi sebagai filter.

Jika menggunakan tegangan Vcc 5 volt, maka nilai C2 100pF dan R2 5kΩ . ≥ ≥

U2

74HC4046

34

14

6

75

1112

12

13

9

1015

CINVCOUT

SIN

CX

CXINHR1R2

PPP1

P2

VCOIN

DEMOZEN

R410K

OUTPUT

R329K

C4300pF

INPUT dr TC1922P

C3470nF

INPUT DARI 74LS90

R510K

Gambar 3.4 Rangkaian Fasa detector dan VCO

3. Rangkaian Pembagi Terprogram

Rangkaian pembagi akan bergantung pada pembagian yang akan

digunakan. Sistem ini menggunakan pembagian langsung, yaitu 4 digit bilangan

bagi yang terdiri dari N1, N2, N3, dan N4. Masing-masing adalah pembagi

ribuan, ratusan, puluhan, dan satuan. Pembagi terprogram (programmable divider)

menggunakan IC TC9122P.

Logika pembagi ini adalah logika TTLdengan tegangan Vdd = 5 volt. IC

ini akan membagi sinyal masukan, sesuai dengan bilangan decimal yang

diumpankan pada masukan IC.

27

Input berasal dari output VCO dan output diumpankan ke input rangkaian

detektor fasa sebagai input yang akan dibandingkan dengan VCO. Pada input

(pin-2) TC9122P, diumpankan gelombang dengan Vpp max = 5 V. Arus yang

dibutuhkan IC sekitar 5 mA .

IC TC9122P ditunjukkan pada Gambar 3.5.

Gambar 3.5 IC TC9122P [15].

Diagram blok IC TC9122P ditunjukkan pada Gambar 3.6.

Gambar 3.6 Diagram blok IC TC9122P [15].

Pembagian bilangan ditunjukkan pada Tabel 3.1. dengan frekuensi yang

digunakan = 1kHz dan = 1050Hz. Frekuensi yang diharapkan dari output

pembagi terprogram adalah 1kHz saat kondisi T

1f 2f

ON. Sedangkan frekuensi yang

dihasilkan saat kondisi TOFF adalah 1050Hz.

28

Frekuensi Ribuan (N1) Ratusan (N2) Puluhan (N3) Satuan (N4)

1kHz 01 0000 0000 0000

1050Hz 00 0000 0101 0000

Tabel 3.1. Pembagian frekuensi dalam bentuk BCD [15].

Dimana TON = Saat timer “1”, TOFF = Saat timer “0”

4. Rangkaian timer 555

Timer dirancang untuk menghasilkan kondisi “1” dan kondisi “0” selama

0,5 detik ( 5,021 == TT detik). Dengan C1 = 1uF dan RA = 10 kΩ, nilai RB dapat

dihitung dengan menggunakan persamaan (2.35)

)2(4,111

121 BA RRCTTTf

+=

+==

)21010(101

4,15,05,0

136

BRxx +=

+ −

BRxx 63 1021010

4,11 −− +=

Ω== − kx

RB 69510239,1

6

Nilai Duty cycle ( D ) dapat dihitung dengan persamaan 2.36

%1002

xRR

RRDBA

BA

++

=

%3,50%100)10695(21010

10695101033

33

=++

= xxx

xxD

29

Rangkaian timer ditunjukkan pada Gambar 3.7.

output

v cc 5v olt

R271Meg1

32

C210.1uF

C19

1uF

R2510K

U13LM555/TO

2

5

3

7

6

4 81

TR

CV

Q

DIS

THR

R

VC

CG

ND

TIMER

Gambar 3.7 Rangakaian Timer. [12]

C. Rangkaian Penggerak (Driver)

Rangkaian penggerak yang digunakan adalah jenis penguat ragam CE dengan

prategangan pembagi tegangan. Rangkaian penggerak ditunjukkan pada Gambar

3.8.

R81k

R627k Output

C61.8nF

InputQ12n39041

23

R710k

C7

1.6nF

VCC 12v

Gambar 3.8 Rangkaian Penggerak [11]

30

Penguat penggerak memiliki tegangan yang dicatu oleh Vcc = 12V untuk

memberikan bias balik pada transistor kaki kolektor, penguat dirancang dengan

transistor 2N3904 (Q), resistor (R), inductor (L) dan kapasitor (C). Q yang

berfungsi sebagai komponen aktif untuk penguatan sinyal, R6 = (27 K ), R7 =

(10 K ) dan R8 = (1 KΩ ) berfungsi sebagai prategangan kaki basis. C6 = (1.8

nF) yang berfungsi sebagai kapasitor by pass dan C7 (1.6nF) yang berfungsi

sebagai kapasitor coupling dan L = 1

Ω

Ω

Hμ berfungsi sebagai RFC (Radio

Frequency Choke).

D. Rangkaian Booster

Rangkaian booster yang digunakan adalah adalah jenis penguat FET

dengan prategangan pembagi tegangan. Rangkaian driver ditunjukkan pada

Gambar 3.9.

output

input

Q1IRF510

3

2

1

VCC

C9470uF

R91.6k

C8

113pF

L1 2.5mH,2A

R111k

R1010k

Gambar 3.9 Rangkaian Booster [11]

Penguat penggerak memiliki tegangan yang dicatu oleh Vcc = 12V untuk

memberikan bias balik pada transistor kaki drain, penguat ini dibangun dengan

transistor IRF510 (Q), resistor (R), inductor (L) dan kapasitor (C). Q yang

31

berfungsi sebagai komponen aktif untuk penguatan sinyal, R9 = (1.6 KΩ ), R10 =

(10 KΩ ) dan R11 = (1 KΩ ) berfungsi sebagai prategangan kaki basis. C8 = (113

pF) yang berfungsi sebagai kapasitor by pass dan C9 (470pF) yang berfungsi

sebagai kapasitor coupling dan L = 2.5mH, 2 A berfungsi sebagai RFC (Radio

Frequency Choke).

E. Modulator AM

Modulator adalah sebuah penguat suara yang berguna untukmenghasilkan

sinyal informasi yang akan dimodulasi pada sinyal frekuensi radio.

Dalam perancangan ini Rangkaian modulator dibangun oleh sebuah penguat suara

yang memiliki daya keluaran sebesar 1W. Pada keluaran penguat ini disambung

dengan Output Transformator (OT 426). Rangkaian modulator ditunjukkan pada

Gambar 3.10.

L2INDUCTOR AUDIO

8

6

T1

OT 426

1 5

6

4 80

MODULATOR PENGUAT

SUARA

Vcc 12V

Gambar 3.10 Rangkaian modulator

32

BAB IV

HASIL DAN PEMBAHASAN

A. Hasil Perancangan

Hasil perancangan terdiri dari satu bagian alat pemancar yang terlihat pada

Gambar 4.1.

Gambar 4.1. Blok pemancar hopping.

B. Pengujian dan Pengukuran Alat

1. Pengujian Transmisi pemancar

Pengujian dilakukan dengan model sistem yang ditunjukkan pada Gambar 4.2

33

•

PEMANCAR AM DENGAN

HOPPING

PESAWAT PENERIMA

AM 1000KHZ

PESAWAT PENERIMA

AM 1050KHZ

A

Gambar 4.2. Model sistem untuk pengujian transmisi pemancar.

Pemancar mengirimkan sinyal informasi dengan dua frekuensi carrier 1000

KHz dan 1050 KHz. Sinyal yang dikirim akan diterima oleh dua pesawat penerima

AM yang masing-masing tertala 1000 KHz dan 1050 KHz

Gambar 4.3 dan Gambar 4.4 menunjukkan spektrum frekuensi pemancar yang

diambil secara bergantian di titik a pada Gambar 4.2. Pada Gambar 4.3 dan Gambar

4.4 memperlihatkan bahwa pemancar dengan frekuensi 1000 KHz dan 1050 KHz

memiliki spektrum frekuensi yang baik. Hal ini dapat dilihat dari frekuensi yang

stabil di 1000 KHz dan 1050KHz.

34

Gambar 4.3. Spektrum frekuensi dengan frekuensi carrier 1000 KHz.

Gambar 4. 4. Spektrum frekuensi dengan frekuensi carrier 1050 KHz.

Pemancar juga diuji untuk membuktikan bahwa pemancar bekerja dengan

modulasi amplitudo. Dengan sinyal informasi sinusoida berfrekuensi 4 KHz yang

terlihat pada Gambar 4.5 didapat bentuk gelombang seperti yang ditunjukkan pada

35

Gambar 4.6 dan Gambar 4.7, ini terlihat bahwa pemancar bekerja dengan modulasi

amplitudo.

Gambar 4.5. Sinyal informasi 4 kHz yang dikirim.

Gambar 4.6. Modulasi amplitudo dengan gelombang carrier 1000 KHz.

36

Gambar 4.7 Modulasi amplitudo dengan gelombang carrier 1050 KHz.

Gambar 4.8. Spektrum frekuensi audio pada penerima AM dengan frekuensi carrier 1000 KHz.

Gambar 4.9. Spektrum frekuensi audio pada penerima AM dengan frekuensi carrier 1050 KHz.

37

Pengamatan juga dilakukan dengan mendengarkan kualitas bunyi tone pada

speaker penerima AM. Semakin tinggi frekuensi sinyal informasi, semakin tinggi

pula bunyi tone yang terdengar demikian pula sebaliknya. Gambar 4.8 dan Gambar

4.9 menunjukkan sektrum frekuensi pada penerima yang memiliki frekuensi

fundamental yang sama dengan frekuensi yang dikirim. Data pendukung dengan

variasi frekuensi masukan dengan amplitudo tetap terdapat pada bagian lampiran.

2. Pengujian Saat Hopping

Pengujian dilakukan dengan sistem yang ditunjukkan pada Gambar 4.10.

Sinyal output blok pemancar diukur dengan menggunakan frequency counter dari 50

- 300 detik, dengan nilai kenaikan 50 detik. Data yang didapat ketika proses hopping

berlangsung terlihat pada Tabel 4.1.

frequency counter

PEMANCAR AM DENGAN

HOPPING

Gambar 4.10 Pengujian kestabilan pemancar saat hopping.

Dari Tabel 4.1 dapat dihitung nilai rata-rata dan prosentase rata-rata error

dari dua frekuensi carrier. Nilai rata-rata dihitung dengan persamaan

Nfrekuensi

X ∑= (4.1)

38

Dengan X adalah nilai rata-rata, ∑ frekuensi adalah penjumlahan seluruh nilai

frekuensi yang diuji dan N adalah banyaknya data yang diuji. % adalah prosentase

rata-rata error, dapat dihitung dengan persamaan.

%100% xcanganNilaiPeran

XcanganNilaiPeran −= (4.2)

Tabel 4.1 Data hasil pemancar saat hopping.

Detik ke-

Frekuensi Carrier 1

(KHz)

Frekuensi Carrier 2

(KHz)

50 1000,0 1050,0

100 1000,2 1050,6

150 1000,4 1050,2

200 1000,0 1050,1

250 1000,0 1050,3

300 1000,1 1050,8

Nilai rata-rata 1000,1 1050,3

Presen

error(%)

0,01 0,28

Dari Tabel 4.1 terlihat bahwa persen rata-rata error (%) frekuensi carrier

kecil yaitu 0,01 % untuk frekuensi carrier 1000 KHz dan 0,028 % untuk frekuensi

39

carrier 1050 KHz. Dari prosentase error itu dapat dikatakan bahwa pemancar

memiliki frekuensi carrier yang stabil saat hopping berlangsung.

3. Pengujian Jarak Pancar

Pengujian dilakukan untuk mengetahui jarak pancar maksimum sinyal

pemancar AM. Pengukuran jarak dilakukan dengan cara meletakkan pemancar pada

satu titik dalam ruangan dan penerima AM berpindah-pindah.

Tabel 4.2 Data hasil jarak pancar

Jarak

(meter)

Tone pada penerima AM 1 (1000 KHz)

Audio Level (dB)

Tone pada penerima AM 2 (1050 KHz)

Audio Level (dB)

1 Baik -3 Baik -3 2 Baik -3 Baik -3 3 Baik -3 Baik -3 4 Baik -3 Baik -3 5 Baik -3 Baik -3

6 Kurang Baik -20 Baik -3

7 Baik -3 Baik -3

8 Baik -3 Kurang Baik -20

9 Kurang Baik -20 Baik -3

10 Baik -3 Kurang Baik -20

11 Kurang Baik -20 Kurang Baik -20

Keterangan: “Baik” adalah tone pada penerima dapat terdengar dengan jelas.

“Kurang Baik” adalah tone yang diterima terdengar putus-putus.

40

Dari Tabel 4.2 terlihat bahwa pemancar bekerja dengan cukup baik pada

jarak maksimal 5 meter. Dari pengujian proses transmisi pemancar, kestabilan jarak

pancar alat dapat disimpulkan bahwa pemancar AM frequency hopping yang telah

dibuat dapat bekerja dengan cukup baik.

C. Pengujian Setiap Blok

1. Frekuensi Pembagi 10 KHz

Pengujian ini bertujuan untuk mendapatkan data mengenai tingkat kestabilan

frekuensi pembagi. Gambar 4.11 menunjukkan gelombang output rangkaian

pembangkit frekuensi referensi 10 KHz dari IC 4060.

Gambar 4.11. Gelombang output IC 4060 frekuensi pembagi 10 KHz.

T1 T2

V1

V2

41

Berdasarkan Gambar 4.11 dapat dihitung nilai frekuensi yang terukur dengan

menggunakan persamaan

21

1TT

f−

= (4.3)

Nilai pembangkit frekuensi pembagi adalah

KHzf 94.9104.99

1)10100(106.0

1666 =

×=

×−−×−= −−−

Persen error frekuensi pembagi adalah

% = %06,0%10010

94.910=

− x .

Dilihat dari persen error frekuensi pembagi yang kecil yaitu 0.06%

memperlihatkan bahwa rangkaian pembangkit frekuensi pembagi yang dibuat telah

bekerja sesuai dengan perancangan yaitu 10 KHz.

2. Frekuensi referensi 1KHz

Pengujian ini bertujuan untuk mendapatkan data mengenai frekuensi referensi.

Gambar 4.12 menunjukkan gelombang output rangkaian pembangkit frekuensi

referensi 1 KHz dari IC 74LS90.

42

T1 T2

Gambar 4.10. Gelombang output IC 4060 frekuensi referensi 1 KHz


menggunakan persamaan (4.1), maka didapat nilai frekuensi referensi sebesar:

V1

V2

KHzf 9936.0109936.0

1)101(104.6

1336 =

×=

×−−×−= −−−

Persen error frekuensi referensi adalah

% = %0064,0%10019936.01

=− x .

Dilihat dari persen error frekuensi referensi yang kecil yaitu 0.06%

memperlihatkan bahwa rangkaian pembangkit frekuensi pembagi yang dibuat telah

bekerja sesuai dengan perancangan yaitu 1 KHz.

43

3. Voltage Controlled Oscillator.

Gambar 4.13 dan Gambar 4.14 menunjukkan kinerja dari osilator yang

digunakan sebagai penghasil gelombang carrier tanpa sinyal informasi.

T2 T1

V1

V2

Gambar 4.13. Sinyal output rangkaian osilator 1000 KHz.


menggunakan persamaan (4.1), dan didapat nilai frekuensi referensi sebesar:

KHzf 10001011

)103(1041

666 =×

=×−−×−

= −−−

Dari hasil perhitungan frekuensi yang terukur memperlihatkan bahwa

rangkaian pembangkit frekuensi referensi yang telah dibuat telah bekerja sesuai

dengan perancangan 1KHz.

44

T1 T2

V1

V2

Gambar 4.14. Sinyal output rangkaian osilator 1050 KHz.


menggunakan persamaan (4.1), maka didapat nilai frekuensi referensi sebesar.

KHzf 10001011

)108.2(108.31

666 =×

=×−−×−

= −−−


rangkaian pembangkit frekuensi referensi yang telah dibuat telah bekerja sesuai

dengan perancangan yaitu 1050KHz.

4. Pembagi Terprogram

Pada blok pembagi terprogram terjadi proses pembagian frekuensi output

rangkaian Voltage Controlled Oscillator. Gambar 4.15 menunjukkan gelombang

output pembagi terprogram TC 9122P.

45

T1 T1

V1

V2

Gambar 4.15. Gelombang output pembagi terprogram.

Frekuensi pembagi terprogram yang terukur pada Gambar 4.15 dihitung

dengan menggunakan persamaan 4.1 adalah

KHzf 11011

)103(1041

333 =×

=×−−×−

= −−−


rangkaian pembagi frekuensi terprogram yang telah dibuat telah bekerja sesuai

dengan perancangan yaitu 1KHz.

5. Phase detector dan Low Pass Filter

LPF dirancang menjadi satu kesatuan dengan phase detector yang berfungsi

untuk menghilangkan komponen frekuensi tinggi. Dari hasil try and error, rangkaian

46

VCO yang dibuat membutuhkan tegangan 1.5 volt untuk melewatkan frekuensi 1000

KHz dan 3,15 Volt untuk melewatkan frekuensi 1050 KHz.

Phase detector menghasilkan tegangan koreksi karena adanya perbedaan fasa

antara frekuensi referensi 1 KHz dan frekuensi output dari pembagi terprogram. Dari

hasil pengukuran alat yang telah dibuat, phase detector menghasilkan tegangan 1 volt

saat frekuensi 1000 KHz dan 2.8 volt saat frekuensi 1050 KHz kemudian menjadi

input LPF. Tegangan output LPF 0.8 volt saat frekuensi 1000 KHz dan 3 volt saat

frekuensi 1000 KHz.

Persen error tegangan LPF saat frekuensi 1000 KHz adalah

% = %46,0%1005,1

8,05,1=

− x .

Persen error tegangan LPF saat frekuensi 1050 KHz adalah

% = %047.0%10015,3

315,3=

− x

Dilihat dari persen error tegangan yang kecil yaitu 0,06 % dan 0,4 %,

sehingga tidak berpengaruh pada kinerja VCO.

47

6. Timer

Gambar 4.16 menunjukkan hasil pengukuran rangkaian timer.

T2T1

V1

V2

Gambar 4.16. (a) Sinyal output IC LM 555.

T1 T2

V1

V2

Gambar 4.16.(b) Sinyal output IC LM 555 TON.

48

Pada Gambar 4.16.(a) terlihat bahwa frekuensi pengendali 1000 KHz sama

dengan frekuensi pengendali 1050 KHz yaitu

Hzf 996,0108,1003

1)10163(108,840

1333 =

×=

×−×−= −−−

sehingga periode sinyal pengendali adalah

ssf

T 1004,1996.011

≅===

Periode ON sinyal pengendali pada Gambar 4.16. (b) adalah

Hzf 83,1105,543

1)103,297(108,840

1333 =

×=

×−−×−= −−−

sehingga periode sinyal pengendali adalah

sf

T 54,083,111

===

% = %008,0%1005,0

54,05,0=

− x

TON

TOFF

Dilihat dari persen error frekuensi referensi yang kecil yaitu 0.008%

memperlihatkan bahwa rangkaian timer yang dibuat tidak sesui dengan perancangan

yaitu 0,5s. Karena timer tidak sesuai maka perlu adanya sinkronisasi timer antara

pemancar dan penerima agar proses hopping tidak terganggu dan data dapat diterima

dengan baik.

49

7. Analisa Phase Lokced Loop

Dari data yang diperoleh, cukup memberi gambaran bagaimana sistem PLL

ini bekerja. PLL berfungsi untuk membangkitkan frekuensi carrier 1000 KHz dan

1050 KHz. Tabel 4.3. terlihat bahwa sistem Phase Lokced Loop bekerja dengan baik,

dilihat dari error yang kecil

Tabel 4.3. Data hasil Phase Lokced Loop

Komponen Phase

Lokced Loop

Perancangan

Hasil pengamatan

Error ( %)

Frekuensi Pembagi 10 KHz 10KHz 9,94 KHz 0,06

Frekuensi Referensi 1 KHz 1KHz 0,9936 KHz 0,0036

VoltageControlledOscillator. 1000 KHz

1050 KHz

1000 KHz

1050 KHz

0

0

Pembagi Terprogram 1 KHz 1 KHz 0

Phase detector dan Low Pass

Filter

1,5 v

3,15 v

0,8 v

3 v

0,46

0,047 Timer 0,5 s 0,54 0,008

8. Driver dan Booster

Gambar 4.17.a. dan Gambar 4.1.b. menunjukkan gelombang dan spektrum

frekuensi hasil pengukuran output rangkaian driver. Gambar 4.17.a. dan Gambar

4.1.b. menunjukkan gelombang dan spektrum frekuensi output rangkaian booster.

50

Output rangkaian driver dan booster diambil dengan sinyal informasi 4 KHz serta

frekuensi carrier 1000 KHz. Nilai tegangan output dapat dihitung dengan

persamaan, nilai ini akan digunakan untuk mengetahui basar penguatan.

pVpVacVout 21)( += (4.4)

T1 T2

V1

V2

Gambar 4.17.a. Gelombang output driver frekuensi carrier 1000 KHz

Gambar 4.17.b. Spektrum frekuensi driver dengan frekuensi carrier 1000 KHz

51

Tegangan output rangkaian driver saat frekuensi carrier 1000 KHz

pmVpxxacdriverVout −=+= −− 6,5108,1108,3)( 33

T2 T1

V2

V1

Gambar 4.18.a. Gelombang output booster frekuensi carrier 1000KHz

Gambar 4.18.b. Spektrum frekuensi booster dengan frekuensi carrier 1000KHz

Tegangan output rangkaian booster saat frekuensi carrier 1000 KHz

pmVpxxacboosterVout −=+= −− 1,28108,5103,22)( 33

52

Sehingga nilai penguatan booster saat frekuensi carrier 1000 KHz adalah

01,56,51,28

=−−

==pmVppmVp

driverVboosterVA

out

outV

Gambar 4.19.a. dan Gambar 4.19.b. menunjukkan gelombang dan spektrum

frekuensi hasil pengukuran tegangan output rangkaian driver. Gambar 4.20.a. dan

Gambar 4.20.b. menunjukkan gelombang dan spektrum frekuensi booster dengan

frekuensi carrier 1050 KHz.

T2 T1

V1

V2

Gambar 4.19.a. Gelombang output rangkaian driver frekuensi carrier 1050 KHz

53

Gambar 4.19.b. Spektrum frekuensi driver dengan frekuensi carrier 1050 KHz

Dari Gambar 4.19.a. didapat nilai tegangan output dengan menggunakan

persamaan 4.4.

Tegangan output rangkaian driver saat frekuensi carrier 1050 KHz adalah

pmVpxxacdriverVout −=+= −− 7,5107,1104)( 33

T1 T1

V2

V1

Gambar 4.20.a. Gelombang output rangkaian booster frekuensi carrier 1050 KHz

54

Gambar 4.20.b. Spektrum frekuensi booster dengan frekuensi carrier 1050 KHz

Tegangan output rangkaian booster saat frekuensi carrier 1050 KHz adalah

pmVpxxacboosterVout −=+= −− 1,70104,14107,55)( 33

Sehingga nilai penguatan booster saat frekuensi carrier 1050 KHz adalah

5,126,51,70

=−−

==pmVppmVp

driverVboosterVA

out

outV

Daya tidak dapat terlihat dikarenakan ketidakmampuan range alat ukur.

55

BAB V

KESIMPULAN DAN SARAN

A. Kesimpulan

Berdasarkan hasil pengamatan dan pembahasan pada rangkaian Pemancar AM

frequency hopping, maka dapat diambil beberapa kesimpulan :

1. Alat yang dibuat dapat bekerja dengan baik sesuai dengan perancangan.

2. Sinyal informasi yang dikirimkan pemancar dapat diterima dengan baik pada

radius 5 meter. Secara kualitatif semakin tinggi amplitudo tone yang dikirim

semakin tinggi pula bunyi tone yang terdengar pada pesawat penerima AM.

B. Saran

1. Rangkaian Phase Locked Loop (PLL) harus dibuat dengan baik, karena

komponen dan grounding rangkaian berpengaruh.

2. Adanya pengembangan alat ini untuk jangka waktu kedepan.

3. Diperlukan sinkronisasi antara pemancar dan penerima AM frequency

hopping yang baik agar proses transmisi data tidak ada kesalahan.

56

DAFTAR PUSTAKA

[1] Roody, Dennis & Coolen, Jhon. 2001. Komunikasi Elektonik. Jakarta: PT. Prenhallindo.

[2] Mouly, M and Pautet, M.B. 1992. The GSM Sistem fer Mobile Communication. Palaiseau: M. Mouly et Marie-B. Pauttet.

[3] Lee, William C.y. 1998. Mobile Comunication Engineering. Singapore.: McGraw-Hill

[4] Skalar B. 1998. Digital Fundamental and Application. Upper Saddle River, NJ: Prentice Hall

[5] Omnispread Communication. 1999. Direc Sequance vs Frequency hopping. URL: http://www. Omnispread.com/direc-vs-hopping.html

[6] Badell, P. 1999. Cellular/PCS Management. A Real World Perspective. New York: McGraw-Hill.

[7] Boylestad, Robert L.1996 Electronic Devices and Circuit Theory. New Jersey: Prentice Hall

[8] Malik.R, Norbert, Electronic Circuits Analysis, Simulation and Design,

Prentice –Hall international Inc, 1995. [9] Roland.E, Best, Phase Locked Loop Theory, Design and Application, Mcgraw

Hill Inc, New York, 1984. [10] _____, ______, 74HC/HCT4046A Phase-locked-loop with VCO, Philips

Semiconductors. [11] Malvino, Albert Paul, Prinsip-prinsip Elektronika, edisi ketiga jilid pertama,

Erlangga, Jakarta, 1986.

57

[12] _____, ______, LM555, Timer, National Semiconductor Corporation, 1995.

Diakses pada 24 Januari 2007.

[13] Wijaya, Damar, “Peningkatan Kapasitas Sistem dan Kualitas Sinyal Pada

Jaringan GSM dengan Frekuensi Hopping”, Majalah SIGMA., vol 5. No 2, hal. 171-183, Juli 2002..

[14] _____, ________, TC74HC4060 14-Stage Binary Counter/Oscilator,

www.TOSHIBA.com, 1998. [15] _____, ________, TC9122P High-Speed BCD Programmable Counter,

www.TOSHIBA.com.

58

http://www.toshiba.com/

http://www.toshiba.com/

Data spektrum frekuensi sinyal informasi pada penerima AM

Frekuensi carrier pemancar 1000 KHz

1. sinyal informasi 1 kHz



Frekuensi carrier pemancar 1050 KHz


Andreas Rony Marlino 015114033 <Rev Code>

PEMANCAR AM DENGAN FREQUENCY HOPPING

Custom

1 1Monday , October 01, 2007

Title

Size Document Number Rev

Date: Sheet of

DIV 1000

R1010K

Y110.240Mhz

C1660pF

R111K

C1539pFC20

100pF

J9

9V

1

R3510K

R81K

R91.6K

T1

OT426

1 5

6

4 8

ANTENA

C19

1uF

R32

10K

VCC_BAR

R2510K

R3110K

C180.1uF

R17

100K

Q3IRF5102

13

L2

2.5mH

C5

1.6nF

R3310K

C61.8nF

U12

74HC4046/SO

34

14

6

75

1112

12

13

9

1015

168

CINVCOUT

SIN

CX

CXINHR1R2

PPP1

P2

VCOIN

DEMOZEN

VD

DVS

S

L11uH

J35

VCC (5V)1

PEMBAGI TERPROGRAM

C210.1uF

U13LM555/TO

2

5

3

7

6

4 81

TR

CV

Q

DIS

THR

R

VC

CG

ND

VCC_BAR

OSILATORREFERENSI

R627k

U10

CD4060B/SO

812

1516

45

6

7

1314

123

91011

GN

DRST

Q10VDD

Q6Q5

Q7

Q4

Q9Q8

Q12Q13Q14

Ø0Ø0Ø1

Q1

2n3904

3

2

1

XTAL OSC

R34

10K

DIV 10

U5

74LS90

141

2367

129811

510

AB

R0(1)R0(2)R9(1)R9(2)

QAQBQCQD

VCC

GN

D

TIMER

U8TCP9122P

1

45

10

12131415161718

23

6789

11

VDD

B0C0

D1

B2C2D2A3B3

POUTGND

PINA0

D0A1B1C1

A2

R18

10K

C4

100pF

R3010K

TRANSISTOR SEBAGAI SAKLAR

Q2

2n3904

3

2

1

R710K

Q13940

MODULATOR

VCO

C7100uf

R23

10K

R271Meg1

3

2

2N3904 / M

MB

T3904 / MM

PQ

3904 / PZT3904

Discrete POWER & SignalTechnologies

N

2N3904 MMBT3904

MMPQ3904 PZT3904

NPN General Purpose Amplifier

This device is designed as a general purpose amplifier and switch.The useful dynamic range extends to 100 mA as a switch and to100 MHz as an amplifier. Sourced from Process 23.

Absolute Maximum Ratings* TA = 25°C unless otherwise noted

*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.

NOTES :1) These ratings are based on a maximum junction temperature of 150 degrees C.2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.

Symbol Parameter Value UnitsVCEO Collector-Emitter Voltage 40 V

VCBO Collector-Base Voltage 60 V

VEBO Emitter-Base Voltage 6.0 V

IC Collector Current - Continuous 200 mA

TJ, Tstg Operating and Storage Junction Temperature Range -55 to +150 °C

CB E

TO-92

BC

C

SOT-223

E

C

B

E

SOT-23Mark: 1A

CC

CC

CC

C C

SOIC-16

EB

EB

EB

E B

2N3904 / M

MB

T3904 / MM

PQ

3904 / PZT3904

NPN General Purpose Amplifier(continued)

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Max Units

V(BR)CEO Collector-Emitter Breakdown Voltage IC = 1.0 mA, IB = 0 40 V

V(BR)CBO Collector-Base Breakdown Voltage IC = 10 µA, IE = 0 60 V

V(BR)EBO Emitter-Base Breakdown Voltage IE = 10 µA, IC = 0 6.0 V

IBL Base Cutoff Current VCE = 30 V, VEB = 0 50 nA

ICEX Collector Cutoff Current VCE = 30 V, VEB = 0 50 nA

OFF CHARACTERISTICS

ON CHARACTERISTICS*

SMALL SIGNAL CHARACTERISTICS

SWITCHING CHARACTERISTICS (except MMPQ3904)

*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%

NPN (Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259 Ise=6.734 Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2Isc=0 Ikr=0 Rc=1 Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75 Tr=239.5n Tf=301.2pItf=.4 Vtf=4 Xtf=2 Rb=10)

Spice Model

fT Current Gain - Bandwidth Product IC = 10 mA, VCE = 20 V,f = 100 MHz

300 MHz

Cobo Output Capacitance VCB = 5.0 V, IE = 0,f = 1.0 MHz

4.0 pF

Cibo Input Capacitance VEB = 0.5 V, IC = 0,f = 1.0 MHz

8.0 pF

NF Noise Figure (except MMPQ3904) IC = 100 mA, VCE = 5.0 V,RS =1.0kW, f=10 Hz to 15.7 kHz

5.0 dB

td Delay Time VCC = 3.0 V, VBE = 0.5 V, 35 ns

tr Rise Time IC = 10 mA, IB1 = 1.0 mA 35 ns

ts Storage Time VCC = 3.0 V, IC = 10mA 200 ns

tf Fall Time IB1 = IB2 = 1.0 mA 50 ns

hFE DC Current Gain IC = 0.1 mA, VCE = 1.0 VIC = 1.0 mA, VCE = 1.0 VIC = 10 mA, VCE = 1.0 VIC = 50 mA, VCE = 1.0 VIC = 100 mA, VCE = 1.0 V

40701006030

300

VCE(sat) Collector-Emitter Saturation Voltage IC = 10 mA, IB = 1.0 mAIC = 50 mA, IB = 5.0 mA

0.20.3

VV

VBE(sat) Base-Emitter Saturation Voltage IC = 10 mA, IB = 1.0 mAIC = 50 mA, IB = 5.0 mA

0.65 0.850.95

VV

2N3904 / M

MB

T3904 / MM

PQ

3904 / PZT3904

Thermal Characteristics TA = 25°C unless otherwise noted

Symbol Characteristic Max Units2N3904 *PZT3904

PD Total Device DissipationDerate above 25°C

6255.0

1,0008.0

mWmW/°C

RqJC Thermal Resistance, Junction to Case 83.3 °C/W

RqJA Thermal Resistance, Junction to Ambient 200 125 °C/W

Symbol Characteristic Max Units**MMBT3904 MMPQ3904

PD Total Device DissipationDerate above 25°C

3502.8

1,0008.0

mWmW/°C

RqJA Thermal Resistance, Junction to AmbientEffective 4 DieEach Die

357125240

°C/W°C/W°C/W

Typical Characteristics

Base-Emitter ON Voltage vsCollector Current

Pr23

0.1 1 10 1000.2

0.4

0.6

0.8

1

I - COLLECTOR CURRENT (mA)V

-

BA

SE

-EM

ITTE

R O

N V

OLT

AG

E (V

)B

E(O

N)

C

V = 5VCE

25 °C

125 °C

- 40 °C

Typical Pulsed Current Gainvs Collector Current

0.1 1 10 1000

100

200

300

400

500

I - COLLECTOR CURRENT (mA)h

- T

YP

ICA

L P

ULS

ED

CU

RR

EN

T G

AIN

FE

- 40º C

25 °C

C

V = 5VCE

125 °C

*Device mounted on FR-4 PCB 36 mm X 18 mm X 1.5 mm; mounting pad for the collector lead min. 6 cm2.

**Device mounted on FR-4 PCB 1.6" X 1.6" X 0.06."


Base-Emitter SaturationVoltage vs Collector Current

Pr23

0.1 1 10 100

0.4

0.6

0.8

1

I - COLLECTOR CURRENT (mA)

V

-

BA

SE

-EM

ITTE

R V

OLT

AG

E (V

)B

ES

AT

C

ββ = 10

25 °C

125 °C

- 40 °C

Collector-Emitter SaturationVoltage vs Collector Current

Pr23

0.1 1 10 100

0.05

0.1

0.15

I - COLLECTOR CURRENT (mA)V

-

CO

LLE

CTO

R-E

MIT

TER

VO

LTA

GE

(V)

CE

SA

T

25 °C

C

ββ = 10

125 °C

- 40 °C

2N3904 / M

MB

T3904 / MM

PQ

3904 / PZT3904


Typical Characteristics (continued)

Collector-Cutoff Currentvs Ambient Temperature

Pr23

25 50 75 100 125 150

0.1

1

10

100

500

T - AMBIENT TEMPERATURE ( C)

I

- CO

LLE

CTO

R C

UR

RE

NT

(nA

)

A

V = 30VCB

CB

O

°

Capacitance vs Reverse Bias Voltage

0.1 1 10 1001

2

3

45

10

REVERSE BIAS VOLTAGE (V)

CA

PA

CIT

AN

CE

(pF)

C obo

C ibo

f = 1.0 MHz

Noise Figure vs Frequency

0.1 1 10 1000

2

4

6

8

10

12

f - FREQUENCY (kHz)

NF

- N

OIS

E F

IGU

RE

(dB

)

V = 5.0VCE

I = 100 µµA, R = 500 ΩΩC S

I = 1.0 mA R = 200 ΩΩC

S

I = 50 µµA R = 1.0 k ΩΩ

CS

I = 0.5 mA R = 200 ΩΩC

S

kΩΩ

Noise Figure vs Source Resistance

Pr23

0.1 1 10 1000

2

4

6

8

10

12

R - SOURCE RESISTANCE ( )

NF

- N

OIS

E F

IGU

RE

(dB

)

I = 100 µµAC

I = 1.0 mAC

S

I = 50 µµAC

I = 5.0 mAC

- DE

GR

EE

S

0

406080100120140160

20

180

Current Gain and Phase Anglevs Frequency

1 10 100 100005

101520253035404550

f - FREQUENCY (MHz)

h

- C

UR

RE

NT

GA

IN (d

B)

θθ

V = 40VCEI = 10 mAC

h fe

fe

Power Dissipation vsAmbient Temperature

0 25 50 75 100 125 1500

0.25

0.5

0.75

1

TEMPERATURE ( C)

P

- PO

WE

R D

ISS

IPA

TIO

N (W

)D

o

SOT-223

SOT-23

TO-92

2N3904 / M

MB

T3904 / MM

PQ

3904 / PZT3904


Typical Characteristics (continued)

Turn-On Time vs Collector Current

Pr23

1 10 1005

10

100

500


TIM

E (

nS)

I = I = B1

C

B2I c

1040V

15V

2.0V

t @ V = 0VCBd

t @ V = 3.0VCCr

Rise Time vs Collector Current

Pr23

1 10 1005

10

100

500


t -

RIS

E T

IME

(ns

)

I = I = B1

C

B2I c

10

T = 125°C

T = 25°CJ

V = 40VCC

r

J

Storage Time vs Collector Current

Pr23

1 10 1005

10

100

500


t -

STO

RA

GE

TIM

E (

ns) I = I = B1

C

B2I c

10

S

T = 125°C

T = 25°CJ

J

Fall Time vs Collector Current

Pr23

1 10 1005

10

100

500


t -

FA

LL T

IME

(ns

)

I = I = B1

C

B2I c

10V = 40VCC

f

T = 125°C

T = 25°CJ

J

2N3904 / M

MB

T3904 / MM

PQ

3904 / PZT3904


Test Circuits

10 K Ω

3.0 V

275 Ω

t1

C1 < 4.0 pF

Duty Cycle = 2%

Duty Cycle = 2%

< 1.0 ns

- 0.5 V

300 ns10.6 V

10 < t1 < 500 µs 10.9 V

- 9.1 V

< 1.0 ns

0

0

10 K Ω

3.0 V

275 Ω

C1 < 4.0 pF

1N916

FIGURE 2: Storage and Fall Time Equivalent Test Circuit

FIGURE 1: Delay and Rise Time Equivalent Test Circuit

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.

http://www.datasheetcatalog.com



TL/F/6381

DM

74LS90/D

M74LS93

Decade

and

Bin

ary

Counte

rs

June 1989

DM74LS90/DM74LS93Decade and Binary Counters

General DescriptionEach of these monolithic counters contains four master-

slave flip-flops and additional gating to provide a divide-by-

two counter and a three-stage binary counter for which the

count cycle length is divide-by-five for the ’LS90 and divide-

by-eight for the ’LS93.

All of these counters have a gated zero reset and the LS90

also has gated set-to-nine inputs for use in BCD nine’s com-

plement applications.

To use their maximum count length (decade or four bit bina-

ry), the B input is connected to the QA output. The input

count pulses are applied to input A and the outputs are as

described in the appropriate truth table. A symmetrical di-

vide-by-ten count can be obtained from the ’LS90 counters

by connecting the QD output to the A input and applying the

input count to the B input which gives a divide-by-ten square

wave at output QA.

FeaturesY Typical power dissipation 45 mWY Count frequency 42 MHz

Connection Diagrams (Dual-In-Line Packages)

TL/F/6381–1

Order Number DM74LS90M or DM74LS90N

See NS Package Number M14A or N14A

TL/F/6381–2

Order Number DM74LS93M or DM74LS93N

See NS Package Number M14A or N14A

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage (Reset) 7V

Input Voltage (A or B) 5.5V

Operating Free Air Temperature Range

DM74LS 0§C to a70§CStorage Temperature Range b65§C to a150§C

Note: The ‘‘Absolute Maximum Ratings’’ are those valuesbeyond which the safety of the device cannot be guaran-teed. The device should not be operated at these limits. Theparametric values defined in the ‘‘Electrical Characteristics’’table are not guaranteed at the absolute maximum ratings.The ‘‘Recommended Operating Conditions’’ table will definethe conditions for actual device operation.

Recommended Operating Conditions

Symbol ParameterDM74LS90

UnitsMin Nom Max

VCC Supply Voltage 4.75 5 5.25 V

VIH High Level Input Voltage 2 V

VIL Low Level Input Voltage 0.8 V

IOH High Level Output Current b0.4 mA

IOL Low Level Output Current 8 mA

fCLK Clock Frequency (Note 1) A to QA 0 32MHz

B to QB 0 16

fCLK Clock Frequency (Note 2) A to QA 0 20MHz

B to QB 0 10

tW Pulse Width (Note 1) A 15

B 30 ns

Reset 15


B 50 ns

Reset 25

tREL Reset Release Time (Note 1) 25 ns


TA Free Air Operating Temperature 0 70 §CNote 1: CL e 15 pF, RL e 2 kX, TA e 25§C and VCC e 5V.

Note 2: CL e 50 pF, RL e 2 kX, TA e 25§C and VCC e 5V.

’LS90 Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions MinTyp

Max Units(Note 1)

VI Input Clamp Voltage VCC e Min, II e b18 mA b1.5 V

VOH High Level Output VCC e Min, IOH e Max2.7 3.4 V

Voltage VIL e Max, VIH e Min

VOL Low Level Output VCC e Min, IOL e Max

Voltage VIL e Max, VIH e Min 0.35 0.5V

(Note 4)

IOL e 4 mA, VCC e Min 0.25 0.4

II Input Current @ Max VCC e Max, VI e 7V Reset 0.1

Input VoltageVCC e Max A 0.2 mA

VI e 5.5VB 0.4

2

’LS90 Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted) (Continued)


Max Units(Note 1)

IIH High Level Input VCC e Max, VI e 2.7V Reset 20

CurrentA 40 mA

B 80

IIL Low Level Input VCC e Max, VI e 0.4V Reset b0.4

CurrentA b2.4 mA

B b3.2

IOS Short Circuit VCC e Max (Note 2)b20 b100 mA

Output Current

ICC Supply Current VCC e Max (Note 3) 9 15 mA

Note 1: All typicals are at VCC e 5V, TA e 25§C.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded.

Note 4: QA outputs are tested at IOL e Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.

’LS90 Switching Characteristicsat VCC e 5V and TA e 25§C (See Section 1 for Test Waveforms and Output Load)

From (Input)RL e 2 kX

Symbol Parameter To (Output) CL e 15 pF CL e 50 pF Units

Min Max Min Max

fMAX Maximum Clock A to QA 32 20MHz

Frequency B to QB 16 10

tPLH Propagation Delay TimeA to QA 16 20 ns

Low to High Level Output

tPHL Propagation Delay TimeA to QA 18 24 ns

High to Low Level Output

tPLH Propagation Delay TimeA to QD 48 52 ns


tPHL Propagation Delay TimeA to QD 50 60 ns


tPLH Propagation Delay TimeB to QB 16 23 ns


tPHL Propagation Delay TimeB to QB 21 30 ns


tPLH Propagation Delay TimeB to QC 32 37 ns


tPHL Propagation Delay TimeB to QC 35 44 ns


tPLH Propagation Delay TimeB to QD 32 36 ns


tPHL Propagation Delay TimeB to QD 35 44 ns


tPLH Propagation Delay Time SET-9 to30 35 ns

Low to High Level Output QA, QD

tPHL Propagation Delay Time SET-9 to40 48 ns

High to Low Level Output QB, QC


High to Low Level Output Any Q

3

Recommended Operating Conditions

Symbol ParameterDM74LS93

UnitsMin Nom Max

VCC Supply Voltage 4.75 5 5.25 V

VIH High Level Input Voltage 2 V

VIL Low Level Input Voltage 0.8 V

IOH High Level Output Current b0.4 mA

IOL Low Level Output Current 8 mA

fCLK Clock Frequency (Note 1) A to QA 0 32

B to QB 0 16MHz

fCLK Clock Frequency (Note 2) A to QA 0 20

B to QB 0 10


B 30 ns

Reset 15


B 50 ns

Reset 25



TA Free Air Operating Temperature 0 70 §CNote 1: CL e 15 pF, RL e 2 kX, TA e 25§C and VCC e 5V.

Note 2: CL e 50 pF, RL e 2 kX, TA e 25§C and VCC e 5V.

’LS93 Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)


Max Units(Note 1)

VI Input Clamp Voltage VCC e Min, II e b18 mA b1.5 V

VOH High Level Output VCC e Min, IOH e Max2.7 3.4 V

Voltage VIL e Max, VIH e Min

VOL Low Level Output VCC e Min, IOL e Max

Voltage VIL e Max, VIH e Min 0.35 0.5 V

(Note 4)

IOL e 4 mA, VCC e Min 0.25 0.4

II Input Current @Max VCC e Max, VI e 7V Reset 0.1

Input VoltageVCC e Max A 0.2 mA

VI e 5.5VB 0.4

IIH High Level Input VCC e Max Reset 20

Current VI e 2.7VA 40 mA

B 80

4

’LS93 Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted) (Continued)


Max Units(Note 1)

IIL Low Level Input VCC e Max, VI e 0.4V Reset b0.4

CurrentA b2.4 mA

B b1.6

IOS Short Circuit VCC e Max (Note 2)b20 b100 mA

Output Current

ICC Supply Current VCC e Max (Note 3) 9 15 mA

Note 1: All typicals are at VCC e 5V, TA e 25§C.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded.

Note 4: QA outputs are tested at IOL e max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.

’LS93 Switching Characteristicsat VCC e 5V and TA e 25§C (See Section 1 for Test Waveforms and Output Load)

From (Input)RL e 2 kX

Symbol Parameter To (Output) CL e 15 pF CL e 50 pF Units

Min Max Min Max

fMAX Maximum Clock A to QA 32 20MHz

FrequencyB to QB 16 10

tPLH Propagation Delay TimeA to QA 16 20 ns


tPHL Propagation Delay TimeA to QA 18 24 ns


tPLH Propagation Delay TimeA to QD 70 85 ns


tPHL Propagation Delay TimeA to QD 70 90 ns


tPLH Propagation Delay TimeB to QB 16 23 ns


tPHL Propagation Delay TimeB to QB 21 30 ns


tPLH Propagation Delay TimeB to QC 32 37 ns


tPHL Propagation Delay TimeB to QC 35 44 ns


tPLH Propagation Delay TimeB to QD 51 60 ns


tPHL Propagation Delay TimeB to QD 51 70 ns



High to Low Level Output Any Q

5

Function Tables

LS90

BCD Count Sequence

(See Note A)

CountOutput

QD QC QB QA

0 L L L L

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 L H L H

6 L H H L

7 L H H H

8 H L L L

9 H L L H

LS90

Bi-Quinary (5-2)

(See Note B)

CountOutput

QA QD QC QB

0 L L L L

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 H L L L

6 H L L H

7 H L H L

8 H L H H

9 H H L L

LS93

Count Sequence

(See Note C)

CountOutput

QD QC QB QA

0 L L L L

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 L H L H

6 L H H L

7 L H H H

8 H L L L

9 H L L H

10 H L H L

11 H L H H

12 H H L L

13 H H L H

14 H H H L

15 H H H H

Note A: Output QA is connected to input B for BCD count.

Note B: Output QD is connected to input A for bi-quinary count.

Note C: Output QA is connected to input B.

Note D: H e High Level, L e Low Level, X e Don’t Care.

LS90

Reset/Count Truth Table

Reset Inputs Output

R0(1) R0(2) R9(1) R9(2) QD QC QB QA

H H L X L L L L

H H X L L L L L

X X H H H L L H

X L X L COUNT

L X L X COUNT

L X X L COUNT

X L L X COUNT

LS93

Reset/Count Truth Table

Reset Inputs Output

R0(1) R0(2) QD QC QB QA

H H L L L L

L X COUNT

X L COUNT

6

Logic Diagrams

LS90

TL/F/6381–3

LS93

TL/F/6381–4

The J and K inputs shown without connection are for reference only and are functionally at a high level.

7

Physical Dimensions inches (millimeters)

14-Lead Small Outline Molded Package (M)

Order Number DM74LS90M or DM74LS93M

NS Package Number M14A

9

DM

74LS90/D

M74LS93

Decade

and

Bin

ary

Counte

rsPhysical Dimensions inches (millimeters) (Continued)

14-Lead Molded Dual-In-Line Package (N)

Order Number DM74LS90N or DM74LS93N

NS Package Number N14A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

National Semiconductor National Semiconductor National Semiconductor National SemiconductorCorporation Europe Hong Kong Ltd. Japan Ltd.1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, KowloonFax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600Italiano Tel: (a49) 0-180-534 16 80 Fax: (852) 2736-9960

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

© 2000 Fairchild Semiconductor Corporation DS011677 www.fairchildsemi.com

April 1994

Revised January 2000

74VH

C4066 Q

uad

An

alog

Sw

itch

74VHC4066Quad Analog Switch

General DescriptionThese devices are digitally controlled analog switches uti-lizing advanced silicon-gate CMOS technology. Theseswitches have low “on” resistance and low “off” leakages.They are bidirectional switches, thus any analog input maybe used as an output and visa-versa. Also the 4066switches contain linearization circuitry which lowers the“on” resistance and increases switch linearity. The 4066devices allow control of up to 12V (peak) analog signalswith digital control signals of the same range. Each switchhas its own control input which disables each switch whenlow. All analog inputs and outputs and digital inputs areprotected from electrostatic damage by diodes to VCC andground.

Features Typical switch enable time: 15 ns

Wide analog input voltage range: 0–12V

Low “on” resistance: 30 typ. ('4066)

Low quiescent current: 80 µA maximum (74VHC)

Matched switch characteristics

Individual switch controls

Pin and function compatible with the 74HC4066

Ordering Code:

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Top View

Schematic Diagram

Truth Table

Order Number Package Number Package Description

74VHC4066M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

74VHC4066MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC4066N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Input Switch

CTL I/O–O/I

L “OFF”

H “ON”

www.fairchildsemi.com 2

74V

HC

4066 Absolute Maximum Ratings(Note 1)

(Note 2)

Recommended OperatingConditions

Note 1: Absolute Maximum Ratings are those values beyond which dam-age to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating — plastic “N” package: −12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 4)

Note 4: For a power supply of 5V ± 10% the worst case on resistance (RON) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing

with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current occurs

for CMOS at the higher voltage and so the 5.5V values should be used.

Note 5: At supply voltages (VCC – GND) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that

these devices be used to transmit digital only when using these supply voltages.

Supply Voltage (VCC) −0.5 to +15V

DC Control Input Voltage (VIN) −1.5 to VCC + 1.5V

DC Switch I/O Voltage (VIO) VEE − 0.5 to VCC + 0.5V

Clamp Diode Current (IIK, IOK) ±20 mA

DC Output Current, per pin (IOUT) ±25 mA

DC VCC or GND Current, per pin (ICC) ±50 mA

Storage Temperature Range (TSTG) −65°C to +150°CPower Dissipation (PD) (Note 3) 600 mW

S.O. Package only 500 mW

Lead Temperature (TL)

(Soldering 10 seconds) 260°C

Min Max Units

Supply Voltage (VCC) 2 12 V

DC Input or Output Voltage 0 VCC V

(VIN, VOUT)

Operating Temperature Range (TA) −40 +85 °CInput Rise or Fall Times (tr, tf)

VCC = 2.0V 1000 ns

VCC = 4.5V 500 ns

VCC = 9.0V 400 ns

Symbol Parameter Conditions VCCTA=25°C TA=−40 to 85°C

UnitsTyp Guaranteed Limits

VIH Minimum HIGH Level 2.0V 1.5 1.5 V

Input Voltage 4.5V 3.15 3.15 V

9.0V 6.3 5.3 V

12.0V 8.4 8.4 V

VIL Maximum LOW Level 2.0V 0.5 0.5 V

Input Voltage 4.5V 1.35 1.35 V

9.0V 2.7 2.7 V

12.0V 3.6 3.6 V

RON Maximum “ON” Resistance VCTL = VIH, IS = 2.0 mA 4.5V 100 170 200 Ω

See (Note 5) VIS = VCC to GND 9.0V 50 85 105 Ω

(Figure 1) 12.0V 30 70 85 Ω

2.0V 120 180 215 Ω

VCTL = VIH, IS = 2.0 mA 4.5V 50 80 100 Ω

VIS = VCC or GND 9.0V 35 60 75 Ω

(Figure 1) 12.0V 20 40 60 Ω

RON Maximum “ON” Resistance VCTL = VIH 4.5V 10 15 20 Ω

Matching VIS = VCC to GND 9.0V 5 10 15 Ω

12.0V 5 10 15 Ω

IIN Maximum Control VIN = VCC or GND ±0.05 ±0.5 µA

Input Current VCC = 2 − 6V

IIZ Maximum Switch “OFF” VOS = VCC or GND 6.0V 10 ±60 ±600 nA

Leakage Current VIS = GND or VCC 9.0V 15 ±80 ±800 nA

VCTL = VIL (Figure 2) 12.0V 20 ±100 ±1000 nA

IIZ Maximum Switch “ON” VIS = VCC to GND 6.0V 10 ±40 ±150 nA

Leakage Current VCTL = VIH 9.0V 15 ±50 ±200 nA

VOS = OPEN (Figure 3) 12.0V 20 ±60 ±300 nA

ICC Maximum Quiescent VIN = VCC or GND 6.0V 1.0 10 µA

Supply Current IOUT = 0 µA 9.0V 2.0 20 µA

12.0V 4.0 40 µA

3 www.fairchildsemi.com

74VH

C4066

AC Electrical CharacteristicsVCC = 2.0V−6.0V VEE = 0V−12V, CL = 50 pF (unless otherwise specified)

Note 6: Adjust 0 dBm for F = 1 kHz (Null RL/RON Attenuation).

Note 7: VIS is centered at VCC/2.

Note 8: Adjust input for 0 dBm.

Symbol Parameter Conditions VCCTA=25°C TA=−40 to 85°C

UnitsTyp Guaranteed Limits

tPHL, tPLH Maximum Propagation 3.3V 25 30 20 ns

Delay Switch In to Out 4.5V 5 10 13 ns

9.0V 4 8 10 ns

12.0V 3 7 11 ns

tPZL, tPZH Maximum Switch Turn RL = 1 kΩ 3.3V 30 58 73 ns

“ON” Delay 4.5V 12 20 25 ns

9.0V 6 12 15 ns

12.0V 5 10 13 ns

tPHZ, tPLZ Maximum Switch Turn RL = 1 kΩ 3.3V 60 100 125 ns

“OFF” Delay 4.5V 25 36 45 ns

9.0V 20 32 40 ns

12.0V 15 30 38

Minimum Frequency RL = 600Ω 4.5V 40 MHz

Response (Figure 7) VIS = 2 VPP at (VCC/2) 9.0V 100 MHz

20 log(VO/VI) = −3 dB (Note 6)(Note 7)

Crosstalk Between RL = 600Ω, F = 1 MHz

any Two Switches (Note 7)(Note 8) 4.5V −52 dB

(Figure 8) 9.0V −50 dB

Peak Control to Switch RL = 600Ω, F = 1 MHz 4.5V 100 mV

Feedthrough Noise CL = 50 pF 9.0V 250 mV

(Figure 9)

Switch OFF Signal RL = 600Ω, F = 1 MHz

Feedthrough V(CT) VIL

Isolation (Note 7)(Note 8) 4.5V −42 dB

(Figure 10) 9.0V −44 dB

THD Total Harmonic RL = 10 kΩ, CL = 50 pF,

Distortion F = 1 kHz

(Figure 11) VIS = 4 VPP 4.5V .013 %

VIS = 8 VPP 9.0V .008 %

CIN Maximum Control 5 10 10 pF

Input Capacitance

CIN Maximum Switch 20 pF

Input Capacitance

CIN Maximum Feedthrough VCTL = GND 0.5 pF

Capacitance

CPD Power Dissipation 15 pF

Capacitance


74V

HC

4066 AC Test Circuits and Switching Time Waveforms

FIGURE 1. “ON” Resistance

FIGURE 2. “OFF” Channel Leakage Current

FIGURE 3. “ON” Channel Leakage Current

FIGURE 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output

FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output


74VH

C4066

AC Test Circuits and Switching Time Waveforms (Continued)

FIGURE 6. tPZH, tPHZ Propagation Delay Time Control to Signal Output

FIGURE 7. Frequency Response

Crosstalk and Distortion Test Circuits

FIGURE 8. Crosstalk: Control Input to Signal Output

FIGURE 9. Crosstalk Between Any Two Switches


74V

HC

4066 Crosstalk and Distortion Test Circuits (Continued)

FIGURE 10. Switch OFF Signal Feedthrough Isolation

FIGURE 11. Sinewave Distortion

Typical Performance Characteristics

Typical “ON” Resistance Typical Crosstalk BetweenAny Two Switches

Typical Frequency Response

Special ConsiderationsIn certain applications the external load-resistor current may include both VCC and signal line components. To avoid draw-ing VCC current when switch current flows into the analog switch input pins, the voltage drop across the switch must notexceed 0.6V (calculated from the ON resistance).


74VH

C4066

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 NarrowPackage Number M14A


74V

HC

4066 Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC14


74VH

C4066 Q

uad

An

alog

Sw

itchPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WidePackage Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.

2. A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

Data sheet acquired from Harris SemiconductorSCHS049C − Revised October 2003

CD4060B consists of an oscillatorsection and 14 ripple-carry binary counterstages. The oscillator configuration allowsdesign of either RC or crystal oscillatorcircuits. A RESET input is provided whichresets the counter to the all-O’s state anddisables the oscillator. A high level on theRESET line accomplishes the reset function.All counter stages are master-slave flip-flops.The state of the counter is advanced one stepin binary order on the negative transition of I(and O). All inputs and outputs are fullybuffered. Schmitt trigger action on theinput-pulse line permits unlimitedinput-pulse rise and fall times.

The CD4060B-series types are supplied in16-lead hermetic dual-in-line ceramic packages(F3A suffix), 16-lead dual-in-line plasticpackages (E suffix), 16-lead small-outlinepackages (M, M96, MT, and NSR suffixes), and16-lead thin shrink small-outline packages (PWand PWR suffixes).

Copyright 2003, Texas Instruments Incorporated

PACKAGING INFORMATION

Orderable Device Status (1) PackageType

PackageDrawing

Pins PackageQty

Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

CD4060BE ACTIVE PDIP N 16 25 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type

CD4060BEE4 ACTIVE PDIP N 16 25 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type

CD4060BF ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type

CD4060BF3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type

CD4060BM ACTIVE SOIC D 16 40 Green (RoHS &no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CD4060BM96 ACTIVE SOIC D 16 2500 Green (RoHS &no Sb/Br)


CD4060BM96E4 ACTIVE SOIC D 16 2500 Green (RoHS &no Sb/Br)


CD4060BME4 ACTIVE SOIC D 16 40 Green (RoHS &no Sb/Br)


CD4060BMT ACTIVE SOIC D 16 250 Green (RoHS &no Sb/Br)


CD4060BMTE4 ACTIVE SOIC D 16 250 Green (RoHS &no Sb/Br)


CD4060BNSR ACTIVE SO NS 16 2000 Green (RoHS &no Sb/Br)


CD4060BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS &no Sb/Br)


CD4060BPW ACTIVE TSSOP PW 16 90 Green (RoHS &no Sb/Br)


CD4060BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS &no Sb/Br)


CD4060BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &no Sb/Br)


CD4060BPWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS &no Sb/Br)


(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please checkhttp://www.ti.com/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHScompatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.

PACKAGE OPTION ADDENDUM

www.ti.com 18-Jul-2006

Addendum-Page 1

http://www.ti.com/productcontent

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 18-Jul-2006

Addendum-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE14 PINS SHOWN

0,65 M0,10

0,10

0,25

0,500,75

0,15 NOM

Gage Plane

28

9,80

9,60

24

7,90

7,70

2016

6,60

6,40

4040064/F 01/97

0,30

6,606,20

8

0,19

4,304,50

7

0,15

14

A

1

1,20 MAX

14

5,10

4,90

8

3,10

2,90

A MAX

A MIN

DIMPINS **

0,05

4,90

5,10

Seating Plane

0°–8°

NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.D. Falls within JEDEC MO-153

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. To minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third-party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproductionof this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable forsuch altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for thatproduct or service voids all express and any implied warranties for the associated TI product or service andis an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and applicationsolutions:

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Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


©2002 Fairchild Semiconductor Corporation

www.fairchildsemi.comwww.fairchildsemi.comwww.fairchildsemi.comwww.fairchildsemi.com

Rev. 1.0.3

FeaturesFeaturesFeaturesFeatures• High Current Drive Capability (200mA)• Adjustable Duty Cycle• Temperature Stability of 0.005%/°C• Timing From µSec to Hours• Turn off Time Less Than 2µSec

ApplicationsApplicationsApplicationsApplications• Precision Timing• Pulse Generation• Time Delay Generation• Sequential Timing

DescriptionDescriptionDescriptionDescriptionThe LM555/NE555/SA555 is a highly stable controllercapable of producing accurate timing pulses. With amonostable operation, the time delay is controlled by oneexternal resistor and one capacitor. With an astable operation, the frequency and duty cycle are accurately controlled by two external resistors and one capacitor.

8-DIP8-DIP8-DIP8-DIP

8-SOP8-SOP8-SOP8-SOP

1

1

Internal Block DiagramInternal Block DiagramInternal Block DiagramInternal Block Diagram

F/FF/FF/FF/FOutPutOutPutOutPutOutPutStageStageStageStage

1111

7777

5555

2222

3333

4444

6666

8888RRRR RRRR RRRR

Comp.Comp.Comp.Comp.

Comp.Comp.Comp.Comp.

Discharging Tr.Discharging Tr.Discharging Tr.Discharging Tr.

VrefVrefVrefVref

VccVccVccVcc

DischargeDischargeDischargeDischarge

ThresholdThresholdThresholdThreshold

ControlControlControlControlVoltageVoltageVoltageVoltage

GNDGNDGNDGND

TriggerTriggerTriggerTrigger

OutputOutputOutputOutput

ResetResetResetReset

LM555/NE555/SA555Single Timer

LM555/NE555/SA555

2222

Absolute Maximum Ratings (TAbsolute Maximum Ratings (TAbsolute Maximum Ratings (TAbsolute Maximum Ratings (TAAAA = 25 = 25 = 25 = 25°°°°C)C)C)C)ParameterParameterParameterParameter SymbolSymbolSymbolSymbol ValueValueValueValue UnitUnitUnitUnit

Supply Voltage VCC 16 V

Lead Temperature (Soldering 10sec) TLEAD 300 °CPower Dissipation PD 600 mW

Operating Temperature Range LM555/NE555SA555

TOPR 0 ~ +70-40 ~ +85

°C

Storage Temperature Range TSTG -65 ~ +150 °C

LM555/NE555/SA555

3333

Electrical CharacteristicsElectrical CharacteristicsElectrical CharacteristicsElectrical Characteristics(TA = 25°C, VCC = 5 ~ 15V, unless otherwise specified)

Notes:Notes:Notes:Notes:1. When the output is high, the supply current is typically 1mA less than at VCC = 5V.2. Tested at VCC = 5.0V and VCC = 15V.3. This will determine the maximum value of RA + RB for 15V operation, the max. total R = 20MΩ, and for 5V operation, the max.

total R = 6.7MΩ.4. These parameters, although guaranteed, are not 100% tested in production.

ParameterParameterParameterParameter SymbolSymbolSymbolSymbol ConditionsConditionsConditionsConditions Min.Min.Min.Min. Typ.Typ.Typ.Typ. Max.Max.Max.Max. UnitUnitUnitUnit

Supply Voltage VCC - 4.5 - 16 V

Supply Current (Low Stable) (Note1) ICCVCC = 5V, RL = ∞ - 3 6 mA

VCC = 15V, RL = ∞ - 7.5 15 mA

Timing Error (Monostable)Initial Accuracy (Note2)Drift with Temperature (Note4)Drift with Supply Voltage (Note4)

ACCUR∆t/∆T

∆t/∆VCC

RA = 1kΩ to100kΩC = 0.1µF

- 1.0500.1

3.0

0.5

%ppm/°C

%/V

Timing Error (Astable) Intial Accuracy (Note2)Drift with Temperature (Note4)Drift with Supply Voltage (Note4)

ACCUR∆t/∆T

∆t/∆VCC

RA = 1kΩ to 100kΩC = 0.1µF

- 2.251500.3

- %ppm/°C

%/V

Control Voltage VCVCC = 15V 9.0 10.0 11.0 V

VCC = 5V 2.6 3.33 4.0 V

Threshold Voltage VTHVCC = 15V - 10.0 - V

VCC = 5V - 3.33 - V

Threshold Current (Note3) ITH ---- - 0.1 0.25 µA

Trigger Voltage VTRVCC = 5V 1.1 1.67 2.2 V

VCC = 15V 4.5 5 5.6 V

Trigger Current ITR VTR = 0V 0.01 2.0 µA

Reset Voltage VRST ---- 0.4 0.7 1.0 V

Reset Current IRST ---- 0.1 0.4 mA

Low Output Voltage VOL

VCC = 15VISINK = 10mAISINK = 50mA

- 0.060.3

0.250.75

VV

VCC = 5VISINK = 5mA - 0.05 0.35 V

High Output Voltage VOH

VCC = 15VISOURCE = 200mAISOURCE = 100mA 12.75

12.513.3

- VV

VCC = 5VISOURCE = 100mA 2.75 3.3 - V

Rise Time of Output (Note4) tR ---- - 100 - ns

Fall Time of Output (Note4) tF ---- - 100 - ns

Discharge Leakage Current ILKG ---- - 20 100 nA

LM555/NE555/SA555

4444

Application InformationApplication InformationApplication InformationApplication InformationTable 1 below is the basic operating table of 555 timer:

When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes according to threshold voltage and trigger voltage.When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr. turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high.

1. Monostable Operation1. Monostable Operation1. Monostable Operation1. Monostable Operation

Table 1. Basic Operating TableTable 1. Basic Operating TableTable 1. Basic Operating TableTable 1. Basic Operating Table

Threshold Voltage Threshold Voltage Threshold Voltage Threshold Voltage (V(V(V(Vthththth)(PIN 6))(PIN 6))(PIN 6))(PIN 6)

Trigger VoltageTrigger VoltageTrigger VoltageTrigger Voltage(V(V(V(Vtrtrtrtr)(PIN 2))(PIN 2))(PIN 2))(PIN 2) Reset(PIN 4)Reset(PIN 4)Reset(PIN 4)Reset(PIN 4) Output(PIN 3)Output(PIN 3)Output(PIN 3)Output(PIN 3) Discharging Tr.Discharging Tr.Discharging Tr.Discharging Tr.

(PIN 7)(PIN 7)(PIN 7)(PIN 7)Don't care Don't care Low Low ON

Vth > 2Vcc / 3 Vth > 2Vcc / 3 High Low ONVcc / 3 < Vth < 2 Vcc / 3 Vcc / 3 < Vth < 2 Vcc / 3 High - -

Vth < Vcc / 3 Vth < Vcc / 3 High High OFF

10101010-5-5-5-5 10101010-4-4-4-4 10101010-3-3-3-3 10101010-2-2-2-2 10101010-1-1-1-1 101010100000 101010101111 10101010222210101010-3-3-3-3

10101010-2-2-2-2

10101010-1-1-1-1

101010100000

101010101111

101010102222

10M

10M

10M

10M

ΩΩΩΩ

1M1M1M1MΩΩΩΩ10

k10

k10

k10

kΩΩΩΩ10

0k10

0k10

0k10

0kΩΩΩΩ

RRRR AAAA=1k=1k=1k=1k

ΩΩΩΩ

C

apac

itanc

e(uF

)C

apac

itanc

e(uF

)C

apac

itanc

e(uF

)C

apac

itanc

e(uF

)

Time Delay(s)Time Delay(s)Time Delay(s)Time Delay(s)

Figure 1. Monoatable CircuitFigure 1. Monoatable CircuitFigure 1. Monoatable CircuitFigure 1. Monoatable Circuit Figure 2. Resistance and Capacitance vs.Figure 2. Resistance and Capacitance vs.Figure 2. Resistance and Capacitance vs.Figure 2. Resistance and Capacitance vs. Time delay(tTime delay(tTime delay(tTime delay(tdddd))))

Figure 3. Waveforms of Monostable OperationFigure 3. Waveforms of Monostable OperationFigure 3. Waveforms of Monostable OperationFigure 3. Waveforms of Monostable Operation

1

5

6

7

84

2

3

RESET VccDISCH

THRES

CONTGND

OUT

TRIG

+Vcc

RA

C1

C2RL

Trigger

LM555/NE555/SA555

5555

Figure 1 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor C1 and setting the flip-flop output at the same time. The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t=RA*C and reaches 2Vcc/3 at td=1.1RA*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant RAC, the longer it takes for the VC1 to reach 2Vcc/3. In other words, the time constant RAC controls the output pulse width. When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop, turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low.In this way, the timer operating in the monostable repeats the above process. Figure 2 shows the time constant relationship based on RA and C. Figure 3 shows the general waveforms during the monostable operation. It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at the end of the output pulse remains at below Vcc/3. Figure 4 shows such a timer output abnormality.

2. Astable Operation2. Astable Operation2. Astable Operation2. Astable Operation

Figure 4. Waveforms of Monostable Operation (abnormal)Figure 4. Waveforms of Monostable Operation (abnormal)Figure 4. Waveforms of Monostable Operation (abnormal)Figure 4. Waveforms of Monostable Operation (abnormal)

100m100m100m100m 1111 10101010 100100100100 1k1k1k1k 10k10k10k10k 100k100k100k100k1E-31E-31E-31E-3

0.010.010.010.01

0.10.10.10.1

1111

10101010

100100100100

10M10M10M10M

ΩΩΩΩ

1M1M1M1MΩΩΩΩ

100k100k100k100kΩΩΩΩ

10k10k10k10kΩΩΩΩ

1k1k1k1kΩΩΩΩ

(R(R(R(R AAAA+2R+2R+2R+2R BBBB))))

Cap

acita

nce(

uF)

Cap

acita

nce(

uF)

Cap

acita

nce(

uF)

Cap

acita

nce(

uF)

Fr equency(Hz)Frequency(Hz)Frequency(Hz)Frequency(Hz)

Figure 5. Astable CircuitFigure 5. Astable CircuitFigure 5. Astable CircuitFigure 5. Astable Circuit Figure 6. Capacitance and Resistance vs. FrequencyFigure 6. Capacitance and Resistance vs. FrequencyFigure 6. Capacitance and Resistance vs. FrequencyFigure 6. Capacitance and Resistance vs. Frequency

1

5

6

7

84

2

3

RESET VccDISCH

THRES

CONTGND

OUT

TRIG

+Vcc

RA

C1

C2RL

RB

LM555/NE555/SA555

6666

An astable timer operation is achieved by adding resistor RB to Figure 1 and configuring as shown on Figure 5. In the astable operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multi vibrator. When the timer output is high, its internal discharging Tr. turns off and the VC1 increases by exponential function with the time constant (RA+RB)*C. When the VC1, or the threshold voltage, reaches 2Vcc/3, the comparator output on the trigger terminal becomes high,resetting the F/F and causing the timer output to become low. This in turn turns on the discharging Tr. and the C1 discharges through the discharging channel formed by RB and the discharging Tr. When the VC1 falls below Vcc/3, the comparator output on the trigger terminal becomes high and the timer output becomes high again. The discharging Tr. turns off and the VC1 rises again. In the above process, the section where the timer output is high is the time it takes for the VC1 to rise from Vcc/3 to 2Vcc/3, and the section where the timer output is low is the time it takes for the VC1 to drop from 2Vcc/3 to Vcc/3. When timer output is high, the equivalent circuit for charging capacitor C1 is as follows:

Since the duration of the timer output high state(tH) is the amount of time it takes for the VC1(t) to reach 2Vcc/3,

Figure 7. Waveforms of Astable OperationFigure 7. Waveforms of Astable OperationFigure 7. Waveforms of Astable OperationFigure 7. Waveforms of Astable Operation

Vcc

RA RB

C1 Vc1(0-)=Vcc/3

C1dvc1

dt-------------

Vcc V 0-( )–

RA RB+-------------------------------= 1( )

VC1 0+( ) VCC 3⁄= 2( )

VC1 t( ) VCC 1 23---e

- tRA RB+( )C1

------------------------------------–

–

= 3( )

LM555/NE555/SA555

7777

The equivalent circuit for discharging capacitor C1, when timer output is low is, as follows:

Since the duration of the timer output low state(tL) is the amount of time it takes for the VC1(t) to reach Vcc/3,

Since RD is normally RB>>RD although related to the size of discharging Tr.,tL=0.693RBC1 (10)

Consequently, if the timer operates in astable, the period is the same with 'T=tH+tL=0.693(RA+RB)C1+0.693RBC1=0.693(RA+2RB)C1' because the period is the sum of the charge time and discharge time. And since frequency is the reciprocal of the period, the following applies.

3. Frequency divider3. Frequency divider3. Frequency divider3. Frequency dividerBy adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure 8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle.

VC1 t( ) 23---VCC V=

CC1 2

3---e

-tH

RA RB+( )C1------------------------------------–

–

= 4( )

tH C1 RA RB+( )In2 0.693 RA RB+( )C1== 5( )

C1

RB

RDVC1(0-)=2Vcc/3

C1dvC1

dt-------------- 1

RA RB+-----------------------VC1 0=+ 6( )

VC1 t( ) 23---V

CCe

- tRA RD+( )C1

-------------------------------------

= 7( )

13---VCC

23---V

CCe

-tL

RA RD+( )C1-------------------------------------

= 8( )

tL C1 RB RD+( )In2 0.693 RB RD+( )C1== 9( )

frequency, f 1T--- 1.44

RA 2RB+( )C1----------------------------------------= = 11( )

LM555/NE555/SA555

8888

4. Pulse Width Modulation4. Pulse Width Modulation4. Pulse Width Modulation4. Pulse Width ModulationThe timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the reference of the timer's internal comparators. Figure 9 illustrates the pulse width modulation circuit.When the continuous trigger pulse train is applied in the monostable mode, the timer output width is modulated according to the signal applied to the control terminal. Sine wave as well as other waveforms may be applied as a signal to the control terminal. Figure 10 shows the example of pulse width modulation waveform.

5. Pulse Position Modulation5. Pulse Position Modulation5. Pulse Position Modulation5. Pulse Position ModulationIf the modulating signal is applied to the control terminal while the timer is connected for the astable operation as in Figure 11, the timer becomes a pulse position modulator.In the pulse position modulator, the reference of the timer's internal comparators is modulated which in turn modulates the timer output according to the modulation signal applied to the control terminal.Figure 12 illustrates a sine wave for modulation signal and the resulting output pulse position modulation : however, any wave shape could be used.

Figure 8. Waveforms of Frequency Divider OperationFigure 8. Waveforms of Frequency Divider OperationFigure 8. Waveforms of Frequency Divider OperationFigure 8. Waveforms of Frequency Divider Operation

Figure 9. Circuit for Pulse Width ModulationFigure 9. Circuit for Pulse Width ModulationFigure 9. Circuit for Pulse Width ModulationFigure 9. Circuit for Pulse Width Modulation Figure 10. Waveforms of Pulse Width ModulationFigure 10. Waveforms of Pulse Width ModulationFigure 10. Waveforms of Pulse Width ModulationFigure 10. Waveforms of Pulse Width Modulation

84

7

1

2

3

5

6

CONTGND

Vcc

DISCH

THRES

RESET

TRIG

OUT

+Vcc+Vcc+Vcc+Vcc

TriggerTriggerTriggerTrigger

RRRRAAAA

CCCC

OutputOutputOutputOutputInputInputInputInput

LM555/NE555/SA555

9999

6. Linear Ramp6. Linear Ramp6. Linear Ramp6. Linear RampWhen the pull-up resistor RA in the monostable circuit shown in Figure 1 is replaced with constant current source, the VC1 increases linearly, generating a linear ramp. Figure 13 shows the linear ramp generating circuit and Figure 14 illustrates the generated linear ramp waveforms.

In Figure 13, current source is created by PNP transistor Q1 and resistor R1, R2, and RE.

For example, if Vcc=15V, RE=20kΩ, R1=5kW, R2=10kΩ, and VBE=0.7V, VE=0.7V+10V=10.7VIc=(15-10.7)/20k=0.215mA

84

7

1

2

3

5

6

CONTGND

Vcc

DISCH

THRES

RESET

TRIG

OUT

+Vcc+Vcc+Vcc+Vcc

RRRRAAAA

CCCC

RRRRBBBB

ModulationModulationModulationModulation

OutputOutputOutputOutput

Figure 11. Circuit for Pulse Position ModulationFigure 11. Circuit for Pulse Position ModulationFigure 11. Circuit for Pulse Position ModulationFigure 11. Circuit for Pulse Position Modulation Figure 12. Waveforms of pulse position modulationFigure 12. Waveforms of pulse position modulationFigure 12. Waveforms of pulse position modulationFigure 12. Waveforms of pulse position modulation

Figure 13. Circuit for Linear RampFigure 13. Circuit for Linear RampFigure 13. Circuit for Linear RampFigure 13. Circuit for Linear Ramp Figure 14. Waveforms of Linear RampFigure 14. Waveforms of Linear RampFigure 14. Waveforms of Linear RampFigure 14. Waveforms of Linear Ramp

1

5

6

7

84

2

3

RESET VccDISCH

THRES

CONTGND

OUT

TRIG

+Vcc

C2

R1

R2

C1

Q1

Output

RE

ICVCC VE–

RE---------------------------= 12( )

Here, VE is

VE VBE

R2R1 R2+----------------------VCC+= 13( )

LM555/NE555/SA555

10101010

When the trigger starts in a timer configured as shown in Figure 13, the current flowing through capacitor C1 becomes a constant current generated by PNP transistor and resistors. Hence, the VC is a linear ramp function as shown in Figure 14. The gradient S of the linear ramp function is defined as follows:

Here the Vp-p is the peak-to-peak voltage.If the electric charge amount accumulated in the capacitor is divided by the capacitance, the VC comes out as follows:

V=Q/C (15)

The above equation divided on both sides by T gives us

and may be simplified into the following equation.

S=I/C (17)

In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the constant current flowing through the capacitor. If the constant current flow through the capacitor is 0.215mA and the capacitance is 0.02µF, the gradient of the ramp function at both ends of the capacitor is S = 0.215m/0.022µ = 9.77V/ms.

SVp p–

T----------------= 14( )

VT---- Q T⁄

C------------= 16( )

LM555/NE555/SA555

11111111

Mechanical DimensionsMechanical DimensionsMechanical DimensionsMechanical Dimensions

PackagePackagePackagePackageDimensions in millimetersDimensions in millimetersDimensions in millimetersDimensions in millimeters

6.40 ±0.20

3.30 ±0.30

0.130 ±0.012

3.40 ±0.20

0.134 ±0.008

#1

#4 #5

#8

0.252 ±0.008

9.20

±0.

20

0.79

2.54

0.10

0

0.03

1(

)

0.46

±0.

10

0.01

8 ±0

.004

0.06

0 ±0

.004

1.52

4 ±0

.10

0.36

2 ±0

.008

9.60

0.37

8M

AX

5.080.200

0.330.013

7.62

0~15°

0.300

MAX

MIN

0.25+0.10–0.05

0.010+0.004–0.002

8-DIP8-DIP8-DIP8-DIP

LM555/NE555/SA555

12121212

Mechanical Dimensions Mechanical Dimensions Mechanical Dimensions Mechanical Dimensions (Continued)

PackagePackagePackagePackageDimensions in millimetersDimensions in millimetersDimensions in millimetersDimensions in millimeters

4.9

2 ±

0.2

0

0.1

94

±0.0

08

0.4

1 ±

0.1

0

0.0

16

±0.0

04

1.2

70

.05

0

5.720.225

1.55 ±0.20

0.061 ±0.008

0.1~0.250.004~0.001

6.00 ±0.30

0.236 ±0.012

3.95 ±0.20

0.156 ±0.008

0.50 ±0.20

0.020 ±0.008

5.1

30

.20

2M

AX

#1

#4 #5

0~8°

#8

0.5

60

.02

2(

)

1.800.071

MA

X0

.10

MA

X0

.00

4

MAX

MIN

+0.1

0-0

.05

0.1

5

+0.0

04

-0.0

02

0.0

06

8-SOP8-SOP8-SOP8-SOP

LM555/NE555/SA555

13131313

Ordering InformationOrdering InformationOrdering InformationOrdering InformationProduct NumberProduct NumberProduct NumberProduct Number PackagePackagePackagePackage Operating TemperatureOperating TemperatureOperating TemperatureOperating Temperature

LM555CN 8-DIP0 ~ +70°C

LM555CM 8-SOP

Product NumberProduct NumberProduct NumberProduct Number PackagePackagePackagePackage Operating TemperatureOperating TemperatureOperating TemperatureOperating Temperature

NE555N 8-DIP0 ~ +70°C

NE555D 8-SOP

Product NumberProduct NumberProduct NumberProduct Number PackagePackagePackagePackage Operating TemperatureOperating TemperatureOperating TemperatureOperating Temperature

SA555 8-DIP-40 ~ +85°C

SA555D 8-SOP

LM555/NE555/SA555LM555/NE555/SA555LM555/NE555/SA555LM555/NE555/SA555

11/29/02 0.0m 001Stock#DSxxxxxxxx

2002 Fairchild Semiconductor Corporation

LIFE SUPPORT POLICY LIFE SUPPORT POLICY LIFE SUPPORT POLICY LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

DISCLAIMER DISCLAIMER DISCLAIMER DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

Any and all SANYO products described or contained herein do not have specifications that can handleapplications that require extremely high levels of reliability, such as life-support systems, aircraft’scontrol systems, or other applications whose failure can be reasonably expected to result in seriousphysical and/or material damage. Consult with your SANYO representative nearest you before usingany SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values thatexceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or otherparameters) listed in products specifications of any and all SANYO products described or containedherein.

Monolithic Linear IC

6W 2-Channel, Bridge 19W typ Power Amplifier

Ordering number:ENN750F

LA4440

SANYO Electric Co.,Ltd. Semiconductor CompanyTOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

21500TH (KT)/90196RM/33194HO/8064KI/3233KI/O070KI, TS No.750–1/13

Package Dimensionsunit:mm

3023A-SIP14H

[LA4440]

SANYO : SIP14H

Features• Built-in 2 channels (dual) enabling use in stereo and bridge

amplifier applications.Dual : 6W×2 (typ.)Bridge : 19W (typ.)

• Minimun number of external parts required.• Small pop noise at the time of power supply ON/OFF and

good starting balance.• Good ripple rejection : 46dB (typ.)• Good channel separation.• Small residual noise (Rg=0).• Low distortion over a wide range from low frequencies to

high frequencies.• Easy to design radiator fin.• Built-in audio muting function.• Built-in protectors.

a. Thermal protectorb. Overvoltage, surge voltage protectorc. Pin-to-pin short protector

SpecificationsAbsolute Maximum Ratings at Ta = 25˚C

˚C

˚C

141

13.8

0.6

37.0

30.0

R1.

7

11.0

8.0

0.8m

in

6.0

15.0

max

1.99 2.54 1.40.4

4.5

2.25

retemaraP lobmyS snoitidnoC sgnitaR tinU

egatlovylppusmumixaMV CC 1xam )s03=t(tnecseiuQ 52 V

V CC 2xam gnitarepO 81 V

egatlovylppusegruS V CC )egrus( t≤ s2.0 05 V

noitapissidrewopelbawollA xamdP 51 W

ecnatsiserlamreT θ c-j esac-ot-noitcnuJ 3

erutarepmetgnitarepO rpoT 57+ot02–

erutarepmetegarotS gtsT 051+ot04–

˚C/W

Recommended Operating Conditions at Ta = 25˚C

Tc=75˚C, See Pd max – Ta characteristic

retemaraP lobmyS snoitidnoC sgnitaR tinU

egatlovylppuS V CC 2.31 V

ecnatsiserdaoL RLoeretS 8ot2 Ω

egdirB 8ot4 Ω

LA4440

No.750–2/13

Operating Characteristics at Ta = 25˚C, VCC=13.2V, RL=4Ω, f=1kHz, Rg=600Ω, with 100×100×1.5mm3 Al fin,

See specified Test Circuit.

retemaraP lobmyS snoitidnoCsgnitaR

tinUnim pyt xam

tnerructnecseiuQ occI 001 002 Am

niagegatloV GV 5.94 5.15 5.35 Bd

rewoptuptuO POoeretS,%01=DHT 0.5 0.6 W

egdirB,%01=DHT 91 W

noitrotsidcinomrahlatoT DHT PO W1= 1.0 0.1 %

ecnatsisertupnI ri k03 Ω

egatlovesiontuptuO V ON0=gR 6.0 0.1 Vm

k01=gR Ω 0.1 0.2 Vm

oitarnoitcejerelppiR Rr VR f,Vm002= R 0=gR,zH001= 64 Bd

noitarapeslennahC peshC VO k01=gR,mBd0= Ω 54 55 Bd

noitaunettagnituM TTA VO V,mBd0= M V9= 04 Bd

slennahcneewtebecnereffidniaG ∆ GV 2 Bd

Equivalent Circuit Block Diagram

LA4440

No.750–3/13

Sample Application Circuit 1. Stereo use

Sample Application Circuit 2. Bridge amplifier 1

LA4440

No.750–4/13

Sample Application Circuit 3. Bridge amplifier 2

Description of External PartsC1 (C2) · Feedback capacitor : The low cutoff frequency depends on this capacitor.

If the capacitance value is increased, the starting time is delayed.C3 (C4) · Bootstrap capacitor : If the capacitance value is decreased, the output at low frequencies goes lower.C5 (C6) · Oscillation preventing capacitor : Polyester film capacitor, being good in temperature characteristic,

frequency characteristic, is used.The capacitance value can be reduced to 0.047µF depending on the stability of the board.

C7 (C8) · Output capacitor : The low cutoff frequency depends on this capacitor.At the bridge amplifier mode, the output capacitor is generally connected.

C9 · Decoupling capacitor :Used for the ripple filter. Since the rejection effect is saturated at a certaincapacitance value, it is meaningless to increase the capacitance value more than required. This capaci-tor, being also used for the time constant of the muting circuit, affects the starting time.

R1 (R2) · Filter resistor for preventing oscillation.R3 (R4) · Resistor for making input signal of inverting amplifier in Voltage Gain Adjust at Bridge Amplifier

Mode (No. 1).R5 · Resistor for adjusting starting time in Voltage Gain Adjust at Bridge Amplifier Mode (No. 2)C10 · Capacitor for preventing oscillation in Voltage Gain Adjust at Bridge Amplifier Mode (No. 2)C11 · Power source capacitor.R6 (R7) · Used at bridge amplifier mode in order to increase discharge speed and to secure transient stability.

Feaures of IC System and Functions of Remaining Pins(a) Since the input circuit uses PNP transistors and the input potential is designed to be 0 bias, no input coupling

capacitor is required and direct coupling is available. However, when slider contact noise caused by the variableresistor presents a problem, connect an capacitor in series with the input.

(b) The open-loop voltage gain is lowered and the negative feedback amount is reduced for stabilization. An increasein distortion resulted from the reduced negative feedback amount is avoided by use of the built-in unique distor-tion reduction circuit, and thus distortion is kept at 0.1% (typ.).

(c) A capacitor for oscillation compensation is contained as a means of reducing the number of external parts. Thecapacitance value is 35pF which determines high cutoff frequency fH (–3dB point) of the amplifier (fH≈20kHz).

(d) For preventing the IC from being damaged by a surge applied on the power line, an overvoltage protector iscontained. Overvoltage setting is 25V. It is capable of withstanding up to 50V at giant pulse surge 200ms.

(e) No damege occurs even when power is applied at a state where pins 10, 11, and 12 are short-circuited with solderbridge, etc.

(f) To minimize the variations in voltage gain, feedback resistor RNF is contained and voltage gain (51.5dB) is fixed.

LA4440

No.750–5/13

Voltage Gain Adjust at Stereo Mode

RNF=50Ω (typ), Rf=20kΩ (typ)At RNF’=0 (recommended VG)

VG=20log (dB)

In case of using RNF’

VG=20log (dB)

VGRNF

RfRNF+RNF’

Voltage Gain Adjust at Bridge Amplifier Mode (No. 1)

· The bridge amplifier configuration is as shown left, inwhich ch1 and ch2 operate as noninverting amplifierand inverting amplifier respectively.The output of the noninverting amplifier divided byresistors R3, R4 is applied, as input, to the invertingamplifier.Since attenuation (R4/R3) of the non-inverting amplifieroutput and amplification factor (Rf/R4+RNF) of theinverting amplifier are fixed to be the same, signals ofthe same level and 180° out of phase with each othercan be obtained at output pins (12) and (10). The totalvoltage gain is apparently higher than that of thenoninverting amplifier by 6dB and is approximatelycalculated by the following formula.

VG=20log + 6dB

In case of reducing the voltage gain, RNF’ is connectedto the noninverting amplifier side only and the followingformula is used.

VG=20log + 6dB

VG=20log (dB)

where (RNF+RNF’) << R5

From this formula, it is seen that connecting RNF’causes the voltage gain to be reduced at the modes ofboth stereo amplifier and bridge amplifier.

RfRNF

Voltage Gain Adjust at Bridge Amplifier Mode (No. 2)

RfRNF+RNF’

RfRNF+RNF’

2

LA4440

No.750–6/13

(g) In case of applying audio muting in each application circuit, the following circuit is used.

6V≤VM≤VCCRecommended VM=9VATT=40dB (Rg=600Ω)

Flow-in current IO is calculated by the following formula.

IO=

In case of increasing the muting attenuation, resistor 5.6kΩ is connected in series with the input, and then theattenuation is made to be 55dB. Be careful that connecting an input capacitor causes pop noise to be increased atthe time of application of AC muting. Increased RO, CO make it possible to reduce the noise. In case of com-pletely cutting off power IC, pin (5) is grounded, and then DC control is available and the attenuation is made tobe ∞.

VM – VBERO

Stereo : 20Ω≤R≤100ΩBridge No.1 : 20Ω≤R≤100ΩBridge No. 2 : 0Ω≤R≤50Ω

Pin Voltage (unit : V)

.oNniP 1 2 3 4 5 6 7 8 9 01 11 21 31 41

nipnoitcnuF 1HCFN

1HCFN

erPDNG

CAoiduAgnituM

CD 2HCNI

2HCFN

2HCrewoP

DNG

2HCSB

2HCTUO V CC

1HCTUO

1HCSB

1HCrewoP

DNG

taegatloVniPedomtnecseiuq 4.1 30.0 0 0 0.31 30.0 4.1 0 9.11 8.6 2.31 8.6 9.11 0

Proper Cares in Using IC· Maximum ratingsIf the IC is used in the vicinity of the maximum ratings, even a slight variation in conditions may cause the maximumratings to be exceeded, thereby leading to breakdown. Allow an ample margin of variation for supply voltage, etc. anduse the IC in the range where the maximum ratings are not exceeded.

· Printed circuit boardWhen making the board, refer to the sample printed circuit pattern and be careful that no feedback loop is formedbetween input and output.

· Oscillation preventing capacitorNormally, a polyester film capacitor is used for 0.1µF + 4.7Ω. The capacitance value can be reduced to 0.047µF depend-ing on the stability of the board.

· OthersConnect the radiator fin of the package to GND.

LA4440

No.750–7/13

Characteristics at stereo amplifier mode

LA4440

No.750–8/13

LA4440

No.750–9/13

Characteristics at bridge amplifier mode No. 1

LA4440

No.750–10/13

LA4440

No.750–11/13

Characteristics at bridge amplifier mode No. 2

LA4440

No.750–12/13

Proper Cares in Mounging Radiator Fin1. The mounting torque is in the range of 39 to 59N · cm.2. The distance between screw holes of the radiator fin must coincide with the distance between screw holes of the IC.

With case outline dimensions L and R referred to, the screws must be tightened with the distance between them asclose to each other as possible.

3. The screw to be used must have a head equivalent to the one of truss machine screw or binder machine screw definedby JIS. Washers must be also used to protect the IC case.

4. No foreign matter such as cutting particles shall exist between heat sink and radiator fin. When applying grease on thejunction surface, it must be applied uniformly on the whole surface.

5. IC lead pins are soldered to the printed circuit board after the radiator fin is mounted on the IC.

Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guaranteesof the performance, characteristics, and functions of the described products as mounted in the customer'sproducts or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and allsemiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,or that could cause damage to other property. When designing equipment, adopt safety measures sothat these kinds of accidents or events cannot occur. Such measures include but are not limited to protectivecircuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or al l SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations,such products must not be expor ted without obtaining the expor t l icense from the authorit iesconcerned in accordance with the above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic ormechanical, including photocopying and recording, or any information storage or retrieval system,or otherwise, without the prior written permission of SANYO Electric Co. , Ltd.

Any and all information described or contained herein are subject to change without notice due toproduct/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only ; it is notguaranteed for volume production. SANYO believes information herein is accurate and reliable, butno guarantees are made or implied regarding its use or any infringements of intellectual property rightsor other rights of third parties.

This catalog provides information as of February, 2000. Specifications and information herein are subject

to change without notice.

LA4440

PS No.750–13/13

TLC2932 Evaluation ModuleTechnical Reference

SLAU003AOctober 1997

Printed on Recycled Paper

IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductorproduct or service without notice, and advises its customers to obtain the latest version of relevant informationto verify, before placing orders, that the information being relied on is current.

TI warrants performance of its semiconductor products and related software to the specifications applicable atthe time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques areutilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of eachdevice is not necessarily performed, except those mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, orsevere property or environmental damage (“Critical Applications”).

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTEDTO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHERCRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TIproducts in such applications requires the written approval of an appropriate TI officer. Questions concerningpotential risk applications should be directed to TI through a local SC sales office.

In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards should be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance, customer product design, software performance, orinfringement of patents or services described herein. Nor does TI warrant or represent that any license, eitherexpress or implied, is granted under any patent right, copyright, mask work right, or other intellectual propertyright of TI covering or relating to any combination, machine, or process in which such semiconductor productsor services might be or are used.


Notational Conventions

iii Read This First

Preface

Read This First

About This Manual

The Texas Instruments (TI ) TLC2932 Evaluation Module TechnicalReference Manual for the TLC2932 high-performance phase-locked loopprovides information to assist managers and hardware/software engineers inapplication development.

How to Use This Manual

This document contains the following chapters:

Chapter 1 OverviewA general description of the TLC2932 Evaluation Module (TLC2932EVM), keyfeatures, and a functional overview are included.

Chapter 2 HardwareA general description of the TLC2932EVM hardware is included.

Appendix A TLC2932 Data SheetA copy of the TLC2932 data sheet is included.

Appendix B TC9122P Data Sheet SummaryA summary of the TC9122P data sheet is included.

Symbol Convention

This document uses the following convention:

TC TOSHIBA device number prefix

Information About Cautions and Warnings/Related Documentation From Texas Instruments

iv

Information About Cautions and Warnings

This book may contain cautions and warnings.

This is an example of a caution statement.

A caution statement describes a situation that could potentiallydamage your software or equipment.

This is an example of a warning statement.

A warning statement describes a situation that could potentiallycause harm to you .

The information in a caution or a warning is provided for your protection.Please read each caution and warning carefully.

Related Documentation From Texas Instruments

TLC2932 High-Performance Phase-Locked Loop Data Sheet ( literaturenumber SLAS097E) is included in Appendix A of this book. It containselectrical specifications, available temperature options, generaloverview of the device, and application information.

TLC2932 Phase-Locked Loop Building Block With AnalogVoltage-Controlled Oscillator and Phase Frequency DetectorApplication Report (literature number SLAA011B) contains anoverview of phase-locked loop functional blocks, transfer functionanalyses, evaluation module (EVM) board design, and performancecharacteristics.

Data Acquisition Circuits Data Book (literature number SLAD001) containsthe data sheets for devices that perform analog-to-digital,digital-to-analog, and related functions. It also has selection tables andpackage and ordering information.

FCC Warning

This equipment is intended for use in a laboratory test environment only. Itgenerates, uses, and can radiate radio frequency energy and has not beentested for compliance with the limits of computing devices pursuant to subpartJ of part 15 of FCC rules, which are designed to provide reasonable protectionagainst radio frequency interference. Operation of this equipment in otherenvironments may cause interference with radio communications, in whichcase the user at his own expense will be required to take whatever measuresmay be required to correct this interference.

If You Need Assistance

v Read This First

Trademarks

TI is a trademark of Texas Instruments Incorporated.

TOSHIBA is a trademark of TOSHIBA AMERICA, Inc.

If You Need Assistance. . .

If you want to. . . Do this. . .

Request more information aboutTexas Instruments Mixed SignalProducts (MSP)

Call the Product Information Center (PIC)hotline:(214) 644–5580

Or send a fax to the PIC:(214) 480–7800

Or write to:Texas Instruments IncorporatedProduct Information Center, MS 3123P.O. Box 660246Dallas, Texas 75266

Order Texas Instrumentsdocumentation

Call the PIC hotline:(214) 644–5580

Ask questions about productoperation or report suspectedproblems

Call the PIC hotline:(214) 644–5580

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Running Title—Attribute Reference

vii Chapter Title—Attribute Reference

Contents

1 Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Introduction 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 TLC2932EVM Operating Specifications 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Evaluation of the Clock Synthesizer 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.1 Calculation of the LPF C and R Values 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 Evaluation Board Output Waveform 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.3 Using an Active Filter as the LPF 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Operation Notes 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Hardware 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Board Schematic 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Power, Ground, and Capacitor Connections 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Board Layout 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Board Layers 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Part Descriptions 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A TLC2932 Data Sheet A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1 TLC2932 Data Sheet A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B TC9122P Data Sheet Summary B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1 Reference Information for the TC9122P Programmable Counter B-2. . . . . . . . . . . . . . . . . . B.2 Device Connections B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3 Terminal Functions B-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.4 Absolute Maximum Ratings, TA = 25°C B-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.5 Electrical Characteristics at VDD = 7.5 V, TA = 25°C B-4. . . . . . . . . . . . . . . . . . . . . . . . . . . .


viii

Figures

1–1 TLC2932EVM Block Diagram 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 TLC2932EVM Block Diagram With the Given Conditions Set 1-4. . . . . . . . . . . . . . . . . . . . . . . 1–3 VCO Characteristic Curve 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Input Frequencies and VCO Output Waveform 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 TLC2932EVM Board Schematic 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 VDD and GND Line Connections and Bypass Capacitors 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 TLC2932EVM Board Layout 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Layer 1 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Layer 2 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 Layer 3 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 Layer 4 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1 TC9122P Connections B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

1–1 Supply Voltage Operating Specifications 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Part Descriptions 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1 TC9122P Terminal Functions B-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–2 TC9122P Absolute Maximum Ratings B-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–3 TC9122P Electrical Characteristics B-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1 Chapter Title—Attribute Reference

Overview

The TLC2932 evaluation module (TLC2932EVM) provides a method toevaluate the performance of the TLC2932 phase-locked-loop (PLL) buildingblock. The TLC2932EVM contains a phase frequency detector (PFD) and avoltage-controlled oscillator (VCO). This manual explains how to constructbasic frequency synthesis circuits including the design of a low-pass filter(LPF). This chapter includes the following topics:

Topic Page

1.1 Introduction 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 TLC2932EVM Operating Specifications 1-3. . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Evaluation of the Clock Synthesizer 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Operation Notes 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 1

Introduction

1-2

1.1 Introduction

The TLC2932EVM for the TLC2932IPW Texas Instruments CMOSphase-locked loop (PLL) integrated circuit (IC) contains a TLC2932IPW, twoTC9122P programmable counters, a loop filter, and other devices, as shownin Figure 1–1. These devices comprise a clock synthesizer on the module toevaluate basic PLL functionality and performance. The general externalconnections of the TLC2932EVM are shown in Figure 1–2.

The TLC2932EVM includes the following:

A reference frequency is generated by the crystal (XTAL) oscillator andsupplied to PFD input through the programmable counter. An external ref-erence (F–ref in) can be input through the Baby N Connector (BNC).

The 14.31818-MHz XTAL oscillator on the EVM is a standard part. It canbe replaced by any other XTAL oscillator with an oscillation frequency inthe functional range of the TC9122P programmable counter.

A lag-lead filter standard connection is available on the board. For moreflexible filter design, a free area beside the socket of TLC2932IPW isprovided.

Dip switches on the board are used to set the TC9122P programmablecounter and can be used to set the N/M counter as a frequencysynthesizer.

Figure 1–1. TLC2932EVM Block Diagram

ProgrammableCounterTC9122P

XTAL Oscillator14.31818 MHz

Selector

S3–S5

ProgrammableCounterTC9122P

Prescalar74AC11074

1/2 1/2

TLC2932IPW

Low-PassFilter

DVDD 5 VAVDD 5 V

AGND DGND

Output

U1 U2 U6

U3/U4 U5

F–ref in

TLC2932EVM Operating Specifications

1-3 Overview

1.2 TLC2932EVM Operating Specifications

If the on-board XTAL oscillator supplied with the EVM is used, DVDD shouldbe adjusted to 5.5 V instead of 5 V nominal because of the improvedperformance of the TC9122P counter at the higher DVDD.

Table 1–1 lists the supply voltage operating specifications.

Table 1–1.Supply Voltage Operating Specifications

Clock Generator UsedDVDD

(nominal) (V)AVDD

(nominal) (V)

On-board oscillator with TC9122Pprogrammable counter

5.5 5

Externally applied reference frequency atF–ref in

5 5

Evaluation of the Clock Synthesizer

1-4

1.3 Evaluation of the Clock Synthesizer

This section includes a typical evaluation using the TLC2932EVM. The PLLblock [voltage-controlled oscillator (VCO), phase frequency detector (PFD),low-pass filter (LPF), and counter] parameters of this evaluation include thefollowing:

VCO: R1 = 2.2 kΩ as RBIAS, lock frequency = 14.31818 MHz

PFD: Comparison frequency = fREF = 15.734 kHz, 14.31818-MHz XTAL oscillator as reference

LPF: Lag-lead filter C and R values are calculated in the followingsection

Counter: N/M = 455/910, 1/2 divide prescalar (P = 2)

Figure 1–2 shows a block diagram of the TLC2932EVM with the given conditions set.

Figure 1–2. TLC2932EVM Block Diagram With the Given Conditions Set

DGND

DGND

DVDD

AVDDDVDD

LOGIC VDD

LOGIC GND NC

VCO GND

VCO IN

BIAS

VCO VDD

R3

C1R2C2

S1

S2

S3

0.022 µF

+

–

0.022 µF

10 µF

R1 = 2.2 kΩ

Low-Pass Filter

47 kΩ

AGND

SELECT

VCO OUT

FIN-A

FIN-B

PFD OUT

VCO INHIBIT

PFD INHIBIT

+

–

0.022 µF

10 µF

ProgrammableCounter (1/M)

ProgrammableCounter (1/N)

fREF

XTALOscillator

Prescalar(1/P)

fosc = 14.31818 MHz

DGND

M = 910

N = 455P = 2

Programmable Counter – TC9122PPre-Scalar – 74AC11074 × 2

S1, S2: ONS3: OFF (SELECT = H)

TLC2932


1-5 Overview

1.3.1 Calculation of the LPF C and R Values

This section examines the calculations used to derive the C and R values forthe lag-lead filter. The design parameters selected for this example include thefollowing:

VCO range: Selected from the VCO characteristic curvebelow (see Figure 1–3)

Lock up time: ts = 1 ms

P N count: 910

Damping factor: ζ = 0.7

Selected radians to lock-up time: ωnts = 4.5 rad

Natural angular frequency: ωn = ωnts/ts = 4500 rad/sec (1)

Figure 1–3. VCO Characteristic Curve

20

15

5

00 1 2 3

– O

scill

atio

n F

requ

ency

– M

Hz

25

35

VCO IN – Control Voltage – V

Oscillation Frequency vs Control Voltage40

4 5

10

30

VDD = 5 VRBIAS = 2.2 kΩSELECT = HTA = 25°C

osc

f

In the case of the lag-lead filter, ωn and ζ are calculated according to thefollowing equations:

n (Kp Kv)(P N) (T1 T2) (2)

n2 T2 N(Kp Kv) (3)(T1 R2 C1, T2 R3 C1)

PFD gain

Kp 0.32 V/radVOH – VOL

4π= (4)

where VOH and VOL are obtained from the data sheet

VCO gain from Figure 1–3

(5)Kv (32 12)MHz 106(4 1)V 2

41.9 MradVsec


1-6

The R2 and R3 values for the LPF are calculated according to the followingequations:

R2 Kp Kvn2 1(P N) 2n N(Kp Kv)C1

R3 2n N(Kp Kv)C1 (7)

(6)

When C1 is set to 1 µF, the R2 and R3 calculated values are:

R2 = 470 Ω , R3 = 240 Ω

Capacitor C2 is added to minimize high-frequency pickup at the VCO input,and the C2 value should be set equal to or smaller than C1 ⋅ 1/10 to have aminimal effect on the LPF poles, hence:

C2 = 0.1 µF is selected for this application.

1.3.2 Evaluation Board Output Waveform

Figure 1–4 shows the input frequencies and the VCO output waveform usingthe C and R values calculated in the previous section.

Figure 1–4. Input Frequencies and VCO Output Waveform

100-ns/div

5 V

/div

FIN–A

FIN–B

VCO OUT

TA = 25°C,VDD = 5 V,RBIAS (R1) = 2.2 kΩ ,

Low-Pass Filter:R2 = 470 Ω ,R3 = 240 Ω ,C1 = 1 µF,C2 = 0.1 µF

0 V

0 V

0 V

1.3.3 Using an Active Filter as the LPF

For active filtering on the EVM, space is available to build the filter using anoperational amplifier. Note the inverted output of the filter; this inverted outputcan be compensated for by changing the JP2 connections of 1 to 4, 2 to 3(normally 1 to 2, 3 to 4 for lag-lead filter).

To find the best C and R values for each application, some evaluation may berequired. The LPF characteristics resulting from standard values of R and Ccan cause the PLL performance to be slightly different from theoretical results.

Operation Notes

1-7 Overview

1.4 Operation Notes

When an external reference frequency is input through the J1 connector,an R7 resistor should be inserted as termination.

The VCO output should drive only one external device to avoid overload.

Because this evaluation board has a high-frequency VCO functionalblock, it requires the closest connection and shortest possible lead-in ofeach I/O to optimize board performance.

The supply voltage for this board should be 5 V or as specified inSection 1.2, TLC2932EVM Operating Specifications, as determined bythe peripheral IC supply voltage requirements, because the TLC2932IPWcan use both 5 V and 3 V.

For details of the 74AC11074 prescalar on this board, see the TI CMOSData Book.

For a description of the programmable counter functions, see the generalreference information included in this document from the TOSHIBATC9122P data sheet.

A bypass capacitor for the BIAS terminal should be used for anyapplication and placed as close as possible to terminal 13. This capacitoris included on the TLC2932EVM and designated as C17.

2-1 Chapter Title—Attribute Reference

Hardware

This chapter includes the following topics:

Topic Page

2.1 Board Schematic 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Power, Ground, and Capacitor Connections 2-4. . . . . . . . . . . . . . . . . . . . .

2.3 Board Layout 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Board Layers 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Part Descriptions 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2

Board Schematic

2-2

2.1 Board Schematic

The TLC2932EVM board schematic is shown in Figure 2–1.

Board Schematic

2-3Hardware

12

34

56

78

910

1112

2423

2221

2019

1817

1615

1413

1413

1211

109

87

65

43

1614

B3A3

D3C3B2A2D1C1B1A1

D0C0B0A0

INO

UT

GND

VCC

U2

TC

9122

P

DV

DD

172

8O

SC

GN

D

V CC

12

34

56

78

910

1112

2423

2221

2019

1817

1615

1413

1413

1211

109

87

65

43

1614

B3A3

D3C3B2A2D1C1B1A1

D0C0B0A0

INO

UT

GND

VCCU

2T

C91

22P

DV

DD

172

DV

DD

V CC

V DD

1 3

2 4

JP3

DV

DD

1 2

R7

51 (Opt

iona

l)

14

Q

CLK

13Q

DP

R CL

14

2 3

DV

DD

DV

DD121

Q

CLK

9Q

DP

R CL

8

6 5

DV

DD

DV

DD121

U3A

74A

C11

074

U3B

74A

C11

074

621 3 5

4

JP3

Q

CLK

13Q

DP

R CL

14

2 3

DV

DD

DV

DD121

Q

CLK

9Q

DP

R CL

8

5

DV

DD

DV

DD121

U4A

74A

C11

074

U4B

74A

C11

074

6

1 3

2 4

JP2

LOG

IC V

CC

SE

LEC

T

VC

O O

UT

FIN

–A

FIN

–B

PF

D O

UT

DG

ND

VC

O V

DD

BIA

S

VC

O IN

VC

O G

ND

VC

O IN

HIB

PF

D IN

HIB

U6

TLC

2932

181

181

1 2 3 4 5 6 7

14 13 12 11 10 9

TP

11T

P1

11

TP

13T

P3

J2

J11

R1

2.2

k ΩJ1

2

1 2C

17.0

221 J3 1 2

C2

2.1

J4 1

1 1 2 1J5 J6R2

470TP

4 1 11

J7

R3

240

21

J8

1 2 11 J9 J10

C1

2.1

uF

1T

P5

1T

P5

1 2 3

6 5 4

2 1

2 1

R6 47

kΩ

R5

47 k

Ω

2 1

R4

47 k

Ω

DV

DD

2 4

TB

1

DV

DD

5 V

GN

D

2 4

TB

2

AV

DD

5 V

GN

D

1 2

1 2Fµ

10C

3

C4

0.1

1 2

C6

0.1

1 2Fµ

10C

5 +1 2

C8

0.1

1 2Fµ

10C

7 +1 2

C10 0.1

1 2Fµ

10C

9 +1 2

C12 0.1

1 2Fµ

10C

11 +1 2

C14 0.1

1 2Fµ

10C

13 +1 2

C16

0.02

2

1 2Fµ

10C

15 +AV

DD

DV

DD

DV

DDS

2

1 1

TP

2

TP

12

S1

7

Fig

ure

2–1.

TLC

2932

EV

M B

oard

Sch

emat

ic

Power, Ground, and Capacitor Connections/Board Layout

2-4

2.2 Power, Ground, and Capacitor Connections

The power, ground, and capacitor connections of the TLC2932EVM areshown in Figure 2–2.

Figure 2–2. VDD and GND Line Connections and Bypass Capacitors

U1+

–

C3 C4U2

+

–

C5 C6U3

+

–

C7 C8U4

+

–

C9 C10U5

+

–

C11 C12

U6+

–

C16+

–

C13 C14 C15

1

4

1

18

11

4

1, 7, 10, 12

11

4

1, 7, 10, 12

1

18

C3, C5, C7, C9, C11, C13, C15 = 10 µFC4, C6, C8, C10, C12, C14, C16, C17 = 0.022 µF

1

7

14

11

+

–

DVDD

DGND

AVDD

AGND

C17

13

2.3 Board Layout

The TLC2932EVM board layout is shown in Figure 2–3.

Board Layout

2-5Hardware

J1:F

–RE

F IN

R7

TLC

2932

EV

MG

ND

TP

5G

ND

TP

4

J1:F

–VC

O O

UT

TP

3

GN

DLO

GO

+C

5

C6

U2

1/M

10 101

102

S2

JP1

12

34

TB

1T

B1

GN

DA

VD

DG

ND

DV

DD

U1

+

TE

XA

S IN

ST

RU

ME

NT

SP

HA

SE

-LO

CK

ED

LO

OP

C3

C8

+ C7

R1

C1

C2

R2

R3

C17

C16

U6

C14

+

C15

C13

+R

6R

5

R4

C10

+

C9

SW

1V

CO

INH

PF

D IN

HV

CO

Fre

q

JP2

1 3

2 4

1 3

2 45

6

JP3

+C

11

U4

U3

U5

C12

S2

10101

1021/N

GN

DT

P2

GN

DT

P1

MS

N:

Fig

ure

2–3.

TLC

2932

EV

M B

oard

Lay

out

Board Layers

2-6

2.4 Board Layers

Figure 2–4. Layer 1


Board Layers

2-7 Hardware



Part Descriptions

2-8

2.5 Part Descriptions

The TLC2932EVM parts are listed in Table 2–1.

Table 2–1.Part Descriptions

Number Quantity Reference Description

1 1 C1 1-µF ceramic capacitor, 0.2-inch LS, (AVXSR30C105KAA or equivalent)

2 1 C2 0.1-µF ceramic capacitor, 0.2-inch LS, (AVXSR215C104KAA or equivalent)

3 7 C3, C5, C7, C9 C11, C13,C15

10-µF 16-V aluminum capacitors

4 5 C4, C6, C8, C10, C12 0.1-µF ceramic capacitors,0.2 inch LS, radial lead (AVX SR21C104KAA orequivalent)

5 3 C14, C16, C17 0.022-µF capacitors, X7R, 1206 SMT

6 1 JP1 Header 2 x 2

7 1 JP3 Header 3 x 2

8 2 J1, J2 BNC connectors, PCB mount, RT angle

9 10 J3, J4, J5, J6, J7, J8, J9,J10, J11, J12

Pin sockets

10 1 R1 2.2 kΩ, 5%, 1/4 W resistor

11 1 R2 470 Ω, 5%, 1/4 W resistor

12 1 R3 240 Ω, 5%, 1/4 W resistor

13 3 R4, R5, R6 47 kΩ, 5%, 1/4 W resistors

14 2 S1, S2 12-position DIP switch

15 1 S3 3-position DIP switch

16 2 (JP1, JP3) Shorting plug, header pin

17 2 TB1, TB2 Term block, screw terminal

18 10 TP1, TP2, TP3, TP4, TP5,TP11, TP12, TP13, TP14,

TP15

Terminal, test point

19 1 U1 XTAL oscillator 14.31818 MHz

20 2 U2, U5 TC9122 programmable counter

21 2 U3, U4 74AC11074 prescalar

22 1 U6 TLC2932 PLL functional block

23 2 [JP2] (1–2, 3–4) Bus wire, #24

24 1 PC board


A-1 Chapter Title—Attribute Reference

TLC2932 Data Sheet

This appendix presents a copy of the TLC2932 data sheet.

Appendix A

TLC2932I Data Sheet

A-2

A.1 TLC2932 Data Sheet

TLC2932IHIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997

A-3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Voltage-Controlled Oscillator (VCO)Section:– Complete Oscillator Using Only One

External Bias Resistor (R BIAS)– Lock Frequency:

22 MHz to 50 MHz (VDD = 5 V ±5%,TA = –20°C to 75°C, ×1 Output)11 MHz to 25 MHz (VDD = 5 V ±5%,TA = –20°C to 75°C, ×1/2 Output)

– Output Frequenc y . . . ×1 and ×1/2Selectable

Phase-Frequency Detector (PFD) SectionIncludes a High-Speed Edge-TriggeredDetector With Internal Charge Pump

Independent VCO, PFD Power-Down Mode

Thin Small-Outline Package (14 terminal)

CMOS Technology

Typical Applications:– Frequency Synthesis– Modulation/Demodulation– Fractional Frequency Division

Application Report Available †

CMOS Input Logic Level

description

The TLC2932I is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlledoscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency rangeof the VCO is set by an external bias resistor (RBIAS). The VCO has a 1/2 frequency divider at the output stage.The high-speed PFD with internal charge pump detects the phase difference between the reference frequencyinput and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions,which can be used as a power-down mode. The TLC2932I is suitable for use as a high-performance PLL dueto the high speed and stable oscillation capability of the device.

functional block diagram

PhaseFrequencyDetector

4

5

9

6FIN–A

FIN–B

PFD INHIBIT

PFD OUT

Voltage-ControlledOscillator

12

13

103

VCO IN

BIAS

VCO INHIBITVCO OUT

2SELECT

AVAILABLE OPTIONS

PACKAGE

TA SMALL OUTLINE(PW)

–20°C to 75°C TLC2932IPWLE

Copyright 1997, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

† TLC2932 Phase-Locked-Loop Building Block With Analog Voltage-Controlled Oscillator and Phase Frequency Detector (SLAA011).

1

2

3

4

5

6

7

14

13

12

11

10

9

8

LOGIC VDDSELECT

VCO OUTFIN–AFIN–B

PFD OUTLOGIC GND

VCO VDDBIASVCO INVCO GNDVCO INHIBITPFD INHIBITNC

PW PACKAGE †

(TOP VIEW)

NC – No internal connection

† Available in tape and reel only and ordered as theTLC2932IPWLE.



A-4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINALI/O DESCRIPTION

NAME NO.I/O DESCRIPTION

FIN–A 4 I Input reference frequency f(REF IN) is applied to FIN–A.

FIN–B 5 I Input for VCO external counter output frequency f(FIN–B). FIN–B is nominally provided from the externalcounter.

LOGIC GND 7 GND for the internal logic.

LOGIC VDD 1 Power supply for the internal logic. This power supply should be separate from VCO VDD to reducecross-coupling between supplies.

NC 8 No internal connection.

PFD INHIBIT 9 I PFD inhibit control. When PFD INHIBIT is high, PFD output is in the high-impedance state, see Table 3.

PFD OUT 6 O PFD output. When the PFD INHIBIT is high, PFD output is in the high-impedance state.

BIAS 13 I Bias supply. An external resistor (RBIAS) between VCO VDD and BIAS supplies bias for adjusting theoscillation frequency range.

SELECT 2 I VCO output frequency select. When SELECT is high, the VCO output frequency is ×1/2 and when low, theoutput frequency is ×1, see Table 1.

VCO IN 12 I VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCOoscillation frequency.

VCO INHIBIT 10 I VCO inhibit control. When VCO INHIBIT is high, VCO OUT is low (see Table 2).

VCO GND 11 GND for VCO.

VCO OUT 3 O VCO output. When the VCO INHIBIT is high, VCO output is low.

VCO VDD 14 Power supply for VCO. This power supply should be separated from LOGIC VDD to reduce cross-couplingbetween supplies.

detailed description

VCO oscillation frequency

The VCO oscillation frequency is determined by an external resistor (RBIAS) connected between the VCO VDDand the BIAS terminals. The oscillation frequency and range depends on this resistor value. The bias resistorvalue for the minimum temperature coefficient is nominally 3.3 kΩ with 3-V at the VCO VDD terminal andnominally 2.2 kΩ with 5-V at the VCO VDD terminal. For the lock frequency range refer to the recommendedoperating conditions. Figure 1 shows the typical frequency variation and VCO control voltage.

VCO Oscillation Frequency Range

Bias Resistor (R BIAS)

1/2 VDDVCO Control Voltage (VCO IN)

VC

O O

scill

atio

n F

requ

ency

(f

)os

c

Figure 1. VCO Oscillation Frequency




VCO output frequency 1/2 divider

The TLC2932I SELECT terminal sets the fosc or 1/2 fosc VCO output frequency as shown in Table 1. The 1/2fosc output should be used for minimum VCO output jitter.

Table 1. VCO Output 1/2 Divider Function

SELECT VCO OUTPUT

Low fosc

High 1/2 fosc

VCO inhibit function

The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCOINHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level duringthe power-down mode, refer to Table 2.

Table 2. VCO Inhibit Function

VCO INHIBIT VCO OSCILLATOR VCO OUTPUT IDD(VCO)Low Active Active Normal

High Stopped Low level Power Down

PFD operation

The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phasedifference between two frequency inputs supplied to FIN–A and FIN–B as shown in Figure 2. Nominally thereference is supplied to FIN–A, and the frequency from the external counter output is fed to FIN–B.

FIN–A

FIN–B

PFD OUT

VOH

Hi-Z

VOL

Figure 2. PFD Function Timing Chart

PFD output control

A high level on the PFD INHIBIT terminal places the PFD output in the high-impedance state and the PFD stopsphase detection as shown in Table 3. A high level on the PFD INHIBIT terminal also can be used as thepower-down mode for the PFD.

Table 3. VCO Output Control Function

PFD INHIBIT DETECTION PFD OUTPUT IDD(PFD)Low Active Active Normal

High Stopped Hi-Z Power Down




schematics

VCO block schematic

BiasControl

VCOOutput

1/2

RBIAS

VCO IN

VCO INHIBIT

VCO OUT

SELECT

BIAS

MUX

PFD block schematic

Detector

Charge Pump

PFD OUT

FIN–A

FIN–B

PFD INHIBIT

VDD

absolute maximum ratings †

Supply voltage (each supply), VDD (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range (each input), VI (see Note 1) –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input current (each input), II ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output current (each output), IO ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total power dissipation, at (or below) TA = 25°C (see Note 2) 700 mW. . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range, TA –20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to network GND.2. For operation above 25°C free-air temperature, derate linearly at the rate of 5.6 mW/°C.




recommended operating conditions

PARAMETER MIN NOM MAX UNIT

Supply voltage V (each supply see Note 3)VDD = 3 V 2.85 3 3.15

VSupply voltage, VDD (each supply, see Note 3)VDD = 5 V 4.75 5 5.25

V

Input voltage, VI (inputs except VCO IN) 0 VDD V

Output current, IO (each output) 0 ±2 mA

VCO control voltage at VCO IN 0.9 VDD V

Lock frequency (×1 output)VDD = 3 V 14 21

MHzLock frequency (×1 output)VDD = 5 V 22 50

MHz

Lock frequency (×1/2 output)VDD = 3 V 7 10.5

MHzLock frequency (×1/2 output)VDD = 5 V 11 25

MHz

Bias resistor RBIASVDD = 3 V 2.2 3.3 4.3

kΩBias resistor, RBIAS VDD = 5 V 1.5 2.2 3.3kΩ

NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) should be at the same voltageand separated from each other.

electrical characteristics over recommended operating free-air temperature range, V DD = 3 V(unless otherwise noted)

VCO sectionPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOH High-level output voltage IOH = –2 mA 2.4 V

VOL Low-level output voltage IOL = 2 mA 0.3 V

VIT Input threshold voltage at SELECT, VCO INHIBIT 0.9 1.5 2.1 V

II Input current at SELECT, VCO INHIBIT VI = VDD or GND ±1 µA

Zi(VCO IN) Input impedance VCO IN = 1/2 VDD 10 MΩ

IDD(INH) VCO supply current (inhibit) See Note 4 0.01 1 µA

IDD(VCO) VCO supply current See Note 5 5 15 mA

NOTES: 4. Current into VCO VDD, when VCO INHIBIT = VDD, PFD is inhibited.5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kΩ, VCO INHIBIT = GND, and PFD is inhibited.

PFD sectionPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOH High-level output voltage IOH = –2 mA 2.7 V


IOZ High-impedance-state output currentPFD INHIBIT = high,VI = VDD or GND

±1 µA

VIH High-level input voltage at FIN–A, FIN–B 2.7 V

VIL Low-level input voltage at FIN–A, FIN–B 0.5 V

VIT Input threshold voltage at PFD INHIBIT 0.9 1.5 2.1 V

Ci Input capacitance at FIN–A, FIN–B 5 pF

Zi Input impedance at FIN–A, FIN–B 10 MΩ

IDD(Z) High-impedance-state PFD supply current See Note 6 0.01 1 µA

IDD(PFD) PFD supply current See Note 7 0.1 1.5 mA

NOTES: 6. Current into LOGIC VDD, when FIN–A, FIN–B = GND, PFD INHIBIT = VDD, no load, and VCO OUT is inhibited.7. Current into LOGIC VDD, when FIN–A, FIN–B = 1 MHz (VI(PP) = 3 V, rectangular wave), NC = GND, no load, and VCO OUT is

inhibited.




operating characteristics over recommended operating free-air temperature range, V DD = 3 V(unless otherwise noted)


fosc Operating oscillation frequency RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD 15 19 23 MHz

ts(fosc) Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ 10 µs

t Rise timeCL = 15 pF, See Figure 3 7 14

nstr Rise timeCL = 50 pF, See Figure 3 14

ns

t Fall timeCL = 15 pF, See Figure 3 6 12

nstf Fall timeCL = 50 pF, See Figure 3 10

ns

Duty cycle at VCO OUT RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD, 45% 50% 55%

α(fosc) Temperature coefficient of oscillation frequencyRBIAS = 3.3 kΩ, VCO IN = 1/2 VDD,TA = –20°C to 75°C 0.04 %/°C

kSVS(fosc) Supply voltage coefficient of oscillation frequencyRBIAS = 3.3 kΩ, VCO IN = 1.5 V,VDD = 2.85 V to 3.15 V

0.02 %/mV

Jitter absolute (see Note 9) RBIAS = 3.3 kΩ 100 ps

NOTES: 8. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.9. The low-pass-filter (LPF) circuit is shown in Figure 28 with calculated values listed in Table 7. Jitter performance is highly dependent

on circuit layout and external device characteristics. The jitter specification was made with a carefully designed PCB with no devicesocket.


fmax Maximum operating frequency 20 MHz

tPLZ PFD output disable time from low level 21 50ns

tPHZ PFD output disable time from high levelSee Figures 4 and 5 and Table 4

23 50ns

tPZL PFD output enable time to low levelSee Figures 4 and 5 and Table 4

11 30ns

tPZH PFD output enable time to high level 10 30ns

tr Rise timeCL = 15 pF See Figure 4

2.3 10 ns

tf Fall timeCL = 15 pF, See Figure 4

2.1 10 ns




electrical characteristics over recommended operating free-air temperature range, V DD = 5 V(unless otherwise noted)


VOH High-level output voltage IOH = –2 mA 4 V


VIT Input threshold voltage at SELECT, VCO INHIBIT 1.5 2.5 3.5 V

II Input current at SELECT, VCO INHIBIT VI = VDD or GND ±1 µA

Zi(VCO IN) Input impedance VCO IN = 1/2 VDD 10 MΩ

IDD(INH) VCO supply current (inhibit) See Note 4 0.01 1 µA

IDD(VCO) VCO supply current See Note 5 15 35 mA

NOTES: 4. Current into VCO VDD, when VCO INHIBIT = VDD, and PFD is inhibited.5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kΩ, VCO INHIBIT = GND, and PFD is inhibited.


VOH High-level output voltage IOH = 2 mA 4.5 V


IOZ High-impedance-state output currentPFD INHIBIT = high,VI = VDD or GND

±1 µA

VIH High-level input voltage at FIN–A, FIN–B 4.5 V

VIL Low-level input voltage at FIN–A, FIN–B 1 V

VIT Input threshold voltage at PFD INHIBIT 1.5 2.5 3.5 V

Ci Input capacitance at FIN–A, FIN–B 5 pF

Zi Input impedance at FIN–A, FIN–B 10 MΩ

IDD(Z) High-impedance-state PFD supply current See Note 6 0.01 1 µA

IDD(PFD) PFD supply current See Note 7 0.15 3 mA

NOTES: 6. Current into LOGIC VDD, when FIN–A, FIN–B = GND, PFD INHIBIT = VDD, no load, and VCO OUT is inhibited.7. Current into LOGIC VDD, when FIN–A, FIN–B = 1 MHz (VI(PP) = 5 V, rectangular wave), PFD INHIBIT = GND, no load, and

VCO OUT is inhibited.




operating characteristics over recommended operating free-air temperature range, V DD = 5 V(unless otherwise noted)


fosc Operating oscillation frequency RBIAS = 2.2 kΩ, VCO IN = 1/2 VDD 30 41 52 MHz

ts(fosc) Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ 10 µs

t Rise timeCL = 15 pF, See Figure 3 5.5 10

nstr Rise timeCL = 50 pF, See Figure 3 8

ns

t Fall timeCL = 15 pF, See Figure 3 5 10

nstf Fall timeCL = 50 pF, See Figure 3 6

ns

Duty cycle at VCO OUT RBIAS = 2.2 kΩ, VCO IN = 1/2 VDD, 45% 50% 55%

α(fosc) Temperature coefficient of oscillation frequencyRBIAS = 2.2 kΩ, VCO IN = 1/2 VDD,TA = –20°C to 75°C 0.06 %/°C

kSVS(fosc) Supply voltage coefficient of oscillation frequencyRBIAS = 2.2 kΩ, VCO IN = 2.5 V,VDD = 4.75 V to 5.25 V

0.006 %/mV

Jitter absolute (see Note 9) RBIAS = 2.2 kΩ 100 ps

NOTES: 8: The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.9. The LPF circuit is shown in Figure 28 with calculated values listed in Table 7. Jitter performance is highly dependent on circuit layout

and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.


fmax Maximum operating frequency 40 MHz

tPLZ PFD output disable time from low level 21 40ns

tPHZ PFD output disable time from high levelSee Figures 4 and 5 and Table 4

20 40ns

tPZL PFD output enable time to low levelSee Figures 4 and 5 and Table 4

7.3 20ns

tPZH PFD output enable time to high level 6.5 20ns

tr Rise timeCL = 15 pF See Figure 4

2.3 10 ns

tf Fall timeCL = 15 pF, See Figure 4

1.7 10 ns




PARAMETER MEASUREMENT INFORMATION

tr tf

90%

10%

90%

10%VCO OUT

Figure 3. VCO Output Voltage Waveform

50%

90%10% 10%

50%

50%

tPHZtr tftPLZ

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

VDD

GND

FIN–A†

FIN–B†

PFD INHIBIT

PFD OUT

(a) OUTPUT PULLDOWN(see Figure 5 and Table 4)

(b) OUTPUT PULLUP(see Figure 5 and Table 4)

† FIN–A and FIN–B are for reference phase only, not for timing.

90%

tPZLtPZH

GND

VOH50%50% 50%

VDD

VOL

Figure 4. PFD Output Voltage Waveform

Table 4. PFD Output Test Conditions

PARAMETER RL CL S1 S2tPZHtPHZ Open Close

tr1 kΩ 15 pF

O en Close

tPZL1 kΩ 15 pF

tPLZ Close Open

tf

Close O en

S1

S2

RL

CL

Test Point

PFD OUTDUT

VDD

Figure 5. PFD Output Test Conditions




TYPICAL CHARACTERISTICS

Figure 6

10

0

40

20

0 1 2 3

30

VCO OSCILLATION FREQUENCYvs

VCO CONTROL VOLTAGE

VCO IN – VCO Control Voltage – V

VDD = 3 VRBIAS = 2.2 kΩ –20°C

25°C

75°C

– V

CO

Osc

illat

ion

Fre

quen

cy –

MH

zf o

sc

Figure 7

60

40

0 1 2 3

80


VCO CONTROL VOLTAGE100

4 5

20


–20°C

25°C

75°C

VDD = 5 VRBIAS = 1.5 kΩ

– V

CO

Osc

illat

ion

Fre

quen

cy –

MH

zf o

sc

Figure 8

10

0

40

20

0 1 2 3

30


VCO CONTROL VOLTAGE



25°C

75°C

–20°C

– V

CO

Osc

illat

ion

Fre

quen

cy –

MH

zf o

sc

Figure 9

40

00 1 2 3

80

4 5

20

60


VCO CONTROL VOLTAGE


25°C

75°C


–20°C

– V

CO

Osc

illat

ion

Fre

quen

cy –

MH

zf o

sc





Figure 10

10

0

40

20

0 1 2 3

30


VCO CONTROL VOLTAGE


–20°C

25°C

75°C


– V

CO

Osc

illat

ion

Fre

quen

cy –

MH

zf o

sc

Figure 11

40

00 1 2 3

80

4 5

20

60


VCO CONTROL VOLTAGE


–20°C

25°C

75°C


– V

CO

Osc

illat

ion

Fre

quen

cy –

MH

zf o

sc

Figure 12

20

15

10

30

25

2 2.5 3.5 4 4.5

– V

CO

Osc

illat

ion

Fre

quen

cy –

MH

z


BIAS RESISTOR

VDD = 3 VVCO IN = 1/2 VDDTA = 25°C

f osc

RBIAS – Bias Resistor – k Ω3

Figure 13

40

30

20

60

50

1.5 2 2.5 3.5

– V

CO

Osc

illat

ion

Fre

quen

cy –

MH

z


BIAS RESISTOR

VDD = 5 VVCO IN = 1/2 VDDTA = 25°C

f osc

RBIAS – Bias Resistor – k Ω3





Figure 14

0.2

0.1

2 2.5 3.3

0.3

TEMPERATURE COEFFICIENT OFOSCILLATION FREQUENCY

vsBIAS RESISTOR

0.4

4 4.5

C°–

Tem

pera

ture

Coe

ffici

ent o

f Osc

illat

ion

RBIAS – Bias Resistor – k Ω

Fre

quen

cy –

% /

VDD = 3 VVCO IN = 1/2 VDDTA = –20°C to 75°C

3 3.5

(fos

c)α 0

Figure 15

0.2

0.1

1.5 2.2

0.3

TEMPERATURE COEFFICIENT OFOSCILLATION FREQUENCY

vsBIAS RESISTOR

0.4

3.5RBIAS – Bias Resistor – k Ω

VDD = 5 VVCO IN = 1/2 VDDTA = –20°C to 75°C

2 2.5 3

C°–

Tem

pera

ture

Coe

ffici

ent o

f Osc

illat

ion

Fre

quen

cy –

% /

(fos

c)α

0

Figure 16

20

18

163.05 3

22


VCO SUPPLY VOLTAGE

24

3.15VDD – VCO Supply Voltage – V

RBIAS = 3.3 kΩVCO IN = 1.5 VTA = 25°C

– V

CO

Osc

illat

ion

Fre

quen

cy –

MH

zf o

sc

Figure 17

40

36

324.75 5

44


VCO SUPPLY VOLTAGE

48

5.25VDD – VCO Supply Voltage – V

RBIAS = 2.2 kΩVCO IN = 1/2 VDDTA = 25°C

– V

CO

Osc

illat

ion

Fre

quen

cy –

MH

zf o

sc





Figure 18

0.03

0.02

0.01

2 2.5 3.5 4

0.04

SUPPLY VOLTAGE COEFFICIENT OF VCOOSCILLATION FREQUENCY

vsBIAS RESISTOR

0.05


VDD = 2.85 V to 3.15 VVCO IN = 1/2 VDDTA = 25°C

3

V

– S

uppl

y V

olta

ge C

oeffi

cien

t of V

CO

Osc

illat

ion

Fre

quen

cy –

% /

(fos

c)α

0

Figure 19

0.005

1.5 2.5 3

0.01


SUPPLY VOLTAGE COEFFICIENT OF VCOOSCILLATION FREQUENCY

vsBIAS RESISTOR

VDD = 4.75 V to 5.25 VVCO IN = 1/2 VDDTA = 25°C

2

V

– S

uppl

y V

olta

ge C

oeffi

cien

t of V

CO

Osc

illat

ion

Fre

quen

cy –

% /

(fos

c)α

0

Figure 20

20

15

10

30

25

2 2.5 3.5 4 4.5

Rec

omm

ende

d Lo

ck F

requ

ency

– M

Hz

RECOMMENDED LOCK FREQUENCY(×1 OUTPUT)

vsBIAS RESISTOR


VDD = 2.85 V to 3.15 VTA = –20°C to 75°C

3

Figure 21

40

30

20

101.5 2 2.5

50

60


Rec

omm

ende

d Lo

ck F

requ

ency

– M

Hz

RECOMMENDED LOCK FREQUENCY(×1 OUTPUT)

vsBIAS RESISTOR

VDD = 4.75 V to 5.25 VTA = –20°C to 75°C

3




APPLICATION INFORMATION

Figure 22

Rec

omm

ende

d Lo

ck F

requ

ency

– M

Hz

RECOMMENDED LOCK FREQUENCY(×1/2 OUTPUT)

vsBIAS RESISTOR


10

7.5

5

15

12.5

2 2.5 3.5 4 4.53

VDD = 2.85 V to 3.15 VTA = –20°C to 75°CSELECT = VDD

Figure 23


Rec

omm

ende

d Lo

ck F

requ

ency

– M

Hz

RECOMMENDED LOCK FREQUENCY(×1/2 OUTPUT)

vsBIAS RESISTOR

20

15

10

51.5 2 2.5

25

30

3.53

VDD = 4.75 V to 5.25 VTA = –20°C to 75°CSELECT = VDD





gain of VCO and PFD

Figure 24 is a block diagram of the PLL. Thecountdown N value depends on the inputfrequency and the desired VCO output frequencyaccording to the system application requirements.The Kp and KV values are obtained from theoperating characteristics of the device as shownin Figure 24. Kp is defined from the phase detectorVOL and VOH specifications and the equationshown in Figure 24(b). KV is defined fromFigures 8, 9, 10, and 11 as shown in Figure 24(c).

The parameters for the block diagram with theunits are as follows:

KV : VCO gain (rad/s/V)Kp : PFD gain (V/rad)Kf : LPF gain (V/V)KN : count down divider gain (1/N)

external counter

When a large N counter is required by theapplication, there is a possibility that the PLLresponse becomes slow due to the counterresponse delay time. In the case of a highfrequency application, the counter delay timeshould be accounted for in the overall PLL design.

RBIAS

The external bias resistor sets the VCO center frequency with 1/2 VDD applied to the VCO IN terminal. However,for optimum temperature performance, a resistor value of 3.3 kΩ with a 3-V supply and a resistor value of 2.5kΩ for a 5-V supply is recommended. For the most accurate results, a metal-film resistor is the better choicebut a carbon-compositiion resistor can be used with excellent results also. A 0.22 µF capacitor should beconnected from the BIAS terminal to ground as close to the device terminals as possible.

hold-in range

From the technical literature, the maximum hold-in range for an input frequency step for the three types of filterconfigurations shown in Figure 25 is as follows:

H 0.8 Kp KV Kf ()

WhereKf (∞) = the filter transfer function value at ω = ∞

Divider(KN = 1/N)

PFD(Kp)

VCO(KV)

LPF(Kf)

TLC2932

f REF

VOH

fMAX

fMIN

VIN MIN VIN MAX

–2π 2π–π 0 π

Range of Comparison

VOH

VOL

Kp =VOH – VOL

4π KV =2π(fMAX – fMIN)

VIN MAX – VIN MIN

Figure 24. Example of a PLL Block Diagram

(a)

(c)(b)





low-pass-filter (LPF) configurations

Many excellent references are available that include detailed design information about LPFs and should beconsulted for additional information. Lag-lead filters or active filters are often used. Examples of LPFs are shownin Figure 25. When the active filter of Figure 25(c) is used, the reference should be applied to FIN-B becauseof the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at the VCOinput. The value of C2 should be equal to or less than one tenth the value of C1.

R1

C1T1 = C1R1

(a) LAG FILTER

R1

C1

T1 = C1R1T2 = C1R2

R2

(b) LAG-LEAD FILTER

R2 C1

R1T1 = C1R1T2 = C1R2

(c) ACTIVE FILTER

A–

VI VOVI VO

VI

C2

VO

C2

Figure 25. LPF Examples for PLL

the passive filter

The transfer function for the lag-lead filter shown in Figure 25(b) is;

VOVIN

1 s T21 s (T1 T2)

WhereT1 R1 C1 and T2 R2 C1

Using this filter makes the closed loop PLL system a second-order type 1 system. The response curves of thissystem to a unit step are shown in Figure 26.

the active filter

When using the active integrator shown in Figure 25(c), the phase detector inputs must be reversed since theintegrator adds an additional inversion. Therefore, the input reference frequency should be applied to the FIN-Bterminal and the output of the VCO divider should be applied to the input reference terminal, FIN-A.

The transfer function for the active filter shown in Figure 25(c) is:

F(s) 1 s R2 C1s R1 C1

Using this filter makes the closed loop PLL system a second-order type 2 system. The response curves of thissystem to a unit step are shown in Figure 27.

basic design example

The following design example presupposes that the input reference frequency and the required frequency ofthe VCO are within the respective ranges of the device.





basic design example (continued)

Assume the loop has to have a 100 µs settling time (ts) with a countdown N = 8. Using the Type 1, second orderresponse curves of Figure 26, a value of 4.5 radians is selected for ωnts with a damping factor of 0.7. Thisselection gives a good combination for settling time, accuracy, and loop gain margin. The initial parameters aresummarized in Table 5. The loop constants, KV and Kp, are calculated from the data sheet specifications andTable 6 shows these values.

The natural loop frequency is calculated as follows:

nts 4.5

Then

n 4.5

100 s 45 k-radianssec

Since

Table 5. Design Parameters

PARAMETER SYMBOL VALUE UNITS

Division factor N 8

Lockup time t 100 µs

Radian value to selected lockup time ωnt 4.5 rad

Damping factor ζ 0.7

Table 6. Device Specifications


VCO gain 76.6 Mrad/V/s

fMAX 70 MHz

fMIN KV 20 MHz

VIN MAX

KV5 V

VIN MIN 0.9 V

PFD gain Kp 0.342357 V/rad

Table 7. Calculated Values


Natural angular frequency ωn 45000 rad/sec

K = (KV • Kp)/N 3.277 Mrad/sec

Lag-lead filterCalculated valueNearest standard value

R11587016000

Ω

Calculated valueNearest standard value

R2308300

Ω

Selected value C1 0.1 µF





Using the low-pass filter in Figure 25(b) and divider ratio N, the transfer function for phase and frequency areshown in equations 1 and 2. Note that the transfer function for phase differs from the transfer function forfrequency by only the divider value N. The difference arises from the fact that the feedback for phase is unitywhile the feedback for frequency is 1/N.

Hence, transfer function of Figure 24 (a) for phase is

2(s)1(s)

Kp KV

N (T1 T2)

1 s T2

s2 s 1 KpKV T2

N(T1T2) KpKV

N(T1T2)

(1)

and the transfer function for frequency is

FOUT(s)FREF(s)

Kp KV

(T1 T2)

1 s T2

s2 s1 KpKVT2

N(T1T2) KpKV

N(T1T2)

(2)

The standard two-pole denominator is D = s2 + 2 ζ ωn s + ωn2 and comparing the coefficients of the denominatorof equation 1 and 2 with the standard two-pole denominator gives the following results.

n Kp KV

N (T1 T2)

Solving for T1 + T2

T1 T2 Kp KVN 2

n

(3)

and by using this value for T1 + T2 in equation 3 the damping factor is

n2 T2 N

Kp KV

solving for T2

T2 2 – N

Kp KV

then by substituting for T2 in equation 3

T1 KV Kp

N 2n

–2 n

NKp KV





From the circuit constants and the initial design parameters then

R2 2 n

NKp KV

1C1

R1 Kp Kv

2n N

2 n

NKp KV

1

C1

The capacitor, C1, is usually chosen between 1 µF and 0.1 µF to allow for reasonable resistor values andphysical capacitor size. In this example, C1 is chosen to be 0.1 µF and the corresponding R1 and R2 calculatedvalues are listed in Table 7.





1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

00 1 2 3 4 5 6 7 8 9 10 11 12 13

ωnt

(t),

Nor

mal

ized

Res

pons

eφ 2

= 0.1

= 0.2

= 0.3

= 0.4

= 0.5 = 0.6

= 0.7

= 0.8

= 1.0

= 1.5

= 2.0

ωnts = 4.5

Figure 26. Type 1 Second-Order Step Response





1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

00 1 2 3 4 5 6 7 8 9 10 11 12 13

ωnt

(t),

Nor

mal

ized

Out

put F

requ

ency

φ 0

ζ = 0.8

ζ = 0.1

ζ = 0.2

ζ = 0.3

ζ = 0.4

ζ = 0.5

ζ = 0.6

ζ = 0.7

ζ = 1.0

ζ = 2.0

Figure 27. Type 2 Second-Order Step Response





1/2 fosc

PhaseComparator

AGND

DGND

DGND

DGND

REF IN

DVDD

AVDDVDD

LOGIC VDD (Digital)

LOGIC GND (Digital)

SELECT

FIN–A

VCO INHIBIT

PFD INHIBIT

NC

VCO GND

VCO IN

BIAS

VCO VDD

VCO

R1†

R3

C1R2C2

R4 R5 R6

S3

S4

S5

DivideByN

0.22 µF

1

2

3

4

5

6

7

14

13

12

11

10

9

8

FIN–B

† RBIAS resistor

VCO OUT

PFD OUT

Figure 28. Evaluation and Operation Schematic

PCB layout considerations

The TLC2932I contains a high frequency analog oscillator; therefore, very careful breadboarding andprinted-circuit-board (PCB) layout is required for evaluation.

The following design recommendations benefit the TLC2932I user:

External analog and digital circuitry should be physically separated and shielded as much as possible toreduce system noise.

RF breadboarding or RF PCB techniques should be used throughout the evaluation and productionprocess.

Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductanceand resistance. The ground plane is the better choice for noise reduction.

LOGIC VDD and VCO VDD should be separate PCB traces and connected to the best filtered supply pointavailable in the system to minimize supply cross-coupling.

VCO VDD to GND and LOGIC VDD to GND should be decoupled with a 0.1-µF capacitor placed as closeas possible to the appropriate device terminals.

The no-connection (NC) terminal on the package should be connected to GND.




MECHANICAL DATAPW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040064/B 10/94

14 PIN SHOWN

Seating Plane

0,10 MIN1,20 MAX

1

A

7

14

0,17

4,704,30

8

6,106,70

0,32

0,700,40

0,25

Gage Plane

0,15 NOM

0,65 M0,13

0°–8°

0,10

PINS **

A MIN

A MAX

DIM

2,90

3,30

8

4,90

5,30

14

6,80

6,404,90

5,30

16

7,70

20

8,10

24

9,60

10,00

28

NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.


B-1 Chapter Title—Attribute Reference

TC9122P Data Sheet Summary

This appendix presents a summary of the TC9122P data sheet.

Topic Page

B.1 Reference Information for the TC9122P Programmable Counter B-2. .

B.2 Device Connections B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.3 Terminal Functions B-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.4 Absolute Maximum Ratings, T A = 25C B-3. . . . . . . . . . . . . . . . . . . . . . . . .

B.5 Electrical Characteristics at V DD = 7.5 V, TA = 25C B-4. . . . . . . . . . . . . .

Appendix B

Reference Information for the TC9122P Programmable Counter

B-2

B.1 Reference Information for the TC9122P Programmable Counter

The device connections, terminal functions, absolute maximum ratings, andelectrical characteristics reference data included in this document is from theTOSHIBA TC9122P data sheet.

B.2 Device Connections

The connections of the TC9122P are shown in Figure B–1.

Figure B–1.TC9122P Connections

5 V

N = 103 102 101 100

16 15 14 13 12 11 10 9 8 7 6 5 4 3

B3 A3 D2 C2 A2D1 C1 B1 A1 D0 C0 B0 A0B217 2

OUT IN

18 1

5 V

TC9122P

Terminal Functions

B-3 TC9122P Data Sheet Summary

B.3 Terminal Functions

The TC9122P terminal functions are shown in Table B–1.

Table B–1.TC9122P Terminal Functions

TerminalNo.

Name Description Notes

2 INProgrammable counter input. As this input has the self-biased amplifierinternally, input frequency can be a small signal by capacitive couplingthe input.

Internalamplifier

3–6 A0–D0 100

Program input to set divide value N by BCD. N can be set from 8 to 3999.The values below must not be set.

Eachterminal3–6 A0–D0 100

A0 B0 C0 D0 A1 B1 C1 D1 A2 B2 C2 D2 A3 B3

te ahas apull-down

7–10 A1–D1 101 10

01

00

00

00

00

00

00

00

00

00

00

00

00

pull-downresistorinternally.

11–14 A2–D2 102101

100

011

000

000

000

000

000

000

000

000

000

000

000

15, 16 A3, B3 103

101

011

111

000

000

000

000

000

000

000

000

000

000

000

17 OUTProgrammable counter output. 1/N of the IN frequency appears at thisoutput.

1, 18VDD,GND

Power supply and ground.

B.4 Absolute Maximum Ratings, T A = 25°C

The TC9122P absolute maximum ratings at TA = 25°C are shown inTable B–2.

Table B–2.TC9122P Absolute Maximum Ratings

Supply voltage range, VDD –0.3 V to 10 V

Input voltage range, VI –0.3 V to VCC + 0.3 V

Operating temperature range, TA –30°C to 75°C

Storage temperature range, Tstg –55°C to 125°C

Electrical Characteristics

B-4

B.5 Electrical Characteristics at V DD = 7.5 V, TA = 25°C

The TC9122P electrical characteristics are shown in Table B–3.

Table B–3.TC9122P Electrical Characteristics

Parameter Test Conditions Min Typ Max Unit

VDD Supply voltage 4.5 8.5 V

VI(PP) Input voltage swing fI = 15 MHz, VI = 2 Vp-p 2 7 Vp-p

IDD Supply current 15 30 mA

VIH High-level input voltage 5.5 VDD+0.3 V

VIL Low-level input voltage –0.3 2 V

VOH High-level output voltage IOH = –0.5 mA 6.5 V

VOL Low-level output voltage IOL = 0.5 mA 1 V

f Operating frequency (see Note 1) 1 15 MHz

RIN Input pulldown resistor 20 80 kΩ

Rf Amplifier feedback resistor 100 500 kΩ

NOTE 1: VDD = 7.5 V ±10%, VI(PP) = 2 Vp-p, TA = 30°C to 75°C

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