ECE 1201 BJT Transistors

8/9/2019 ECE 1201 BJT Transistors

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Semiconductor Devices 2005

VII-1I. Shih

[2] Modes of operation

Bipolar Junction Transistors

[1] Structure and function of a BJT

[3] Current components and gainof the BJT

Part I

I. Shih

First reported in 1948 by Bardeen, Bra

Semiconductor

Emitter Collector

Base

Bipolar Junction Transistor


VII-3I. Shih

Emitter Base Collector

+ V EC -E C

B

E

B

C

Four regions of operation:

[1] Active region

V EB > 0, V CB < 0

[2] Saturation region

V EB > 0, V CB > 0

[3] Cutoff region

V EB < 0, V CB < 0

[4] Inverted active region

V EB < 0, V CB > 0

PNP


I. Shih

Narrow Base

Wide BaseP

P

Effect of base region width


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VII-5I. Shih

Base Basecontact Emitter Emitter contactCollector

Collector contact

Collector

Base

Top view

Cross-sectionalview

Effect of base region width on BJT:

I. Shih

Common Base

V EB

I E

Emitter-base junctionforward biased

Possible configurations of B

I E

I B

P N P

E B


VII-7I. Shih

E C

E F E i E V

qN B

-qN E

qN B

-qN C

)fieldelectric( P P

N

E-B and B-C junctions at zero bias

I. Shih

W E W

fielectric(

E-B and B-C junctions at ze


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VII-9I. Shih

)fieldelectric(

E C

E F

E V

E-B junction forward biased, B-C junctionreverse biased ( Active region )

I. Shih

I E

N DB N AE

x x

Assumptions: (1) One-dimensional d(2) W diffusion length of minority carriers.

Currents are due tomajority carriers inregions far away fromthe depletion region.

Current in a BJT:

J = J N (-x p) + J P( xn)

J P( x)

J N ( x)

holes electrons

J N/diff J N/drift

P

N

-x p xn

-x p xn

I. Shih

PCurrent in a Junction:Procedure to find I E and I C :

(1) Solve equation for p B( x)

(2) Apply BCs p B(0), p B(w) toevaluate C 1 and C 2

(3) Solve equation for n E (x)

(4) Apply BCs n E ( ) and n E (0) to evaluate C 1 and C 2

(5) Obtain I En and I Bp

J = J N (-x p) + J


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VII-13I. Shih

I B = I E - I C

Procedure to find I C :

(1) Solve equation for nC ( x)

(2) Apply BCs nC ( ) and n

C (0)

(3) Obtain I Ep and I Cn

Current in a Junction:

J = J N (-x p) + J P( xn)

N-base P-collector

I Cn(0) I Cp(w)

holeselectrons

J N/diff J N/drift

N

P

w 0

I. Shih

Procedure to find I E and I C :

0"0 "

)"0()0(

==

=

+=

x

E

E x

B

B

En Ep E

dx

nd

qADdx

pd

qAD

I I I

J = J N (-x p) + J



VII-15I. Shih

I B = I E - I C

0''

)'0()(

==

+

=

+=

x

E C

w x

B B

CnCpC

dxnd

qADdx pd

qAD

I w I I

J = J N (-x p) + J P( xn)

N-base P-collector

I Cn(0)

I Cp(w)

holeselectrons

J N/diff J N/drift

N

P

w 0


I. Shih

hoP

x

( )

( )

=

=

=

=

1exp'

1exp0'

1exp'

exp

kT qV

pw pkT

qV p p

kT qV

p p

kT qV

p p

CB Bo B

EB Bo B

Bo

B

Bo

B

jgq

jdiv

pt

p p

p

p

=+

=

'

PNP transistor:

Continuity equation:


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VII-17I. Shih

( )

+

=

w x

kT qV

pw x

kT qV

p x p CB Bo EB

Bo B 1exp11exp'

( ) ( ) [ ]==

=

=B

B p

B B

D x p

dx x pd

dx pd

0

'2

2

2

2

( ) B Ax x p B +=:Solution

( )( ) B Aww pw x

B p x

B

B

+==

==

at

00at

Base

w0

p B(0)

p B(w)

x

p B( x)

p Bo

For a transistor with w


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VII-21I. Shih

( ) ( )0

:BJTIdeal

2

2

=

=

=


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VII-25I. Shih

EnkT

qV

E E

E iC E B

CB EB Ep

kT qV

B

BiC

En EpkT

qV

B

B

E E

E i E

I e N L

DqAn I I I

kT qV

kT qV

I ewN D

qAn I

I I ewN D

N L D

qAn I

EB

EB

CB

===

==

+=+=

2

2

2

11

w

nCn(0)

0 0

n E (0) p B(0)

p B(w)

0 x x x

I E I C I B

Active region:

I. Shih

==

=

E E

E iC E B

C C

C iC

E E

E i E

N L D

qAn I I I

q N L

DqAn I

N L D

qAn I

2

2

2

Cutoff region:

0 0

n E (0) p B(0)

p B(w)

x

I E I B


VII-27I. Shih

==

>>


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VII-29I. Shih

B

C

B E

E E Bdc I

I w N D

L N D == =

=

kT qV

E

E Eo B

kT qV

B BoC

EB

EB

e L D

qAn I

ew

DqAp I

V EB

I C

V EC = 0

V EC > 3kT/q

V EC

I C Active+ V EB = 0 -

Saturation

Cutoff

I B= 0

Common Emitter

I. Shih

( ) ( ) RF F C E B RF F

kT qV

Bo BC

B B

C

CoC

R RF

EB

B

Bo B

E

Eo E E

I I I I

I I

D

qAew p D

qA I

w

n D

L

n DqA I I

kT qV

Ln D

Ln D

qA I

EB

+==

=

=

+==

+=

11

1

1

An equivalent circuit can be constru

Ebers-Moll Equations:


VII-31I. Shih

( ) ( ) R RF F B RF F C

R RF E

I I I

I I I

I I I

+=

=

=

11

Ebers-Moll equivalent CKT PNP:

Base

Collector

Emitter I E

I F

I R

I B

F I F

R I R

I C

I. Shih

( ) ( ) ( )

( ) ( ) +

=

=

=

B B

B

B

B

B

B

B B

B B

p L

xw p

Lw

x p

L x p

D x p

dx x pd

sinh0

sinh

1

22

2

( ) ( ) ( ) ( )00 B B B B p xww p p

x p +

=

In a practical PNP BJT:

I E = -------

I C = -------

++

+=

co

coth

2

2

N L D

N L D

qAn

N L D

N L D

qAn I

B B

B

C C

C i

B B

B

E E

E i B

Recombination in Base:


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VII-33I. Shih

I E I Ep

I En I B1 I B2 I B3

I Cn

I C I Cp

I B

I E =I Ep+I En I C =I Cp+I En

E C

E F

E V

Active region (PNP BJT)

I. Shih

If N A(emitter) >> N D(base) I E

Emitter Inputresistance: A10

V261 ===mm

I qkT

E

resistanceinputCollector

I C is independe

Large load resistor R L will not affect

Input resistance:


VII-35I. Shih

I E =I En+I Ep

I E I En

I Ep I B1 I B2 I B3

I Cp

I C I Cn

I B

Active region (NPN BJT)

E C

E F

E V

I. Shih

Inverted active

V CB

V EB

Active

Cutoff

Saturation

Inverted

O

I B

Possible configuration of B


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VII-37I. Shih


N+ N+

P+

N

P

Discrete P + NP transistor

N E ( x)

N B( x)

N C


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VII-41I. Shih

( )

+=

+

=

+

+==

En Ep

Ep

Ep

Cp

Ep

En Ep

Cp

Cn En Ep

CnCp

E

C dc

I I

I

I

I

I I I

I

I I I

I I

I I

1

1

0 0

1= T dc

DC Alpha: I E

I Ep

I En I B1 I B2 I B3

I Cn

I C I Cp

I B I E =I Ep+I En

I. Shih

dc

dc

E

C

E

C

C E

C

B

C dc

I I

I I

I I I

I I

=

=

==

11 Emitter

TraBase

I E I Ep

I En I B1 I B2 I B3

I B

DC Beta:


VII-43I. Shih

CBO E dcC

Cn E dcCn Ep

T

Cn EpT CnCpC

I I I

I I I I

I I I I I

+=

+=+=

+=+=

Collector-Base currentwith emitter open

Common Base:

I E I Ep

I En I B1 I B2 I B3

I Cn

I C I Cp

I B I E =I Ep+I En

I. Shih

[ ] [ ][ ]

CEO BdcC

CBOdc Bdc

CBOdc

Bdc

dcC

CBO BC dcC

I I I

I I

I I I

I I I I

+=

++=

+

=

++=

1

11

1

C

[ ] CBO BdcdcC I I I += 1

I E I Ep

I En I B1 I B2 I B3

I B

Common Emitter:


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SAC 01/05


Structure and principle of operation

A bipolar junction transistor consists of two back-to-back p-n junctions, that share a thin common regioncalled the base. If the base region is n-type, the transistor is a pnp. If the base is p-type, the transistor is annpn. Contacts are made to all three regions. The two outer regions called the emitter and the collector. Thestructure of an npn bipolar transistor is shown below. The device is called bipolar since its operationinvolves both types of mobile carriers, electrons and holes.

Figure 1

For an npn device, VBE

and VBC

are both positive in the normal operating mode, called forward active. Thatis, the base is put at a higher potential that the emitter or the collector. For example, one might ground thecollector, then bias the base at 5.0 V and the emitter at 4.3 V. The currents are defined as positive flowinginto the base and collector, and out of the emitter, for an npn. For a pnp device all of the biases and currentsare reversed. V BE and V BC are both negative in forward active. And the currents are defined as positiveflowing out of the base and the collector and into the emitter. In either case:

Eq. 1

The operation of the device is illustrated below for an npn. Only the first order effects for the forwardactive bias mode of operation are shown. The base-emitter junction has been forward biased and the base-collector junction has been reverse biased. Under these conditions, electrons diffuse from the emitter intothe base and holes diffuse from the base into the emitter. The bipolar device is constructed in such a waythat two important effects occur under these conditions. The first is that the emitter is normally doped witha much higher concentration of impurities than the base. As a result, when the emitter base junction isforward biased, many more electrons enter the base from the emitter than holes from the base entering theemitter. There is a strict ratio between these two currents. The number of electrons from the emitter is

Emitter Base Collector

VBE VBC


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SAC 01/05

proportional to the number of holes from the base. The second effect is that the base is physically narrow.This means that most of the electrons sent from the emitter find their way into the collector and constitutethe vast majority of the collector current. Most of the base current typically is injected into the emitter orrecombines with the electrons injected from the emitter.

Figure 2

The transport factor, , is defined as the ratio of the collector and emitter current:

Eq. 2

Using Kirchoffs current law, we show that the base current equals the difference between the emitter andcollector current. The current gain, , is defined as the ratio of the collector and base current. FromEquations 1 and 2 one can show that:

(5.2.15)

This explains how a bipolar junction transistor can provide current amplification. If the collector current isalmost equal to the emitter current, as is the case for most devices, the transport factor, , approaches one.The current gain, , can therefore become much larger than one. Thus a small base current can be used tomodulate (control) a much larger collector current. Finally it should be noted that and are not constants,but vary slightly with the bias conditions.

Emitter Base Collector Electron current fornpn transistor

Hole current for npn

transistor


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1

EE 216 Bipolar Transistor (Winter 2005) S araswat/Pease 1

I. Basic Structure and Band Diagrams

Basic bipolar transistor structure: Two pn junctions J 1 and J 2 areplaced back-to-back a distance W apart, forming an n-p-n structure.

The simple, idealized transistor shown below has doping densityof 10 16 cm -3 in the emitter and collector and 10 14 cm -3 in the base.

9-BIPOLAR JUNCTION TRANSISTOR (BJT)


Energy-band diagrams and electron-density for the

ideal transistor sketched on page 1 for the followingconditions:

(a) thermal equilibrium (zero bias)

(b) both junctions reverse-biased (cutoff mode)

(c) both junctions forward-biased (saturation mode)

(d) J 1 forward-biased and J 2 reverse-biased (activemode)

(a) Equilibrium (b) Cutoff

(c) Saturation(d) Active


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2


Current voltage characteristics


C

B

E

Structure and Model of Bipolar Transistor

Discrete pnp transistor

Symbol

Integrated circuit npn bipolar transistor

C

B

E

pnp npn


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3


Doping prole in a realistic IC npn transistor

N+ P N N+E C

holes for recombinationand injection into emitter

B

! 0.7 volts

e mostof the

e

XB

Collector is formed byepitaxy and base and emitterby ion implantation


N+ P NE C

B

X B

x

x

x

V

E c

E v

E F

Basic Operation in Forward Active Region

The E-B junction isforward biased andthe C-B junction isreverse biased


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5


J n = q nB n" x + qD nBdndx

=kT nB

pn

dpdx

+ qD nBdndx

=qD nB

pn

dpdx

+ pdndx

# $ %

& ' (

=qD nB

p

d pn( )dx

J n p

qDn B

dx

0

x B

" = d ( pn )0

x B

" = pn x B( ) # pn 0( )

In a modern ion implanted basetransistor, dp/dx 0, hence x 0. The direction of this eldaids electron ow from E to C,and retards electron ow fromC to E.

The electron ow between

emitter and collector is given by


From diode analysis, the pn products at the edge of thedepletion regions are given by

pn x = 0( ) = ni2eqV BE

/ kT

pn x B( ) = ni2eqV BC

/ kT

J n =qn i

2eqV BC

/ kT " eqV BE / kT [ ] p

DnBdx

0

x B #

I n = I s eqV BC / kT " eqV BE

/ kT [ ]Assuming D n is constant in the base

(2)

I s =q

2 Ani

2 DnB

Q B

(3)

where (4)


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6


Q B = q p dx0

x B " (5)

is called the base Gummel number.

(6)

A = E-B cross-sectional area

1. Only one of the two exponential terms is important inforward or reverse active bias region. When the deviceis in saturation, both junctions are forward biased andboth terms must be included.

2. The quantity

Which is the total undepleted charge in the base

Q B

q

= p dx0

x B " # N aB dx

0

x B "


I n = "qAni

2 DnB

N aB x BeqV BE

/ kT " eqV BC / kT ( )

= " q2

Ani2

DnBQ B

eqV BE / kT " eqV BC / kT ( ) (7)

Q B is the total integrated base charge (atoms/cm 2). Since I 1/ Q B, it is important to minimize Q B, i.e., use lowdoping levels in the base (this is a good strategy toachieve maximum dc current gain, but we will see thatthis does not work for high frequencies).

If the base is uniformly doped, = 0, Q B = q N aB x B


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7


A. Recombination in the Neutral Base Region

Some of the electrons traversing the base will recombine withmajority carrier holes. (This is usually unimportant in modernIC BJTs).

III. Current Gain

A number of factors can contribute to base current in a BJT.We consider them individually.NN +

n p

npopn opn

pn o

np


For simplicity if we assume that the base is uniformly doped so that x = 0,then the electron transport and the continuity equations are reduced to

DnBd 2 n pdx 2

"n p " n po

# nB

= 0

J n = q nB n" x + qD nBdndx

# qD nBdndx

As discussed in the case of the P-N junction, the general solution to theseequations is

where LnB = (D nB nB)1/2 = diffusion lengthThe appropriate boundary conditions are

n p " n po = K 1 e" x / LnB + K 2 e

x / LnB

n p x = 0( ) = n po eqV BE / kT = n i2

N aeqV BE / kT

n p x = X B( )" 0


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8


Excess Minority Carrier Proles for Different x B /L n Ratios

Most minority carriers make itacross the base if x B Ln

n p " n po eqV BE / kT # 1( )sinh x B # x( )/ LnB[ ]sinh x B / LnB( )

With these boundary conditions, the solution is

NN +n p

npo pnopnpn o

np


The emitter and collector electron currents are

(9)

(10)

The ratio of these two currents is dened as the basetransport factor .

I n E = I n x = 0( )=

qADnBn po LnB

eqV BE / kT " 1( )coth x B LnB

I nC = I n x = X B( ) =

qADnBn po LnB

eqV BE / kT " 1( )csch x B LnB

(11)" T = I

nC I nE

= sechx

B L nB


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9


(12)

In a typical modern BJT, x B 1 m and LnB 30 m so that

T 0.9994. T is NOT a limiting factor in current gain.

Using Eq. 9, 11 and 12 the base current due to T is

(13)

" T # 1 $1

2

x B2

L nB2

I B REC = I nE " I nC

= 1 " # T ( ) I n

$ qAni2

x B2 N aB % nBeqV BE

/kT " 1( )

In modern IC BJTs, x B > L PE x E


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10


The injected hole currents in each case come directly from

the analysis of the long and short base pn junction diodes.

(14)

(15)

(The subscript E is used to refer to emitter properties.)

The emitter injection efciency is dened as

(16)

I p E =qAni

2 D pE

N dE L pE eqV BE

/ kT " 1( )for x E >> L pE

I p E =qAni

2 D pE

N dE x E eqV BE

/ kT " 1( )for x E


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11


Summarizing our discussion of current gain,

(17)

In modern BJTs T is nearly 1 and is the main factorlimiting the performance.

(18)

By combining Eq. (12) and (16) and making appropriateapproximations it can be shown that

" F = I C I E

= I nC

I n E + I p E

= I nC I n E

I n E I n E

+ I p E = " T #

! = I C

I B

=

I C

I E " I C =

# F 1 " # F

" = D pE N aB x B DnB N dE L pE

+ 12

x B LnB

#

$ % &

' (

2)

* + +

,

- . .

/ 1

0 DnB N dE L pE D pE N aB x B

The main parameter to achieve high gain is the ratio of N dE /N aB


Deviations from the IdealBase Width Modulation

p Collect.

n+ Base

p+ Emit.

Constant base width,independent of V CB

VEB

V CB

IE

n+ Base

p Collect.

p+ Emit.

VEB

More depletion withVCB : smaller x B

IE

V CB

As V C increases, the reverse bias across the B-C increases, thedepletion region widens. Hence the neutral base width W resulting in an increase in thus and I C An extreme case of base width modulation is punch through


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12


Base Width Modulation: Early Voltage

is known as the Early voltage, which is a measure of how independent the basewidth x B is from V CB . Small | V A| means large base width modulation.

I C = I S eqV BE / kT ! 1( ) 1 + V CE

V A

"

# $

%

& ' (19)

Where V A "qN aBW B2

# Si

This is known as Early effect (after Jim Early) and is usually modeled as


Preventing Base Width Modulation

Base width modulation is caused by the CBdepletion region growing into the base.

To prevent this, collector doping should be muchlower than base doping, so depletion region extendsmuch farther into the collector than into the base.

n+ Base

I C

p co ect.

p+ Emit.

VEB

V CB

n+ Base

IC

p o ect .

p+ Emit.

VEB

V CB


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13


Avalanche Multiplication and Breakdown

Base current is held constant in the common emitter conguration,

so the only place that excess electrons in the base (4) can go is intothe emitter. This produces an internal bias that causes an injectionof holes, I p = I n, which is regenerative and leads to a much lowerbreakdown voltage

P-N-P transistor

Breakdown!


I C =" dc

1 # " dc I B +

1

1 # " dc I CB 0

I C =" dc

1 # M " dc I B +

1

1 # M " dc I CB 0

The common expression for collector current

can be modied to account for the avalanche multiplication andresulting emitter injection by replacing dc by M dc

Since dc ~ 0.99, M need only be ~1.01 to have I C .Recall in PN junction avalanche, M 10-100 before I . Lower voltage for the onset of avalanche breakdown.

Collector doping must be light to prevent avalanchebreakdown. (Also prevents base width modulation.)


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14


IV. Low and High Current Level Effects on

Theoretically, T and are independent of V BE , implying thatthe ratio of collector current to base current (i.e., current gain ) is a constant, independent of V BE or I C . In practice, theratio of the two currents is NOT independent of I C .


In the P-N junction discussion, it has been shown that some

recombination of the carriers moving through the depletion

region will occur, and that (19)

where o = lifetime in the depletion region.1. This current ows in the B-E circuit and does not directly affect I C . Thus as

I REC becomes important, the ratio I C /I B decreases.

2. dependence important at low current levels.

E B C

einjection

recombination

holeinjection

*

I REC =qAniW E

" oeqV BE

/2 kT

eqV BE 2 kT

A. B-E Depletion Region Recombination

At low current levels, the dominant reason for the reduced isrecombination in the B-E depletion region.


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15


High Current Effects

A. High Level Injection in the BaseE B C

einjection

NdNa + n

If injection levels are very high, the assumption of n


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16


If the electrons are traveling at the saturated drift velocity, vsat , then at

any given time, the density of electrons in the depletion region is J/qv(x) ,hence the net charge density is

where N(x) = N d -N a

As a result there is excess negative charge on the base side of thedepletion region and less positive charge on the collector side. The netresult is that to maintain charge neutrality the depletion region shrinks inthe base side and widens in the collector side. As a result the neutral baseregion widens. This phenomenon is rst important in the collector sidebecause it is usually the most lightly doped.

X B ! and " #

" = N x( )# J qv ( x)


D. Base Resistance

The effective emitter bias becomes

V BE - I B R B

I C = I S exp qV BE ! I B R B

kT " # $

% & '


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17


E. Current Crowding

As I B and I C increase, the voltage drop across R B becomes signicant. This means that theeffective V BE across the active (center) portion of the device is not as great as the externallyapplied V BE . The edge of the emitter thus has the highest electron current density (currentcrowding). This plays a double role as the bandgap of the material shrinks with increasedtemperature, further increasing the injection around the emitter periphery. The totalcollector current decreases below the ideal eqV BE /kT behavior.

To minimize the impact of this(1) The emitter should be made narrower. For higher current capability multiple emitterscan be used in a single base.

(2) In the extrinsic base region a N + diffusion should be done.


Heterojunction Bipolar Transistor (HBT)

Motivation:Reduce I Ep by makinghole injection into theemitter more difcult.

Solution:Use different materials with differentbandgaps: Barrier to hole injection.

Si SiGe

Emitter BaseEc

Ev


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18


HBT Current Gain

" =1

1 + D E

D B

W

L E

N B

N E

n iE 2

n iB2

#

$ % %

&

' ( (

" ~#

1 $ # ~

D B

D E

L E

W

N E

N B

n iB

n iE

%

& '

(

) *

2

And if is limited by injection efciency, it becomes

And if g = 0.356 eV , thenn iB

n iE

"

# $ %

& '

2= 10 6

Which means N B can be 100-1000 N E and we still have very high current gain.

If we go back to eqs. (7) and (14) used to calculate the injection efciency,but do not cancel out the ni2 terms since they will be different when you havean emitter and base with different E gs. The injection ratio becomes


Big Wins for HBTs

1. Eliminates base width modulation because depletionregions are in the more lightly doped emitter and collectorregions

2. Current gain limited only by recombination in the E-B junction or the base

3. Current crowding and base resistance are greatly reducedbecause of high base doping

4. Completely eliminates Punch-thru due to high base doping5. Improved high frequency performance from decreased

base resistance and E-B capacitance


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19


VI. High Frequency LimitationsA. Base Transit Time

How long does it take from thetime a voltage is applied at theinput (E-B) until a voltage appearsat the output (CB) ?

E B Cn p

! 0

X

In the absence of elds in the base ( N aB = constant, low level injection), thenthe injected electron concentration varies linearly across the base The totalelectron charge in the base is

q B =1

2qAn p x B =

1

2qAn p o e

q V BE / kT ( )x B

I C =

qADnn po x B e

qV BE / kT " 1

( )Since

The transit time across the base is simply " B =q B I C

#x B

2

2 DnB(21)


If the base doping is graded (typical in IC BJTs), an aiding

eld speeds up the carriers and B is reduced.Also, under high level injection, to maintain baseneutrality, the hole concentration in the base and has agradient similar to the electron gradient. This sets up an eld which also speeds up the electron.

B is usually NOT the dominant frequency limitation inmodern BJTs.


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20


B. Emitter Capacitance Charging Time

E B C

reC je

From the earlier pn diode discussion,

C je depends upon the doping levels and current levels ( V BE )in the transistor. A rough approximation is that C je 2

C BE (0) where C BE (0) is the zero voltage B-E junctioncapacitance.

(22)

re =dV BE dI E

"kT qI E

! E = reC je "kT qI E

2 C BE 0( )


R c

C

E

B

C. Collector Capacitance Charging Time

The B-C junction is reverse biased so the junction impedanceis very high.

(23)

where

RC = collector series resistance

C = B-C depletion capacitance

" C = R C C


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21


D. Collector Depletion Layer Transit Time

For moderate or high B-C reverse biases, the eld acrossthe depletion layer is high, so the electrons can beassumed to move at V SAT

" D # x D BC 2 V SAT

(24)

Where x DBC = B-C depletion widthThe factor of 2 in the denominator is one of the mosterroneously quoted equations in semiconductor device physics.It arises because the carriers are moving by drift and a current

starts to appear at the output when the carriers just enter the baseside of the B-C depletion region


All of the time delays we have considered add, so that

(25)

The cutoff frequency of the device is simply

(26)

This is approximately the frequency at which isreduced to 1. Above this frequency, the device is notuseful as an amplier.

! TOT " ! B + ! E + ! C + ! D

f T =1

2 "# TOT


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22


VII. Ebers-Moll Model

(27)

(28)(29)

! R " R

"E "C

E C ! F " F

"B

B"F = "ES e

kTqVBE

1 "R = "C S ekT

qVBC

1

I E = " I F + # R I R

I C = " F I F # I R

I B = 1 " # F ( ) I F + 1 " # R( ) I R


where

F = forward alpha I C /I E if V BE is +ve and V BC is -ve

R = reverse alpha I E /I C if V BC is +ve and V BE is -ve

I ES = emitter reverse saturation current

I CS = collector reverse saturation current

The Ebers-Moll model may be used under all junction biasconditions (i.e., cut-off, forward active, reverse active andsaturation) to estimate the terminal currents.


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23


VIII. Hybrid Equivalent Circuit

A useful small signal , AC equivalent circuit for the BJTs inforward active region is shown below.

The parameters are dened as follows

(30)

d

B

E

C

C

C je

C

g m vbe

rb

r !

vbe

+

gm = transconductane =dI C

dV BE "

qI C kT


C d = Diffusion capacitance of the B-E Junction (due to storedminority carriers)

r"

= base/emitter resistance =dV BE dI B

#$

gmC je = depletion capacitance of B- E junction

C

= depletion capacitance of B- C junction

=

dq BdV BE

=

dq BdI C

dI C dV BE

= " Bgm

(31)

(32)

The DC current gain is " 0 = I C I B

= gm r#

Considering only the input E-B capacitance, the AC gain is

" =" 0

1 + j # r$ C $


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24


The AC gain decreases to 0.707 0 when or" r # C # = 1

f " =1

2 # r# C #

A more widely used measure is when the current gain goes to 1" r# C # = $ 0 = gmr# and

f % =gm

2 # C # &

1

2 #% EC

Even if the current gain is less than unity, the transistor canstill produce power gain due to the impedance transformationand the unity power gain or maximum frequency of oscillation

is f max =

f " 8 # r BC BC

$

% &

'

( )

12 This is the performance parameter

which is dramatically improved byHBTs because of the ability to heavilydope the base region and lower r B


BIPOLAR JUNCTION TRANSISTOR (BJT)

Strengths

1. Threshold Voltage controlled by E g (only very weakdependence on doping and process parameters)

2. Very high transconductance ( gm) and high nonlinearity Lower voltage swing in logic Lower sensitivity to parasitics

3. Vertical device (diffusion, ion implantation and epitaxy) areeasier to achieve small vertical dimensions than lithographyto achieve small lateral dimensions.

4. High current/unit area High drive capability for drivinglong off chip lines or for high current devices, such as LEDsor lasers


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25


BIPOLAR JUNCTION TRANSISTOR (BJT)

Weaknesses1. High Power relatively low levels of integration2. No effective complementary circuit technology3. Device based upon minority carriers charge storage and

diffusion rather than drift4. Difcult compromises for device optimization

Base resistance: RC time constants and transit time favor avery thin, highly doped base

high injection efciency requires N E >> N B Bandgap shrinkage, lower defect densities and E-B

capacitance all favor moderate emitter doping5. Far greater processing complexity, larger number of mask levels

with tight alignment tolerances on high performance devices.


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40/77

between collector and emitter, vCE .) As such, small changes in vBE or iB controls a muchlarger collector current iC . Note that the transistor does not generate iC . It acts as a valvecontrolling the current that can ow through it. The source of current (and power) is thepower supply that feeds the CE terminals.

C

vCE

BE

CB

i

+B

_

+

+_

_

v

vi

i E

A BJT has three terminals. Six parameters; iC , iB , iE , vCE , vBE , andvCB ; dene the state of the transistor. However, because BJT has threeterminals, KVL and KCL should hold for these terminals, i.e.,

iE = iC + iB vBC = vBE vCE

Thus, only four of these 6 parameters are independent parameters. The relationship amongthese four parameters represents the iv characteristics of the BJT, usually shown as iB vsvBE and iC vs vCE graphs.

The above graphs show several characteristics of BJT. First, the BE junction acts likes

a diode. Secondly, BJT has three main states: cut-off, active-linear, and saturation. Adescription of these regions are given below. Lastly, The transistor can be damaged if (1) alarge positive voltage is applied across the CE junction (breakdown region), or (2) productof iC vCE exceed power handling of the transistor, or (3) a large reverse voltage is appliedbetween any two terminals.

Several models available for a BJT. These are typically divided into two general categories:large-signal models that apply to the entire range of values of current and voltages, andsmall-signal models that apply to AC signals with small amplitudes. Low-frequency andhigh-frequency models also exist (high-frequency models account for capacitance of each junction). Obviously, the simpler the model, the easier the circuit calculations are. Morecomplex models describe the behavior of a BJT more accurately but analytical calculationsbecome difficult. PSpice program uses a high-frequency, Eber-Mos large-signal model whichis a quite accurate representation of BJT. For analytical calculations here, we will discuss asimple low-frequency, large-signal model (below) and a low-frequency, small-signal model inthe context of BJT ampliers later.

ECE60L Lecture Notes, Spring 2004 56


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A Simple, Low-frequency, Large Signal Model for BJT:

As the BE junction acts like a diode, a simple piece-wise linear model can be used :

BE Junction ON: vBE = v , and iB > 0

BE Junction OFF: vBE < v , and iB = 0

where v is the forward bias voltage ( v 0.7 V for Si semiconductors).

When the BE junction is reversed-biased, transistor is OFF as no charge carriers enter thebase and move to the collector. The voltage applied between collector and emitter has noteffect. This region is called the cut-off region:

Cut-Off: vBE < v , iB = 0 , iC iE 0

Since the collector and emitter currents are very small for any vCE , the effective resistancebetween collector and emitter is very large (100s of M) making the transistor behave asan open circuit in the cut-off region.

When the BE junction is forward-biased, transistor is ON. The behavior of the transistor,however, depends on how much voltage is applied between collector and emitter. If vCE > v ,the BE junction is forward biased while BC junction is reversed-biased and transistor is inactive-linear region. In this region, iC scales linearly with iB and transistor acts as anamplier.

Active-Linear: vBE = v , iB > 0,iC iB

= constant, v CE v

If vCE < v , both BE and BC junctions are forward biased. This region is called thesaturation region. As vCE is small while iC can be substantial, the effective resistancebetween collector and emitter in saturation region is small and the BJT acts as a closed-circuit.

Saturation: vBE

= v , i

B> 0,

iC iB

< , vCE

vsat

Our model species vCE vsat , the saturation voltage. In reality in the saturation region0 < v CE < v . As we are mainly interested in the value of the collector current in this region,vCE is set to a value in the middle of its range in our simple model: vCE vsat 0.5v .Typically a value of vsat 0.2 0.3 V is used for Si semiconductors.



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CE

i C

1 k

BEv

Bi

40 k v+

_+

_

i E

+

-4 V

12 VExample 1: Compute the parameters of this circuit ( = 100).

Following the procedure above:

BE-KVL: 4 = 40 103 iB + vBE

CE-KVL: 12 = 10 3 iC + vCE ,

Assume BJT is in cut-off. Set iB = 0 in BE-KVL:

BE-KVL: 4 = 40 103 iB + vBE vBE = 4 > v = 0 .7 V

So BJT is not in cut off and BJT is ON. Set vBE = 0 .7 V and use BE-KVL to nd iB .

BE-KVL: 4 = 40 103 iB

+ vBE

iB

=4 0.7

40, 000= 82 .5 A

Assume BJT is in active linear, Find iC = i B and use CE-KVL to nd vCE :

iC = i B = 100iB = 8 .25 mA

CE-KVL: 12 = 1 , 000iC + vCE , vCE = 12 8.25 = 3.75 V

As vCE = 3 .75 > v , the BJT is indeed in active-linear and we have: vBE = 0 .7 V, iB =82.5 A, iE iC = 8 .25 mA, and vCE = 3 .75 V.

CE

i C

i

i B

vBE

1 k

_

+

_

1 k

+v

40 k

E

-+

12 V

4 V

Example 2: Compute the parameters of this circuit ( = 100).

Following the procedure above:

BE-KVL: 4 = 40 103 iB + vBE + 103 iE

CE-KVL: 12 = 1 , 000iC + vCE + 1 , 000iE

Assume BJT is in cut-off.Set iB = 0 and iE = iC = 0 in BE-KVL:

BE-KVL: 4 = 40 103 iB + vBE + 103 iE vBE = 4 > 0.7 V

So BJT is not in cut off and vBE = 0 .7 V and iB > 0. Here, we cannot nd iB right awayfrom BE-KVL as it also contains iE .



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Assume BJT is in active linear, iE iC = i B :

BE-KVL: 4 = 40 103 iB + vBE + 103 i B

4 0.7 = (40 103 + 10 3 102 )iB

iB = 24 A iE iC = i B = 2 .4 mA

CE-KVL: 12 = 1 , 000iC + vCE + 1 , 000iE , vCE = 12 4.8 = 7.2 V

As vCE = 7 .2 > v , the BJT is indeed in active-linear and we have: vBE = 0 .7 V, iB = 24 A,iE iC = 2 .4 mA, and vCE = 7 .2 V.

Load line

The operating point of a BJT can be found graphically using the concept of a load line. Aload line is the relationship between iC and vCE that is imposed on BJT by the externalcircuit. For a given value of iB , the iC vCE characteristics curve of a BJT is the relationshipbetween iC and V CE as is set by BJT internals. The intersection of the load line with theBJT characteristics represent a pair of iC and vCE values which satisfy both conditions and,therefore, is the operating point of the BJT (often called the Q point for Quiescent point)

The equation of a load line for a BJT should include only iC and vCE (no other unknowns).This equation is usually found by writing a KVL around a loop containing vCE . For theexample above, we have (using iE iC ):

KVL: 12 = 1, 000iC + vCE + 1 , 000iE 2, 000iC + vCE = 12

An example of a load line, iC vCE characteristics of a BJT, and the Q-point is shown below.



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BJT Switches and Logic Gates

i C RC

CC

i

o

V

v

v

i B

i C

BR

RC

CC

i

o

V

v

v

The basic element of logic circuits is the transistor switch. Aschematic of such a switch is shown. When the switch is open,

iC = 0 and vo = V CC . When the switch is closed, vo = 0 andiC = V CC /R C .

In an electronic circuit, mechanical switches are not used. Theswitching action is performed by a transistor with an inputvoltage switching the circuit, as is shown. When vi = 0,BJT will be in cut-off, iC = 0, and vo = V CC (open switch).When vi is in high state, BJT can be in saturation withvo = vCE = V sat 0.2 V and iC = ( V CC V sat )/R C (closedswitch). When Rc is replaced with a load, this circuit can switch

a load ON or OFF (LED and motor drive circuits of ECE20ALab).

The above BJT circuit is also an inverter or a NOT logic gate. Lets assume that thelow states are voltages between 0 to 0.5 V, high states voltages are between 4 to 5 V,and V CC = 5 V. When the input voltage is low ( vi 0), BJT will be in cut-off andvo = V CC = 5 V (high state). When input voltage is high, with proper choice of RB ,BJT will be in saturation, and vo = vCE = V sat 0.2 V (low state).

Resistor-Transistor Logic (RTL)

The inverter circuit discussed above is a member of RTL family of logic gates. Plot of voas a function of vi is called the transfer characteristics of the gate. To nd the transfercharacteristics, we need to nd vo for a range of vi values.

When vi < v , BJT will be in cut-off, iC = 0 and vo = V CC . Therefore, for input voltagesbelow certain threshold (denoted by V IL ), the gate output is high. For our circuit, V IL = v .

When vi exceeds v , BE junction will be forward biased and a current iB ows into BJT:

iB =vi v

RB

As BE junction is forward biased, BJT can be either in saturation or active-linear. Letsassume BJT is is in saturation. In that case, vo = vCE = V sat and iC /i B < . Then:

iC =V CC V sat

RC iB >

iC

=V CC V sat

R C



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Therefore, BJT will be in saturation only if iB exceeds the value given by the formula above.This ouccrs when vi become large enough:

vi = v + RB iB > v + RB V CC V sat

R C = V IH

Therefore, for input voltages larger than the a certain value ( V IH ) , the gate output is low.

For vi values between these two limits, the BE junction is forward biased but the BJT isNOT in saturation, therefore, it is in active linear. In this case, the output voltage smoothlychanges for its high value to its low value as is shown in the plot of transfer characteristics.This range of vi is a forbidden region and the gate would not work properly in this region.

This behavior can also seen in the plot of the BJT load line. For small values of vi (iB = 0)BJT is in cut-off. As vi is increased, iB is increased and the operating point moves to theleft and up on the load line and enters the active-linear region. When iB is raised abovecertain limit, the operating point enters the saturation region.

i B

i C

BR

R1 i 1

i 2

RC

CC

i

o

V

v

v

A major drawback of the this RTL inverter gate is the limitedinput range for the low signal ( V IL ). Our analysis indicatedthat V IL = v , that is the gate input is low for voltages between 0and v 0.7 V. For this analysis, we have been using a piecewiselinear model for the BE junction diode. In reality, the BJTwill come out of cut-off (BE junction will conduct) at smaller

voltages (0.40.5 V). To resolve this shortcoming, one can adda resistor between the base and ground (or between base and anegative power supply) as is shown. (You have seen this circuitin ECE20A, motor drive circuit.)

To see the impact of this resistor, note that V IL is the input voltage when BJT is just leavingthe cut-off region. At this point, vBE = v , and iB is positive but very small (effectively



47/77

zero). Noting that a voltage vBE has appeared across R 1 , we have:

i1 =vBE R 1

i2 = iB + i1 i1 =vBE R1

V IL = vi = RB i2 + vBE = vBE RBR1 + vBE = v 1 +

RBR1

This value should be compared with V IL = v in the absence of resistor R 1 . It can be seenthat for RB = R 1 , V IL is raised from 0.7 to 1.4 V and for RB = 2R 1 , V IL is raised to 2.1 V.R 1 does not affect V IH as iB needed to put the BJT in saturation is typically several timeslarger than i1 .

RC

CC

o

BR BR

1 2

v

v

V

v

RTL NOR Gate

By combining two or more RTL inverters, one obtainsthe basic logic gate circuit of RTL family, a NORgate, as is shown. More BJTs can be added for addi-tional input signals. (You have seen in 20B that allhigher level logic gates, e.g., ip-ops, can be madeby a combination of NOR gates or NAND gates.)

Exercise: Show that this ia NOR gate, i.e., the gateoutput will be low as long as at least one of the inputsis high.

RTLs were the rst digital logic circuits using transistors. They were replaced with otherforms (DDT, TTL, and ECL) with the advent of integrated circuits. The major problemwith these circuits are the use of large resistors that would take large space on an IC chip (intodays chip, resistor values are limited to about 20 k and capacitance to about 100 pF).

Before we move on to more modern gates, we consider two important characteristics of adigital gate.



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Switching Time and Propagation Delay:

Consider the inverter gate with an input voltage close to zero (and/or negative). In thiscase, the BJT is in cut-off, iC = 0 and the output of the gate is high. Suppose a highvoltage is applied instantaneously to the gate at some point. We expect BJT to entersaturation with iC = I Csat and output to drop to the lowstate. However, this does notoccur instantaneously.

When the BJT is in cut-off, BE junctionis reversed biased. When a forward volt-age is applied to the BE junction, it takessome time for the BE junction transitioncapacitance to charge up. Time is also re-quired for minority carries to diffuse across

the base and enter the collector. This re-sults in the delay time td , which is of theorder of a nanosecond for a typical BJT.

Before BJT can enter saturation, it should traverse the active-linear region. The rise time,t r (on the order of 1-10 ns) account for this transition. The time that takes for the gate toswitch ON is represented by ton .

Suppose that the input voltage to gate is then reduced instantaneously to low state. BJTwill leave saturation region and go to cut-off. Again, this not occur instantaneously. Whena BJT is in saturation, both BE and BC junctions are forward biased and conducting. Assuch, an excess minority charge is stored in the base. For the transistor to leave saturationand enter active-linear (BC junction to become reversed biased), this excess charge must beremoved. The time required for the removal of excess charge determines the storage time, t s(order of 100 ns). Then, transistor traverses the active-linear region before entering cut-off.This account for the fall time t f (1-10 ns). The total time it takes for the gate to switchOFF is represented by toff . As can be seen, BJT switching is mainly set by the storagetime, ts .

Propagation delays introduced by transistor switching time are important constraints indesigning faster chips. Gate designs try to minimize propagation delays as much as possible.

Fan-out: All digital logic circuits are constructed with cross-coupling of several basic gates(such as NOR or NAND). As such, a basic gate may be attached to several other gates.The maximum number of gates that can be attached to a digital gate is called fan-out.Obviously, one would like to have large fan-out.



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Case 3, v1 = 5 V, v2 = 0 V: Because of the symmetry in the circuit, this is exactly thesame as case 2 with roles of D1 and D 2 reversed.

So, when v1 is high and v2 is low, D1 is OFF and D 2 is ON and vo is low.

Case 4, v1

= v2

= 5 V: Examining the circuit, it appears that the 5-V supply will NOTbe able to forward bias D 1 and D 2 . Assume D1 and D 2 are OFF: i1 = i2 = 0, vD 1 < v andvD 2 < v . Then:

iA = i1 + i2 = 0

vo = V CC i1 RA = 5 0 = 5 V

vD 1 = vo v1 = 5 5 = 0 < v and vD 2 = vo v2 = 5 5 = 0 < v

Thus, our assumption of both diodes being OFF arejustied.

So, when v1 and v2 are high, D 1 and D 2 are OFF and vo is high.

Overall, the output of this circuit is high only if both inputs are high (Case 4) and the outputis low in all other cases (Cases 1 to 3). Thus, this is an AND gate. This analysis can beeasily extended to cases with three or more diode inputs.

DTL NAND Gate:

The basic gate of DTL logic circuits is a NAND gate which is constructed by a combinationof a diode AND gate and a BJT inverter gate as is shown below (left gure). Because RB islarge, on ICs, this resistor is usually replaced with two diodes. The combination of the twodiodes and the BE junction diode leads to a voltage of 2.1 V for the inverter to switch anda V IL = 1 .4 V for the NAND gate (Why?). Resistor R 1 is necessary because without thisresistor, current iB will be too small and the voltage across D 3 and D 4 will not reach 0.7 Valthough they are both forward biased (Recall LED driver circuit of ECE20A in which theLED started to lit for vin about 0.8 V instead of estimated 1.4 V).

RA

1

1

A

2

2

1

2

i B

i C

BR

RC

CC

o

D

i

D

i

i

v

v

V

vi B

i C RC

CC

o

R 1

RA

1

A

2

2

1

2

1 3 4D

i

D

i

i

D D

V

v

v

v



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DTLs were very popular in ICs in 60s and early 70s but are replaced with Transistor-Transistor Logic (TTL) circuits. TTL are described later, but as TTLs are evolved fromDTLs, some examples of DTL circuits are given below.

i B

i C

1

CC

o

2

2

1

2

1 3 4

5

A

34

D

i

D

i

i

D D

ii

5k

5k

1k

v

V

v

v

v

Example: Verify that the DTL circuit shown isa NAND gate. Assume that lowstate is 0.2 V,high state is 5 V, and BJT min = 40.

Case 1: v1 = v2 = 0 .2 V It appears thatthe 5-V supply will forward bias D 1 and D 2 .Assume D1 and D 2 are forward biased: vD 1 =vD 2 = v = 0 .7 V and i1 > 0, i2 > 0. In thiscase:

v3 = v1 + vD 1 = v2 + vD 2 = 0 .2 + 0.7 = 0.9 V

Voltage v3 = 0 .9 V is not sufficient to froward bias D 3 and D 4 as v3 = vD 3 + vD 4 + vBE and weneed at least 1.4 V to forward bias the two diodes. So both D 3 and D 4 are OFF and i4 = 0.(Note that D 3 and D 4 can be forward biased without BE junction being forward biased aslong as the current i4 is small enough such that voltage drop across the 5 k resistor parallelto BE junction is smaller than 0.7 V. In this case, i5 = i4 and iB = 0.) Then:

i1 + i2 = iA =5 v35, 000

=5 0.95, 000

= 0 .82 mA

And by symmetry, i1 = i2 = 0 .5iA = 0 .41 mA. Since both i1 and i2 are positive, ourassumption of D 1 and D 2 being ON are justied. Since i4 = 0, iB = 0 and BJT will be incut-off with iC = 0 and vo = 5 V.

So, in this case, D1 and D 2 are ON, D 3 and D 4 are OFF, BJT is in cut-off, and vo = 5 V.

Case 2: v1 = 0 .2 V, v2 = 5 V Following arguments of case 1, assume D 1 is ON. Again,v3 = 0 .7 + 0 .2 = 0.9 V, and D 3 and D 4 will be OFF with i4 = 0. We nd that voltage acrossD2 is vD 2 = v3 v2 = 0 .9 5 = 4.1 V and, thus, D 2 will be OFF and i2 = 0. Then:

i1 = iA = 5 v35, 000= 5 0.9

5, 000= 0 .82 mA

and since i1 > 0, our assumption of D 1 ON is justied. Since i4 = 0, iB = 0 and BJT willbe in cut-off with iC = 0 and vo = 5 V.

So, in this case, D1 is ON, D2 is OFF, D 3 and D 4 are OFF, BJT is in cut-off, and vo = 5 V.



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Case 3: v1 = 5 V, v2 = 0 .2 V Because of the symmetry in the circuit, this is exactlythe same as case 2 with roles of D1 and D 2 reversed.

So, in this case, D1 is OFF, D 2 is ON, D3 and D 4 are OFF, BJT is in cut-off, and vo = 5 V.

Case 4: v1 = v2 = 5 V Examining the circuit, it appears that the 5-V supply will NOTbe able to forward bias D 1 and D 2 . Assume D1 and D 2 are OFF: i1 = i2 = 0, vD 1 < v andvD 2 < v . On the other hand, it appears that D 3 and D 4 will be forward biased. Assume D 3and D 4 are forward biased: vD 3 = vD 4 = v = 0 .7 V and i4 > 0. Further, assume the BJT isnot in cut-off vBE = v = 0 .7 V and iB > 0. In this case:

v3 = vD 3 + vD 4 + vBE = 0 .7 + 0 .7 + 0.7 = 2.1 V

vD 1 = v3 v1 = 2 .1 5 = 2.9 V < v vD 2 = v3 v2 = 2 .1 5 = 2.9 V < v

Thus, our assumption of D 1 and D 2 being OFF are justied. Furthermore:

i4 = iA =5 v35, 000

=5 2.15, 000

= 0 .58 mA

i5 =vBE

5, 000=

0.75, 000

= 0 .14 mA

iB = i4 i5 = 0 .58 0.14 = 0.44 mA

and since i4 > 0 our assumption of D 3 and D 4 being ON are justied and since iB > 0 ourassumption of BJT not in cut-off is justied.

We still do not know if BJT is in active-linear or saturation. Assume BJT is in saturation:vo = vCE = V sat = 0 .2 V and iC /i B < . Then, assuming no gate is attached to the circuit,we have

iC =5 V sat1, 000

=5 0.21, 000

= 4 .8 mA

and since iC /i B = 4 .8/ 0.44 = 11 < = 40, our assumption of BJT in saturation is justied.

So, in this case, D1 and D 2 are OFF, D 3 and D 4 are ON, BJT is in saturation and vo = 0 .2 V.

Overall, the output in low only if both inputs are high, thus, this is a NAND gate.

Note: It is interesting to note that at the input of this gate, the current actually ows outof the gate. In the example above, when both inputs were high i1 = i2 = 0, when both werelow i1 = i2 = 0 .4 mA, and when one input was low, e.g., v1 was low, i1 = 0 .8mA. The inputcurrent owing in (or out of the gate in this case) has implications for the fan-out capabilityof logic gates as is shown in the example below.



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Example: Find the fan-out of this NAND DTL gate. Assume that lowstate is 0.2 V,high state is 5 V, and BJT = 40.

i B i C

CC

o

1

2

2

1

2

1 3 4

5

A

i R

4

L

D

i

D

i

i

D D

ii

5k

5k

Other gates

i

i

1k

V

v

v

v

The circuit is the same DTL NAND gate of previous example and we can use results fromprevious example here. N other NAND gates are attached to the output of this gate.Fan-out is the maximum value of N . Since we want to make sure that our gate operatesproperly under all conditions, we should consider the worst case, when all of the second stagegates have maximum currents.

For a NAND DTL gate, the maximum current i occurs when all of the inputs are high withexception of one input. We found this value to be 0.82 mA (Cases 2 & 3 in the previousexample). Therefore, the worst case is when the input of all second stage gates are low (forthe rst stage, vo = 0 .2 V) and each draw a current 0.82 mA (a total of iL = N 0.82 mAis drawn from the rst stage gate).

Considering the rst stage gate, we had found that vo = 0 .2 V only for Case 4. For thatcase, we found iB = 0 .44 mA. Then:

iR =5 V sat1, 000

=5 0.21, 000

= 4 .8 mA

iC = iR + 0 .82N = 4 .8 + 0 .82N

The rst stage gate operates properly as long as the BJT is in saturation, i.e.,

iC < i B 4.8 + 0 .82N < 40 0.44 N < 13.7

As the fan-out should be integer, the fan-out for this gate is 13.Fan-out of DTL gates can be greatly increased by a small modication. Fan-out can beincreased by increasing the base current of the BJT. iB is, however, limited by the current iA(and i4 ). Reducing the value of RA in the AND diode part of the circuit will have increaseiB . Unfortunately, as this resistor is reduced, power dissipation in the gate increases and thefan-out capability decreases dramatically.



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i B

i C

CC

R

1

A

22

1

2

1

RC

o

R 1

4

A

D

i

D

i

iD

V

v

v

v

A simple solution which keeps current iA smallbut increases iB drastically is to replace diode D 3with a BJT as is shown. As can be seen, the DTLNAND gate is now made of 3 stages: 1) inputstage (diodes), 2) driver stage (rst BJT) and 3)

output stage (2nd BJT).

Circuit Symbol

2

1

CC

i B

i C

R 1

A

RC

o

R 2RAi

v

v

V

v

Transistor-Transistor Logic (TTL)

A simplied version of an IC-chip NPN transistor is shown.The device is fabricated on a p-type substrate (or body) ina vertical manner by embedding alternating layers of N andP-type semiconductors. By embedding more than one N-

type emitter region, one can obtain a multiple-emitter NPNtransistor as shown. The multiple-emitter NPN transistorscan be used to replace the input diodes of a DTL NANDgate and arrive at a NAND gate entirely made of transistors,hence Transistor-Transistor Logic (TTL) gates.

A simple TTL gate is shown with the multiple-emitter BJTreplacing the input diodes. This transistor operates inreverse-active mode, i.e., like a NPN transistor in active-linear mode but with collector and emitter switched. Oper-

ationally, this BJT acts as two diodes back to back as shownin the circle at the bottom of the gure. As such the oper-ation of this gate is essentially similar to the DTL NANDgate described above (note position of driver transistor andD4 diode is switched).

Similar to DTL NAND gates, a typical TTL NAND gatehas three stages: 1) Input stage (multi-emitter transistor),2) driver stage, and 3) output stage. Modern TTL gatesbasically have the same conguration as is shown with the

exception that the output stage is replaced with the Totem-Pole output stage to increase switching speed and gate fan-out. For a detailed description of TTL gate with Totem-Pole output stage, consult, Sedra and Smith (pages 1175to 1180).



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5.9. Bipolar Power Devices

Power devices can be classified into bipolar-based devices, MOSFET-based devices and devicessuch as the IGBT that combine a bipolar transistor with a MOSFET.

Bipolar power devices are the traditional power devices because of their capability to provide

high currents and high blocking voltages. The bipolar-based power devices include high-powerbipolar transistors, Darlington transistors consisting of two transistors with a common collector,thyristors also called silicon controlled rectifiers (SRCs) and triacs, a complementary thyristorstructure suitable to control AC power.

Power MOSFETs and power devices that combine MOSFETs and bipolar transistors are coveredin chapter 7.

5.9.1. Power BJTs

High power bipolar transistors are conceptually the same as the bipolar transistors described inchapter 8. The main difference is that the active area of the device is distinctly higher, resultingin a much higher current handling capability. Power BJTs also have a thick and low-dopedcollector region. Such collector regions result in a large blocking voltage. Extremely low dopingdensities, down to 10 13 cm-3 , are use to obtain blocking voltages as large as x000 V. As a result,one finds that the structure needs to be redesigned to a) effectively manage the power dissipationand b) avoid the Kirk effect.

The power dissipation is managed by minimizing the power dissipation and spreading theresulting heat dissipation onto a large area. The Kirk effect is normally avoided by increasing thecollector doping density. However, for devices with a very high blocking voltage, this may notbe an option. Power BJTs therefore are operated at rather low current density of 100 A/cm 2 since the lower current density reduces the power dissipation per unit area and eliminates the

Kirk effect. Large currents up to 1000 A are obtained by making a large area device. SiliconBJTs dominate the power device market, in part because of the low cost of large area silicondevices and the high thermal conductivity of silicon compared to GaAs. Silicon carbide (SiC)has been hailed as the perfect material for high-power BJTs. The higher thermal conductivity(3x) and breakdown field (10x) compared to silicon give it a clear performance advantage. Thehigh saturation velocity (3x compared to silicon) also shifts the onset of the Kirk effect to highercurrent densities. The proliferation of its use will heavily depend on the material cost and qualityof the SiC wafers.

5.9.2. Darlington Transistors

Darlington transistors contain two transistors connected in an emitter-follower configuration,while sharing the same collector contact. This structure can be fabricated with the sametechnology as a single BJT as shown in Figure 5.9.1. The key advantage of the Darlingtonconfiguration is that the total current gain of the circuit equals the product of the current gain of the two devices. The disadvantage is the larger saturation voltage. Since the two devices sharethe same collector, the saturation voltage of the Darlington pair equals the forward bias voltageof transistor Q2 plus the saturation voltage of transistor Q1. Since the forward bias voltage ismuch larger than the saturation voltage, the saturation voltage of the Darlington pair is alsosignificantly larger. This larger voltage results in a larger on-state power dissipation in thedevice.


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a) b)

Figure 5.9.1. Darlington transistor structure a) equivalent circuit b) device crosssection.

5.9.3. Silicon Controlled Rectifier (SRC) or Thyristor

The silicon controlled rectifier is 4-layer device with alternating n-type and p-type layers asshown in Figure 5.9.2. This devices is also referred to as a pnpn structure or Thyristor. Suchdevice can in principle be made using any semiconductor. However, silicon thyristors are themost common thyristors. The advantage of the structure is that it provides a high power handlingcapability, high blocking voltage and high gain with a very low on-state resistance.

The operation of the device is best explained by considering the equivalent circuit, shown inFigure 5.9.2. It consists of two bipolar transistors, a n-p-n transistors, Q1, and a p-n-p transistor,Q2. Both transistors share a p-type and n-type layer. For instance, the p-type base layer of transistor Q1 is also the collector layer of transistor Q2, while the n-type base of transistor Q2 isalso the collector of transistor Q1. The Thyristor is controlled by the gate electrode, which is thegate of Q1. By applying a current to the gate one forward biases the base-emitter junction of Q1,which leads to a collector current in Q1, which in turn provides a base current to Q2. Since Q2 isa complementary p-n-p transistor, this negative current also forward biases the base-emitter

junction of transistor Q2, resulting in collector current which forms an additional base currentinto the base of transistor Q1. The applied current to the gate of the Thyristor therefore causes anadditional current into Q1, which can be large enough that both transistors remain in turned oneven if the original gate current is removed. This latching behavior is not unlike that of a flip-flop, where the inputs of two devices are connected to the output as shown in Figxxx. This self-sustaining effect will occur if the product of the current gain of both transistors equals unity,while one of the transistors can have a current gain less than unity. As a result one hasconsiderable flexibility to choose the doping density and thickness of each of the layers to obtaina high blocking voltage and high Early voltage for each transistor, while maintaining sufficientcurrent gain.

The Thyristor has a lower on-state voltage than the Darlington pair and typically requires an

n+ substrate

Collector

p n+

Base Emitter

n -

n+p

Base

Emitter

Collector

Q1

Q2

Q1 Q2

n+ substrate

Collector

p n+

Base Emitter

n -

n+p

Base

Emitter

Collector

Q1

Q2

Q1 Q2


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even smaller turn-on current, which only needs to be applied temporarily because of the internalpositive feedback between the two transistors of the equivalent circuit.

This latter property is also the main disadvantage of the Thyristor: since the device latches intothe on-state once sufficient gate current is supplied, the device can not be turned off by removingthe gate current. Instead one has to disconnect the power supply to turn off the device.Furthermore, since both transistors are in saturtion in the on-state, a significant amount of

minority carriers are accumulated in the base region of each transistor. These minority carriersmust be remove prior to reconnecting the power supply since these carriers would temporarilylead to a base current in each device and trigger the turn-o of the Thyristor. Finally, one has toslowly ramp up the power supply voltage to avoid the so-called dV/dt effect. Since a rapidincrease of the applied voltage with time causes a displacement current proportional to thecapacitance of the junctions, this displacement current could again provide a temporary basecurrent in Q1 and Q2, which is large enough to trigger the Thyristor.

Figure 5.9.2. Thyristor structure: a) circuit symbol, b) device cross-section and c) equivalentcircuit.

A very attractive feature of a Thyristor is that it can be scaled easily to very large area deviceseven if that causes a significant lateral resistance though the thin and lowly-doped base andcollector regions. As one applies a current to the gate electrode, the Thyristor would be triggeredlocally. The turned-on region would then spread laterally thoughout the structure without a needfor an additional gate current. The local triggering also exists in the light-controlled Thyristor.This structure does not contain a gate electrode. Instead the p-n-p-n structure is locallyilluminated with photons whose energy exceeds the bandgap energy of the semiconductor. Thephotogenerated current then acts as the gate current, which triggers the Thyristor.

Gate turn-off Thyristor (GTO)

5.9.4. DIode and TRiode AC Switch (DIAC and TRIAC)

The diode AC switch and the triode AC switch are very similar to the thyristors, since they bothare latching multi-layer device structures. Both are meant to be used in AC powered systems andtherefore respond similarly to positive and negative applied voltages. The circuit symbols andlayer structures are shown for both devices in Figure 5.9.3. The diode AC switch also referred to

Anode

p

n+

Gate

n

p+ substrate

Cathode

p+

Gate

Anode Cathode

Anode

Cathode

Q1

Q2

Gate

Q1

Q2

Anode

p

n+

Gate

n

p+ substrate

Cathode

p+

Gate

Anode Cathode

Anode

Cathode

Q1

Q2

Gate

Q1

Q2


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as DIAC consists of a gate-less pnpn structure connected in parallel to a gate-less npnp structure.This device therefore acts like an open circuit until the threshold voltage is reached - eitherpositive or negative after which the device acts as a short. To achieve this function one startswith a pnp structure. An n + region is added to the front and the back to yield the DIAC structure.

The triode AC switch (TRIAC) also contains the same vertical structure as a DIAC. In addition acontact is made to the p-type gate of the npnp structure as well as the n-type gate of the pnpnstructure. This additional gate contact allows lowering the threshold for latching for both positiveand negative applied voltages applied between terminal 1 and terminal 2.

Figure 5.9.3. Circuit symbol and device cross-section of a) a Diode AC switch (DIAC) and b) aTriode AC switch (TRIAC).

Terminal 2

pn+

Gate

n

n+p

Terminal 1

n+

Gate

Terminal 1 Terminal 2

Terminal 2

pn +

n

n+p

Terminal 1


Terminal 2

pn+

Gate

n

n+p

Terminal 1

n+

Gate


Terminal 2

pn +

n

n+p

Terminal 1



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PHY2003 (Practical Electronics II) Homework Worksheet 9

1

I C I B

I E

V C

V B

V E

I E I B

I C

V E

V B

V C

NPN PNP

Figure 9.1 Current conventions Circuit 9.1 Common Emitter Amplifier

+12V

R1 R2

X1

C1

V 12

3 V 3

R1 1MR2 3K3C1 10NX1 BC107


Introduction

PHY2003 does not require a knowledge of the semiconductor physics underlying how transistors

work, they are treated as nonlinear three-terminal devices. Figure 1 defines the current conventions

used in PHY2003. The rules-of-thumb for analysing bipolar junction transistor (BJT) circuits at low-

frequencies are:

NPN: V C > V B = V E + 0.6 VPNP: V C < V

B= V

E 0.6 V

(9.1)

if NPN: V B < V E + 0.6 VPNP: V B > V E 0.6 V

then I C = 0 else I C = h FE I B (9.2)

typically 50 < h FE < 500 therefore I E I C . (9.3)

Required Reading

Storey (1998) chapter 7, sections 7.17.6, pages 234287.

Another source of the required information are the WWW references listed under:


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PHY2003 (Practical Electronics II) Homework Worksheet 9

2

V 1

2

3

4

R1

R2

R3

R4

X1

C1

12V

C1 01R1 33KR2 10KR3 2K7R4 1K0X1 BC107

V 4

Circuit 9.2 Series Feedback Amplifier

Copyright CDH WilliamsUniversity of Exeter 2003CW030907/1

Exercise 9.1 Analyse circuit 9.1 using typical values from the BC107 datasheet and find:

(a) the quiescent voltage at node 3,

(b) the DC impedance of node 2 and hence the low-frequency 3 dB point

(c) the small-signal voltage gain v3 v1 at 1 kHz and 10 kHz.

Answers: (a) 6.4 V (assuming HFE = 150) (b) 2.2 k , 7.2 kHz (c) 60 and 400

Exercise 9.2 Analyse circuit 9.2 using typical values from the BC107 datasheet and find:

(a) the quiescent voltage at node 3

(b) the quiescent voltage at node 4

(c) the small-signal gain v4 v1 at 1kHz

Answers: (a) 2.1 V (b) 6.3 V (b) 60 and 400 (c) v4 v1 = 2.7


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University of Geneva TPA-Electronique

Circuits with Transistors

Contents

1 Transistors 1

2 Ampliers 22.1 h parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3 Bipolar Junction Transistor (BJT) 33.1 BJT as a switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.2 Small signal BJT ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.2.1 r parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.2.2 Common Emitter Amplier . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2.3 Common Collector Amplier . . . . . . . . . . . . . . . . . . . . . . . . 103.2.4 Common Base Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Field Effect Transistors (FET) 114.1 Small signal FET ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Power ampliers 115.1 Class A power ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1.1 Voltage and power gain . . . . . . . . . . . . . . . . . . . . . . . . . . 125.1.2 Power gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125.1.3 Efciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.2 Class B and class AB power ampliers . . . . . . . . . . . . . . . . . . . . . . 135.2.1 Efciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3 Class C power ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Differential amplier 156.1 Two inputs and two ouputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156.2 One input and two ouputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176.3 Two inputs and one ouputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176.4 One input and one ouput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Darlington and Sziklai connections 17

1 Transistors

Transistors are three terminal semicounductor amplifying device that regulates current orvoltage. A small change in the current or voltage at an inner semiconductor layer (whichacts as the control electrode) produces a large, rapid change in the current passing throughthe entire component. The component can thus act as a switch, opening and closing anelectronic gate. A transistor is a active device that can amplify, producing an output signalwith more power in it than the input signal

E. Cortina Page 1


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v1

i1 2 h

11

h12

v2

v2

h21

i

i1

h22

Figure 2: h parameters denition

2.1 h parameters

An amplier can be seen as a quadrupole. h parameters cames from a direct application ofThevenin theorem to the input dipole and Norton theoreme to the output dipole. See gure2.

The Kirchoff equations for this model are:

v1 = h 11 i1 + h12 v2

i2 = h21 i1 + h22 v2

If the output is short-circuited v2 = 0 then

h11 = v1i 1 = h i input impedance

h21 = i 2i 1 = hf current gain

If the input is open i1 = 0

h12 = v1v2 = hr inverse voltage gain

h22 = i 2v2 = ho output admitance

These four last relations gives the meaning of the h parameters. Beware, that the mean-ing is with the conditions imposed up, that is, output short-circuit (no load) and open input(no input). Typical values of these parameters are:

h11 = 3 .5k

h12 = 1 .3 10 4

h21 = 120

h22 = 8 .5S

3 Bipolar Junction Transistor (BJT)

A bipolar junction transistor is a device based in three area semiconductor material with twodiode junction. There are two types of BJT, the so called npn and pnp transistors, dependigobviously on doping of each area. It is called bipolar because both electrons and holes areinvolved in its operation. The trhee regions are called emiter , base and collector . In gure 3are shown both types of BJT and the majority current ow.

In order to show the transistor effect, the diode polarization should be correct, that is, theemitter-base is in forward bias and the base-collector in reverse bias. In a NPN transistor:

E. Cortina Page 3


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base

V VEE CC

emiter collector

n np+

forward biased reverse bias

II = Ic e

= (1 ) e

e

b

b

ce

b

ce

II = Ic e

= (1 ) e

e

b

base

V VEE CC

emiter collector

+p n p

Figure 3:

a) Electrons are majoritary carriers in the emitters, so they can pass with no problemsto the base. As the emitter is intended to provide the charge carriers will be heavelydoped.

b) The base is slightly doped and made very thin. This allows that the recombinationcurrent, that will exit by the base is small and that the diffussion length is longer than

the base length and consequently almost all electrons from emitter will pass to thecollector

c) Once in the collector, the electrons will exit by the lead.

For PNP transistors the explanation is exactly the same just changing electrons for holesand inversing the currents.

In order to study the transistor we are going to mount the so called common emitterconguration. In gure 4 is shown how this conguration.

The parameters cc and cc , dened for direct current are:

cc =I C I E 0.99

cc =I C I B

100

I E = I B + I C cc = cc

1 ccIn the right side of the gure 4 have been plotted a family of characterisic courbes of atransistor. For a xed value of V BB , that x I B , we can increase V CC from 0V. For lowervalues of V CC both diodes are forward bias so V CE will increase accordingly, this region iscalled saturation. With V CC high enough will enter in the active or linear region, where thebase-collector jounction is reverse bias. At this moment I C becames stable (or almost) and

E. Cortina Page 4


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R b

R c

VCEV

BE

VCB

VCC

VBB

v s

+

+

I B1

BI = 0

IB2

I B3

IB4

I B5

IB6

I B7

I B8

VCE

I C

Blockage region

S a

t u r a

t i o n

r e g e

i o n

Breakdown region

Figure 4: Transistor charactersitic curves I B 1 < I B 2 < I B 3 ,etc

E. Cortina Page 5


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I C

VCE

I c

I CQI BQ

Q

B

A

VCEQ

Vce

I b

Figure 5: Q point. Variations induced in collector current I C and V CE by a variation of thebase current I B

does not change with V CE . In fact, I C increas just a bit due to the larger depletion region inthe base-collector junction. So in this region the value of I C is controlled by I B in such a waythat I C = CC I B . With V CE large enough the base-collector junction breakdown increasingI C quickly. Note that if I B = 0 then I C = 0 so the transistor does not conduct. In this situationthetransistor is in the so called blockage state.

Applying directly Kirchoffs laws to the circuit we can nd directly in the output circuit thatthe summation of voltages around the loop gives

V CC

I C RC

V CE = 0

I C =V CC RC

1RC

V CE

this is the equation of a straight line, known as load line. Superimposing the load line on theoutput characteristics in effect gives us a graphical solution to two simultaneous equations:one equation, belonging to the transistor, non-linear equation given by the family of I C V CE graphs, and the other the load line. The intersection points show the possible values thatmay exist in the circuit. In absence of the any input signal, vs = 0 , the operational point iscalled Q-point. In case of an input signal provoques the variation of the V CE value, modiyngconsequently the operational point. In gure 5 is shown how the operational point moves in

the transistor characteristic-plot.

3.1 BJT as a switch

One of main utilities of BJT are as electronic switches. If the transistor is in blockage, thenthe transistor can be seen as an open circuit. On the other hand, if the transistor is insaturation, then the transistor can be seen as a closed circuit.

3.2 Small signal BJT ampliers

We can found three types of small signal BJT amplier congurations as shown in gure 7:

E. Cortina Page 6


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0 V

R

I = 0

I = 0

B

R R

B

C C C

C

E

+VCC

+VCC

RB

R RC C

C

E

+VCC

+VCC

sat

+VBB

IC

IB

Figure 6: Transistor view as an electronic switch

Common Emitter. From AC point of view the emitter is connected to the ground. Inputsignal is in the base and output in the collector

Common Collector. From AC point of view the collector is connected to the ground.Input signal is in base and output in the emitter.

Common base. From AC point of view the base is connected to the ground. I

ECE 1201 BJT Transistors

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